CN104506191A - Correcting circuit and correcting method for assembly line analog-digital converter based on zero-crossing comparison - Google Patents
Correcting circuit and correcting method for assembly line analog-digital converter based on zero-crossing comparison Download PDFInfo
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- CN104506191A CN104506191A CN201410754786.6A CN201410754786A CN104506191A CN 104506191 A CN104506191 A CN 104506191A CN 201410754786 A CN201410754786 A CN 201410754786A CN 104506191 A CN104506191 A CN 104506191A
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Abstract
The invention belongs to the technical field of integrated circuits, and particularly relates to a correcting circuit and a correcting method for an assembly line analog-digital converter based on zero-crossing comparison. The correcting circuit provided by the invention is connected between two stages of circuits of the assembly line analog-digital converter based on zero-crossing comparison, and the correcting circuit comprises a difference 1/f error amplifier, two capacitors for correction and two transmission gate circuits; each transmission gate circuit comprises an N-type field effect transistor and a P-type field effect transistor, and the channels of the N-type field effect transistor and the P-type field effect transistor are arranged in parallel. The correcting circuit is used for amplifying the error of the former stage of circuit and storing on the capacitors for correction, and then the error is compensated for output along with the setup process of the next stage of circuit. According to the correcting method provided by the invention, the conversion accuracy of the circuit can be effectively improved, meanwhile the conversion time longer than that of a traditional scheme is provided for sub-ADC (Analog to Digital Converter), and thus the speed requirement of a sub-ADC circuit can be reduced.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of production line analog-digital converter correcting circuit and bearing calibration.
Background technology
Be the popular scheme of one realizing production line analog-digital converter in recent years based on Zero-cross comparator, its adjacent two-stage differential circuit as shown in Figure 1.Similar to traditional switch electric capacity gain stage, the process that the differential switched capacitor gain stage based on Zero-cross comparator realizes differential signal with the expense of single-end circuit twice.The circuit structure of upper and lower two parts symmetry forms positive and negative two passages, processes positive input and the negative input of differential input signal respectively, and draws final difference output result.Fig. 1 mainly comprises the sampling capacitance C of N level circuit 101
1 ±and C
2 ±103 ~ 106, the sampling capacitance C of N+1 level circuit 102
3 ±and C
4 ±107 ~ 110, the sampling switch M of N level circuit 101
1111, the sampling switch M of N+1 level circuit 102
4112, the positive channel presetting transistor M of N level circuit 101
2113, the negative channel presetting transistor M of N level circuit 101
3114, the current source I mated up and down
1 ±, I
2 ±115 ~ 118 and I
3 ±, I
4 ±119 ~ 122, and the difference zero-crossing comparator 100 of centre.Circuit realizes the inswept whole output area of output voltage by current source to output node discharge and recharge, and difference zero-crossing comparator 100 realizes the function detecting " empty short " state.
The course of work of foregoing circuit is as follows.Work as φ
1when being in high potential, N level circuit 101 is in sample phase, switch φ
1closed, switch φ
2disconnect, Differential Input is sampled the sampling capacitance C in N level circuit 101
1 ±and C
2 ±on 103 ~ 106.Work as φ
2when being in high potential, N level circuit 101 enters charge transfer phase, and N+1 level circuit 102 enters sample phase, the sampling capacitance C in N+1 level circuit 102
3 ±and C
4 ±107 ~ 110 as the load capacitance of N level circuit 101, the output V of N level of sampling circuit 101
o ±.Enter the beginning of charge transfer phase at N level circuit 101, have a bit of preset stage φ
2I.In preset stage, the sampling capacitance C of N+1 level circuit 102
3 ±and C
4 ±the interior side gusset of 107 ~ 110 can be connected to common mode electrical level, and the positive output node of N level circuit can by positive channel presetting transistor M
2113 discharge into system potential minimum, and the negative output node of N level circuit can by negative channel presetting transistor M
3114 are charged to supply voltage, thus achieve the initialization of the sampling capacitance 107 ~ 110 to N+1 level circuit 102.After preset stage terminates, φ
2Ijump to electronegative potential, respective transistor 113,114 all turns off.The current source I be made up of pMOS pipe
3 ±119,121 charge to the positive output node of N level circuit, the current source I be made up of nMOS pipe
4 ±120,122 by the negative output node discharge to N level circuit.In the ideal case, upper and lower Current-source matching and charging and discharging currents is constant, output node is also fixed to the equivalent capacity on ground, and therefore positive output node voltage will rise with constant rate of speed, and negative output node voltage will decline with constant rate of speed.By M
4112 as the sampling switch of differential signal.Notice in this process of current charge-discharge electricity, M
4112 will keep conducting, to connect upper and lower sampling capacitance 107 ~ 110, and carrying charging and discharging currents.Electric capacity C in upper and lower two parts circuit
1and C
2103 and 105,104 and 106 form capacitor voltage divider separately, the voltage V of zero-crossing comparator 100 two input nodes
x+and V
x-will respectively with its output node voltage V
o+and V
o-change.Until zero-crossing comparator 100 input node reaches " empty short " state, i.e. V
x+=V
x-, the output generation redirect of zero-crossing comparator 100, M
4112 turn off, and the path between upper and lower sampling capacitance 107 ~ 110 disconnects, sampling capacitance C
3 ±and C
4 ±the quantity of electric charge on 107 ~ 110 has just immobilized.This moment determines the end of N+1 level circuit 102 sampling process.Work as φ
1after getting back to electronegative potential, a work period of circuit just finishes.
According to the course of work of foregoing circuit, when zero-crossing comparator 100 can not exactly in zero-acrross ing moment generation redirect time, will transformed error be there is in circuit.This error is similar to the transformed error of stage circuit in conventional pipeline analog to digital converter.Use Δ V
orepresent the transformed error exported, use Δ V
xrepresent zero-crossing comparator input summing junction X
±remainder error, then there is following relationship delta V in them
x=Δ V
o× f, wherein f is the feedback factor of this level production line circuit.For the specific flow line circuit of one-level, its feedback factor is constant substantially, and the transformed error of the remainder error of stage circuit summing junction to this grade of circuit therefore can be utilized to compensate.
Summary of the invention
The object of the present invention is to provide and be a kind ofly applicable to correcting circuit based on the production line analog-digital converter of Zero-cross comparator and method, it can realize this grade of circuit conversion compensation of error according to the remainder error of stage circuit summing junction, thus effectively improves the conversion accuracy of circuit.
The correcting circuit of production line analog-digital converter provided by the invention, its structure as shown in Figure 2.Described correcting circuit 200 is connected between the two-stage circuit 211,212 based on the production line analog-digital converter of Zero-cross comparator, and correcting circuit 200 comprises difference 1/f error amplifier 220,1 first correction electric capacity 201,1 second correction electric capacity 202,1 first transmission gate circuit 203,1 second transmission gate circuit 204; Wherein:
Difference 1/f error amplifier 220 has a positive input terminal, a negative input end, a positive output end and a negative output terminal;
First correction electric capacity 201 has a top crown end and once plate end; Second correction electric capacity 202 has a top crown end and once plate end;
Each transmission gate circuit 203,204 comprises a n type field effect transistor and a p type field effect transistor, both raceway groove parallel arrangements, both drain electrode ends are interconnected to constitute the drain electrode end of transmission gate circuit, source terminal is interconnected to constitute the source terminal of transmission gate circuit, the gate terminal of n type field effect transistor forms the N gate terminal of transmission gate circuit, and the P-gate of the gate terminal formation transmission gate circuit of p type field effect transistor is extreme.
In the present invention, the positive input terminal of described difference 1/f error amplifier 220 is connected to the positive summing junction 207 of the front stage circuits 211 based on the production line analog-digital converter of Zero-cross comparator, and negative input end is connected to the negative summing junction 208 of the front stage circuits 211 based on the production line analog-digital converter of Zero-cross comparator; Difference 1/f error amplifier 220 negative output terminal is connected to the bottom crown end of the first correction electric capacity 201, forms one first switching node 205; Positive output end is connected to the bottom crown end of the second correction electric capacity 202, forms one second switching node 206; Above-mentioned connected mode is in order to be stored in the transformed error of production line analog-digital converter front stage circuits on the first correction electric capacity 201 and the second correction electric capacity 202.
In the present invention, the first correction electric capacity 201 bottom crown end is connected to difference 1/f amplifier 220 negative output terminal, i.e. the first switching node 205; First correction electric capacity 201 top crown end is connected to the positive summing junction 209 of the late-class circuit 212 based on the production line analog-digital converter of Zero-cross comparator; Second correction electric capacity 202 bottom crown end is connected to difference 1/f amplifier 220 positive output end, i.e. the second switching node 206; Second correction electric capacity 202 top crown end is connected to the negative summing junction 210 of the late-class circuit 212 based on the production line analog-digital converter of Zero-cross comparator; Above-mentioned connected mode in order to receive the transformed error of production line analog-digital converter front stage circuits 211, then by the change-over error compensation of front stage circuits 211 in late-class circuit 212.
In the present invention, the first transmission gate 203 drain electrode end is connected to the first correction electric capacity 201 bottom crown end, i.e. the first switching node 205; First transmission gate 203 source terminal is connected to common mode electrical level; Second transmission gate 204 drain electrode end is connected to the second correction electric capacity 202 bottom crown end, i.e. the second switching node 206; Second transmission gate 204 source terminal is connected to common mode electrical level; The N gate terminal of the first transmission gate is connected with the N gate terminal of the second transmission gate, forms a N Enable Pin, in order to receive an enable signal; The P-gate of the first transmission gate is extremely extremely connected with the P-gate of the second transmission gate, forms a P Enable Pin, in order to receive an enable signal.
In the present invention, the first correction electric capacity 201 is equal with the second correction electric capacity 202 capacitance, symmetry arrangement arranged side by side.
The present invention further provides the method adopting above-mentioned correcting circuit 200 to correct the production line analog-digital converter based on Zero-cross comparator, concrete steps are as follows:
First, at the first clock phase φ
1portion of time in, N level circuit 211 is set up, N+1 level circuit 212 is sampled the result of setting up of N level circuit 211, the summing junction 207,208 of N+1 level circuit 212 is connected to common mode electrical level by switch, enable signal makes to be connected across correction electric capacity 201,202 bottom crown 205, two transmission gates 203,204 also all conductings between 206 and common mode electrical level, corrects and obtains initialization with electric capacity 201,202.After N level circuit 211 has been set up, will there is remainder error between the positive and negative summing junction 207,208 of N level circuit 211, this error equals conversion error delta and the N level circuit 211 feedback factor f of N level circuit 211
nproduct.At φ
1remaining time in, N+1 level circuit 212 summing junction 209, switch between 210 and common mode electrical level continue to keep conducting, the top crown of two correction electric capacity 201,202 continues to be connected to common mode electrical level with the summing junction 209,210 of N+1 level circuit, be connected across correction electric capacity 201,202 bottom crown 205, two transmission gates 203,204 between 206 and common mode electrical level all turn off, the remainder error of its input 207,208 is amplified a fixing gain A by difference 1/f error amplifier 220
s, be stored on two correction electric capacity 201,202.It should be noted that and can carry out the transfer process of the sub-ADC of N+1 level circuit 212 in this time period simultaneously.Because this measure can provide the change-over time longer than known schemes for sub-ADC, the rate request of antithetical phrase adc circuit therefore can be reduced.When being in another clock phase φ
2time, the bottom crown 205,206 of two correction electric capacity 201,202 is connected to common mode electrical level by two transmission gates 203,204, and the transformed error of the N level circuit 211 that it stores just has gone along with the process of establishing of N+1 level circuit 212 has compensated to setting up in result of N+1 level circuit 212.
In order to realize the accurate compensation to error, relation below demand fulfillment: A
s/ f
n=(C
1, N+1+ C
2, N+1)/C
c,N, wherein A
sfor the gain of difference 1/f error amplifier 220, f
nbe feedback factor, the C of N level circuit 211
c,Nbe the capacitance of two correction electric capacity 201,202, C
1, N+1and C
2, N+1it is the capacitance of two groups of sampling capacitances of N+1 level circuit 212.
From describing above, at each specifically based in the production line analog-digital converter of Zero-cross comparator, all can use above-mentioned correcting circuit between the two-stage circuit be connected before and after arbitrarily, each correcting circuit can by the change-over error compensation of coupled previous stage circuit in rear stage circuit.What deserves to be explained is, due to the similitude of transformed error, bearing calibration provided by the invention is not limited in the production line analog-digital converter based on Zero-cross comparator effective, and it is effective equally to conventional pipeline analog to digital converter simultaneously.
Bearing calibration of the present invention, go for various types of production line analog-digital converters of the scheme comprised based on Zero-cross comparator, can effectively improve circuit conversion precision, provide the change-over time longer than traditional scheme to sub-ADC simultaneously, thus its circuit realiration difficulty can be reduced.
Foregoing teachings roughly describes characteristic sum technological merit of the present invention, cited below particularly go out embodiment, in order to thought of the present invention to be described more lucidly.Any those of ordinary skill in the art should apprehensiblely be, according to disclosed idea and specific embodiment amendment or can design the framework realizing the identical object of the present invention, this equal framework does not exceed the spirit and scope that the accompanying claim of the present invention defines.
Accompanying drawing explanation
Fig. 1 is the two-stage circuit structure chart of the production line analog-digital converter based on Zero-cross comparator.
Fig. 2 is correcting circuit provided by the invention based on the schematic diagram in the production line analog-digital converter of Zero-cross comparator.
Fig. 3 is the working timing figure of the production line analog-digital converter based on Zero-cross comparator comprising correcting circuit provided by the invention.
Fig. 4 is difference 1/f error amplifier circuit structure chart.
Number in the figure:
101 is based on the N level circuit in the production line analog-digital converter of Zero-cross comparator; 102 is based on the N+1 level circuit in the production line analog-digital converter of Zero-cross comparator; 100 is difference zero-crossing comparator; 103 ~ 106 sampling capacitance C being followed successively by N level circuit
1+, C
1-and C
2+, C
2-; 107 ~ 110 sampling capacitance C being followed successively by N+1 level circuit
3+, C
3-, C
4+, C
4-; 111 is the sampling switch M of N level circuit
1; 112 is the sampling switch M of N+1 level circuit
4; 113 is the positive channel presetting transistor M of N level circuit
2; 114 is the negative channel presetting transistor M of N level circuit
3; 115 ~ 118 are followed successively by the current source I in N level circuit
1+, I
1-, I
2+, I
2-; 119 ~ 122 are followed successively by the current source I in N+1 level circuit
3+, I
3-, I
4+, I
4-;
211 is the N level circuit of production line analog-digital converter based on Zero-cross comparator; 212 is the N+1 level circuit of production line analog-digital converter based on Zero-cross comparator; 200 for being connected to the N level correcting circuit between two-stage circuit; 220 is difference 1/f error amplifier; 201,202 is two correction electric capacity C
c+, N, C
c-, N; 203,204 is two transmission gate circuit TG
+, N, TG
-, N; 205,206 is two switching nodes; 207,208 is the positive and negative summing junction X of N level circuit
+, N, X
-, N; 209,210 is the positive and negative summing junction X of N+1 level circuit
+,
n+1, X
-,
n+1;
401,402 is that the input of difference 1/f error amplifier is to pipe; 403,404 is to managing two PMOS be connected with input; 405,406 is two variable resistors realized by switch resistance array; 407,408 is two difference output ends of difference 1/f error amplifier; 409 is bias current sources; 410 is the switching node that two gate pmos ends are connected to form.
Embodiment
Below in conjunction with accompanying drawing, bearing calibration provided by the invention is described in detail.It should be noted that bearing calibration provided by the invention can be implemented in a number of different ways, embodiment is hereafter a typical realizing circuit of bearing calibration provided by the invention, only in order to formation of the present invention and use to be described, and is not used to limit the present invention.
Have employed the two-stage circuit of the production line analog-digital converter based on Zero-cross comparator of bearing calibration provided by the invention as shown in Figure 2, it comprises: based on the N level production line circuit 211 of Zero-cross comparator, N+1 level production line circuit 212, the N level correcting circuit 200 based on Zero-cross comparator;
Wherein N level correcting circuit comprises: difference 1/f error amplifier 220, two correction electric capacity C
c+, N201, C
c-, N202, two transmission gate circuit TG
+, N203, TG
-, N204.
Two differential input ends of difference 1/f error amplifier 220 are connected to the positive and negative summing junction X of production line analog-digital converter N level circuit 211 respectively
+, N207, X
-, N208; Two difference output ends of difference 1/f error amplifier 220 cross-connect to two correction electric capacity C respectively
c+, N201, C
c-, Nthe bottom crown end 205,206 of 202, namely negative output terminal is connected to the first correction electric capacity C
c+, Nthe bottom crown end 205 of 201, positive output end is connected to the second correction electric capacity C
c-, Nthe bottom crown end 206 of 202; Electric capacity C is used in two corrections
c+, N201, C
c-, Nthe top crown end of 202 is connected to the positive and negative summing junction X of N+1 level circuit 212 respectively
+, N+1209, X
-, N+1210; Two transmission gate TG
+, N203, TG
-, N204 are connected across two correction electric capacity C respectively
c+, N201, C
c-, Nthe bottom crown end 205 of 202, between 206 and common mode electrical level, both N grid end short circuits control enable signal E in order to receive
a+, N, both P-gate end short circuits are in order to receive anti-phase control enable signal E
a-, N.
The working timing figure of this embodiment as shown in Figure 3, is explained as follows its course of work in conjunction with this sequential chart:
(1) above-mentioned production line analog-digital converter works under two-phase non-overlapp-ing clock controls, phase
1with φ
2there is isometric time T1=T2=T T3, between them, there is non-overlapped time T3.
(2) first at the first clock phase φ
1portion of time in, N level production line circuit 211 is in process of establishing, and N+1 level circuit 212 is sampled the result of setting up of N level circuit 211, the summing junction X of N+1 level circuit 212
+, N+1209, X
-, N+1210 are connected to common mode electrical level by switch, difference enable signal E
a+, Nand E
a-, Nmake to be connected across correction electric capacity 201,202 bottom crown 205, two transmission gates 203,204 also all conductings between 206 and common mode electrical level, make correction electric capacity 201,202 initialization.
After (3) N level circuit 211 have been set up, at the positive and negative summing junction X of N level circuit 211
+, N207, X
-, Nto there is remainder error between 208, this error equals conversion error delta and the N level circuit 211 feedback factor f of N level circuit 211
nproduct.
(4) at φ
1remaining time in, N+1 level circuit 212 summing junction X
+, N+1209, X
-, N+1switch between 210 and common mode electrical level continues to keep conducting, and two corrections bottom crown of electric capacity 201,202 continues the summing junction X with N+1 level circuit 212
+, N+1209, X
-, N+1210 are connected to common mode electrical level, be connected across correction electric capacity 201,202 bottom crown 205, two transmission gates 203,204 between 206 and common mode electrical level all turn off, the remainder error of its input 207,208 is amplified a fixing gain A by difference 1/f error amplifier 220
s, be stored on two correction electric capacity 201,202.In this time period, carry out the transfer process of the sub-ADC of N+1 level circuit 212 simultaneously.In traditional scheme, carry out in the non-overlapped time period T4 that this process is dispensed on two phase clock usually, this time period is usually shorter.Therefore the present embodiment can provide the change-over time longer than traditional scheme for sub-ADC, thus reduces the rate request of antithetical phrase adc circuit, such as can with the flash sub ADC in the lower SAR sub ADC replacement traditional scheme of power consumption.
(5) another clock phase φ will be then in
2, N+1 level circuit 212 enters process of establishing, difference enable signal E
a+, Nand E
a-, Nmake to be connected across correction electric capacity 201,202 bottom crown 205, the equal conducting of two transmission gates 203,204 between 206 and common mode electrical level, the bottom crown 205,206 of two correction electric capacity 201,202 is connected to common mode electrical level by two transmission gates 203,204, and the transformed error of the N level circuit 211 that it stores just has gone along with the process of establishing of N+1 level circuit 212 has compensated to setting up in result of N+1 level circuit 212.
From describing above, the summing junction X of N level circuit 211
±, N207, the remainder error between 208 equals conversion error delta and the N level circuit 211 feedback factor f of N level circuit 211
nproduct, wherein the conversion error delta of N level circuit 211 be need compensate the margin of error.(C will be amplified by N+1 level when the output of N level circuit 211 is passed to the output of N+1 level circuit 212
1, N+1+ C
2, N+1)/C
2, N+1doubly, correct electricity consumption in N level correcting circuit 200 to hold when the upper voltage of 201,202 is passed to the output of N+1 level circuit 212 and will be exaggerated C
c,N/ C
2, N+1doubly.Therefore in order to by the conversion error delta accurate compensation of N level circuit 211 to the output of N+1 level circuit 212, relation below demand fulfillment: A
s/ f
n=(C
1, N+1+ C
2, N+1)/C
c,N, wherein A
sfor the gain of difference 1/f error amplifier 220, f
nbe feedback factor, the C of N level circuit 211
c,Nbe the capacitance of two correction electric capacity 201,202, C
1, N+1and C
2, N+1it is the capacitance of two groups of sampling capacitances of N+1 level circuit.
Because we accurately cannot measure the feedback factor f of a certain particular electrical circuit
n, therefore can only take following methods: first estimate a 1/f
nvalue, obtain an A thus
s-value, realize by the physical circuit of above-mentioned parameter as circuit parameter; Then the output of analysis circuit, uses the feedback algorithm of such as LMS and so on to constantly update the 1/f estimated
nvalue, make the output error of circuit more and more less.
According to foregoing, also require that the gain of difference 1/f error amplifier 220 is adjustable, a kind of realizing circuit as shown in Figure 4.As seen from the figure, it is inputted pipe pipe 401,402 conduct by a pair nmos differential.The grid end of two PMOS 403,404 is connected to form a switching node 410, and source electrode is all connected with power supply, and drain terminal is connected with the drain terminal of two NMOS tube 401,402 respectively, forms two difference output ends 407,408 of difference 1/f error amplifier.Current source 409 provides current offset for whole circuit.Two variable resistors 405,406 are connected across between circuit two difference output ends 407,408 and PMOS 403,404 grid end switching node 410 respectively.This circuit realizes adjustable gain by regulating above-mentioned variable resistor 405,406, and variable resistor is realized by the electric resistance array by switch control rule, therefore there is minimum change scale.The linear conditions corrected require that the gain of difference 1/f error amplifier 220 substantially remains unchanged in the output area of its work.Because the remainder error of every level production line circuit summing junction is usually little, the output area of therefore difference 1/f error amplifier work is usually also little, is easily met the linear requirements of gain.
What deserves to be explained is, Fig. 2 show but N level production line circuit 211, N+1 level production line circuit 212 and N level correcting circuit 200, but for the whole production line analog-digital converter based on Zero-cross comparator, all can use above-mentioned correcting circuit between the two-stage flow line circuit be connected before and after arbitrarily, each correcting circuit can by the change-over error compensation of coupled previous stage flow line circuit in rear stage flow line circuit.What deserves to be explained is simultaneously, because the transformed error of the production line analog-digital converter based on Zero-cross comparator and the transformed error of conventional pipeline analog to digital converter exist similitude, therefore bearing calibration provided by the invention is not limited in the production line analog-digital converter based on Zero-cross comparator effective, and it is effective equally to conventional pipeline analog to digital converter.
Although content of the present invention and advantage disclose as above in detail; but should be noted that; scope of the present invention is not limited to the specific embodiment such as method and step described in specification; without departing from the spirit and scope of the present invention; any those of ordinary skill in the art all can make many distortion and amendment according to disclosed content, these also should be considered as protection scope of the present invention.
Claims (5)
1. one kind is applicable to the correcting circuit of the production line analog-digital converter based on Zero-cross comparator, it is characterized in that, described correcting circuit (200) is connected between the two-stage circuit (211,212) of the production line analog-digital converter based on Zero-cross comparator, and correcting circuit (200) comprises a difference 1/f error amplifier (220), one first correction electric capacity (201), one second correction electric capacity (202), one first transmission gate circuit (203), one second transmission gate circuit (204); Wherein:
Difference 1/f error amplifier (220) has a positive input terminal, a negative input end, a positive output end and a negative output terminal;
First correction electric capacity (201) has a top crown end and once plate end; Second correction electric capacity (202) has a top crown end and once plate end;
Each transmission gate circuit (203,204) comprises a n type field effect transistor and a p type field effect transistor, both raceway groove parallel arrangements, both drain electrode ends are interconnected to constitute the drain electrode end of transmission gate circuit, source terminal is interconnected to constitute the source terminal of transmission gate circuit, the gate terminal of n type field effect transistor forms the N gate terminal of transmission gate circuit, and the P-gate of the gate terminal formation transmission gate circuit of p type field effect transistor is extreme.
2. correcting circuit as claimed in claim 1, it is characterized in that, the positive input terminal of difference 1/f error amplifier (220) is connected to the positive summing junction (207) of the front stage circuits (211) of the production line analog-digital converter based on Zero-cross comparator, and negative input end is connected to the negative summing junction (208) of the front stage circuits (211) of the production line analog-digital converter based on Zero-cross comparator; Difference 1/f error amplifier (220) negative output terminal is connected to the bottom crown end of the first correction electric capacity (201), forms one first switching node (205); Positive output end is connected to the bottom crown end of the second correction electric capacity (202), forms one second switching node (206); Like this, the transformed error of production line analog-digital converter front stage circuits is stored on the first correction electric capacity (201) and the second correction electric capacity (202).
3. correcting circuit as claimed in claim 1, it is characterized in that, the first correction electric capacity (201) bottom crown end is connected to difference 1/f amplifier (220) negative output terminal, i.e. the first switching node (205); First correction electric capacity (201) top crown end is connected to the positive summing junction (209) of the late-class circuit (212) of the production line analog-digital converter based on Zero-cross comparator; Second correction electric capacity (202) bottom crown end is connected to difference 1/f amplifier (220) positive output end, i.e. the second switching node (206); Second correction electric capacity (202) top crown end is connected to the negative summing junction (210) of the late-class circuit (212) of the production line analog-digital converter based on Zero-cross comparator; Above-mentioned connected mode in order to receive the transformed error of production line analog-digital converter front stage circuits (211), then by the change-over error compensation of front stage circuits (211) in late-class circuit (212).
4. correcting circuit as claimed in claim 1, it is characterized in that, the first transmission gate (203) drain electrode end is connected to the first correction electric capacity (201) bottom crown end, i.e. the first switching node (205); First transmission gate (203) source terminal is connected to common mode electrical level; Second transmission gate (204) drain electrode end is connected to the second correction electric capacity (202) bottom crown end, i.e. the second switching node (206); Second transmission gate (204) source terminal is connected to common mode electrical level; The N gate terminal of the first transmission gate is connected with the N gate terminal of the second transmission gate, forms a N Enable Pin, in order to receive an enable signal; The P-gate of the first transmission gate is extremely extremely connected with the P-gate of the second transmission gate, forms a P Enable Pin, in order to receive an enable signal.
5. correcting circuit as claimed in claim 1, it is characterized in that, the first correction electric capacity (201) is equal with the second correction electric capacity (202) capacitance, symmetry arrangement arranged side by side.
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| CN201410754786.6A CN104506191B (en) | 2014-12-11 | 2014-12-11 | The correcting circuit of production line analog-digital converter based on Zero-cross comparator and bearing calibration |
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| CN107703468A (en) * | 2017-10-18 | 2018-02-16 | 厦门大学 | The drive circuit of NMR gradient power amplifier |
| CN107733433A (en) * | 2017-11-13 | 2018-02-23 | 英特格灵芯片(天津)有限公司 | A kind of current source calibration device and method |
| CN107947794A (en) * | 2017-11-30 | 2018-04-20 | 无锡中微爱芯电子有限公司 | A kind of error correction circuit for analog-digital converter offset error correction |
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| CN101192829A (en) * | 2007-12-19 | 2008-06-04 | 北京大学 | A forward error compensation and correction method and device for streamline analog/digital converter |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107703468A (en) * | 2017-10-18 | 2018-02-16 | 厦门大学 | The drive circuit of NMR gradient power amplifier |
| CN107703468B (en) * | 2017-10-18 | 2023-12-01 | 厦门大学 | Driving circuit of gradient power amplifier of nuclear magnetic resonance apparatus |
| CN107733433A (en) * | 2017-11-13 | 2018-02-23 | 英特格灵芯片(天津)有限公司 | A kind of current source calibration device and method |
| CN107733433B (en) * | 2017-11-13 | 2024-02-20 | 四川易冲科技有限公司 | Current source calibration device and method |
| CN107947794A (en) * | 2017-11-30 | 2018-04-20 | 无锡中微爱芯电子有限公司 | A kind of error correction circuit for analog-digital converter offset error correction |
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| CN104506191B (en) | 2017-11-17 |
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