CN104503943A - MDIO bus slave unit and method for improving anti-jamming capability - Google Patents
MDIO bus slave unit and method for improving anti-jamming capability Download PDFInfo
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- CN104503943A CN104503943A CN201510004407.6A CN201510004407A CN104503943A CN 104503943 A CN104503943 A CN 104503943A CN 201510004407 A CN201510004407 A CN 201510004407A CN 104503943 A CN104503943 A CN 104503943A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
- G06F13/4273—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a clocked protocol
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses an MDIO bus slave unit and a method for improving anti-jamming capability. The method comprises the steps of running a local high-speed clock on the MDIO bus slave unit, capturing the starting moments of the rising edge and the falling edge of a received MDC main clock signal, generating an MDC slave clock by use of the local high-speed clock according to the starting moments of the rising edge and the falling edge of the MDC main clock signal, and enabling the MDIO bus slave unit to perform MDIO bus data processing by use of the MDC slave clock. According to the method for improving the anti-jamming capability, wrong data acquisition due to distortion of the MDC clock signal under jamming is avoided and the anti-jamming capability of the MDIO bus slave unit is improved.
Description
Technical field
The present invention relates to the MDIO bussing technique field in optical communication technique, be specifically related to the method for MDIO bus slave and raising antijamming capability.
Background technology
CFP (Centum Form Factor Pluggable, multi-functional pluggable) MSA (Multi-SourceAgreement, multi-source agreement) regulation, information interaction between CFP optical module and line card mainboard adopts MDIO (Management Data InpuOt Output, management data input and output) bus to communicate.
Under normal circumstances, 100G CFP optical module need from various different line card mainboard with the use of, because the hardware environment of various line card mainboard is different, 100G CFP optical module, by producing transmission impairment to signal in MDIO bus and line card mainboard communication process, causes the distortion of signal.The method overcoming this distortion normally requires that 100G CFP optical module and line card mainboard carry out strict signal routing, and control group is mated.But due to the diversity of hardware environment; the MDIO bus of line card mainboard and 100G CFP optical module coordinates and often there will be fault; and fault appears in clock signal mostly; simultaneously; containing analog devices such as a large amount of power supply, high-speed transceivers in CFP optical module; there is the electromagnetic interference (EMI) of ground level interference and other signal, therefore jamproof design is carried out to MDIO bus interface extremely important.
Usually adopt at present and filtering process is carried out to ground level, shielding processing is carried out to other electromagnetic device, but these factors can have an impact to MDIO bus signals quality in 100G CFP optical module, simultaneously, in the main equipment of MDIO bus, because all orders are all that main equipment is initiated, and the clock signal of MDIO bus is also sent by main equipment, therefore the impact of various interference on MDIO main equipment is less, and in a slave device, the clock signal of MDIO bus sends over from main equipment, there is various interference in circuit and optical module itself, therefore often there is following problem:
(1) clock signal is interfered and distorts;
(2) collection of clock signal to data makes a mistake.
As can be seen here, existing MDIO bus is lower from equipment antijamming capability.
Summary of the invention
Technical matters to be solved by this invention is the problem lower from equipment antijamming capability of MDIO bus.
In order to solve the problems of the technologies described above, the invention provides a kind of method improving MDIO bus slave antijamming capability, comprising the following steps:
MDIO bus slave runs a local high-frequency clock, and described local high-frequency clock produces the reference clock signal that frequency is greater than MDC master clock signal;
Catch the rising edge of MDC master clock signal and the initial time of negative edge that receive;
According to the described rising edge of MDC master clock signal and the initial time of negative edge, described local high-frequency clock is utilized to generate MDC from clock, namely the rising edge time of described MDC master clock signal triggers described local high-frequency clock and produces the rising edge of MDC from clock, the change of described MDC master clock signal is ignored within the described local high-frequency clock cycle of 3 subsequently, keep MDC from clock high level, before the negative edge moment of described MDC master clock signal, keep high level thereafter; Local high-frequency clock described in the negative edge time trigger of described MDC master clock signal produces the negative edge of MDC from clock, the change of described MDC master clock signal is ignored within the described local high-frequency clock cycle of 3 subsequently, keep MDC from clock low, before the rising edge time of described MDC master clock signal, keep low level thereafter;
MDIO bus slave utilizes MDC to carry out the process of MDIO bus data from clock.
In the above-mentioned methods, the frequency of described local high-frequency clock is more than 10 times or 10 times of MDIO master clock frequency.
Present invention also offers a kind of MDIO bus slave, comprise from equipment body, described have MDIO bus interface from equipment body, and described MDIO bus interface comprises the MDC clock interface for receiving the MDC master clock signal that MDIO main equipment sends, and describedly comprises from equipment body:
Local high-frequency clock, produces the reference clock signal that frequency is greater than described MDC master clock signal;
Capturing unit, for catching from the described rising edge of MDC master clock signal and the initial time of negative edge;
MDC is from clock generating unit, according to the described rising edge of MDC master clock signal and the initial time of negative edge, described local high-frequency clock is utilized to generate MDC from clock, namely the rising edge time of described MDC master clock signal triggers described local high-frequency clock and produces the rising edge of MDC from clock, the change of described MDC master clock signal is ignored within the described local high-frequency clock cycle of 3 subsequently, keep MDC from clock high level, before the negative edge moment of described MDC master clock signal, keep high level thereafter; Local high-frequency clock described in the negative edge time trigger of described MDC master clock signal produces the negative edge of MDC from clock, the change of described MDC master clock signal is ignored within the described local high-frequency clock cycle of 3 subsequently, keep MDC from clock low, before the rising edge time of described MDC master clock signal, keep low level thereafter;
Describedly MDC is utilized to carry out the process of MDIO bus data from clock from equipment body.
In above-mentioned MDIO bus slave, the frequency of described local high-frequency clock is more than 10 times or 10 times of MDIO master clock frequency.
In above-mentioned MDIO bus slave, the frequency of described local high-frequency clock is 100MHz.
The present invention, by running a local high-frequency clock on MDIO bus slave, according to the rising edge of MDC master clock signal received and the initial time of negative edge, local high-frequency clock is utilized to generate MDC from clock, MDIO bus slave utilizes MDC to carry out the process of MDIO bus data from clock, effectively solve the various interference because circuit and optical module itself exist and make the MDC clock signal of MDIO bus be sent to from being interfered the problem that distortion occurs during equipment from main equipment, avoid the collection of MDC clock signal to data to make a mistake, improve the antijamming capability of MDIO bus slave.
Accompanying drawing explanation
What Fig. 1 provided for the embodiment of the present invention a kind ofly improves the method flow diagram of MDIO from equipment antijamming capability;
Fig. 2 is the schematic diagram that in the embodiment of the present invention, MDC generates from clock.
Embodiment
Below in conjunction with specification drawings and specific embodiments, the present invention is described in detail.
Embodiments provide and a kind ofly improve the method for MDIO from equipment antijamming capability, as shown in Figure 1 and Figure 2, said method comprising the steps of:
Step 101, on MDIO bus slave, running the local high-frequency clock that frequency is 100MHz, to produce for generating the reference clock signal of MDC from clock, referring to the CLK_100MHz in Fig. 2.
It should be noted that, the frequency of this local high-frequency clock is generally more than 10 times or 10 times of MDIO master clock frequency, also can be other values, does not limit at this.
Step 102, catch the rising edge of MDC master clock signal and the initial time of negative edge that receive, refer to Fig. 2, MDC is MDC major clock, MDC_T be MDC major clock catch the moment.
It should be noted that, capture MDC (Management data clock, management data clock) master clock signal rising edge time or after the negative edge moment, rising edge time or the negative edge moment of MDC master clock signal is again captured within 3 burst lengths of local high-frequency clock, after then thinking once to catch be interference, catching once after ignoring.This illustrates, by the frequency of the local high-frequency clock of adjustment, can control back the filtering accuracy of hook and vibration.
Step 103, according to the rising edge of MDC master clock signal and the initial time of negative edge, utilize local high-frequency clock generate MDC from clock.
Concrete, the rising edge time of MDC master clock signal triggers local high-frequency clock and produces the rising edge of MDC from clock, the change of MDC master clock signal is ignored within the local high-frequency clock cycle of 3 subsequently, keep MDC from clock high level, before the negative edge moment of MDC master clock signal, keep high level thereafter; The local high-frequency clock of negative edge time trigger of MDC master clock signal produces the negative edge of MDC from clock, the change of MDC master clock signal is ignored within the local high-frequency clock cycle of 3 subsequently, keep MDC from clock low, before the rising edge time of MDC master clock signal, keep low level thereafter.
Refer in Fig. 2, MDC_SYN is that MDC is from clock.
In this way, be equivalent to revise MDC master clock signal, namely time interference such as hook and vibration that MDC master clock signal produces when rising edge and negative edge has been filtered out, revised MDC clock (MDC is from clock) is at the high level of MDC rising edge state and MDC high level stable state stable output, in the low level of MDC negative edge state and MDC low level stable state stable output, eliminate the distortion of MDC master clock signal.
Step 104, MDIO bus slave utilize MDC to carry out the process of MDIO bus data from clock, realize the information interaction of mainboard line card and 100G CFP optical module.
The present invention, by running a local high-frequency clock on MDIO bus slave, according to the rising edge of MDC master clock signal received and the initial time of negative edge, local high-frequency clock is utilized to generate MDC from clock, MDIO bus data is processed, effectively solving the problem that MDC clock signal occurs because being interfered to distort, avoiding the collection of MDC clock signal to data and making a mistake, improve the antijamming capability of MDIO bus slave.
Based on the above method, the embodiment of the present invention additionally provides a kind of MDIO bus slave, comprise from equipment body, described have MDIO bus interface from equipment body, described MDIO bus interface comprises the MDC clock interface for receiving the MDC master clock signal that MDIO main equipment sends, and describedly comprises from equipment body:
Local high-frequency clock, is greater than the reference clock signal of MDC master clock signal for generation of frequency;
Capturing unit, for the initial time of the rising edge and negative edge of catching MDC master clock signal;
MDC is from clock generating unit, for according to the rising edge of MDC master clock signal and the initial time of negative edge, local high-frequency clock is utilized to generate MDC from clock, namely the rising edge time of MDC master clock signal triggers local high-frequency clock and produces the rising edge of MDC from clock, the change of described MDC master clock signal is ignored within the described local high-frequency clock cycle of 3 subsequently, keep MDC from clock high level, before the negative edge moment of MDC master clock signal, keep high level thereafter; The local high-frequency clock of negative edge time trigger of MDC master clock signal produces the negative edge of MDC from clock, the change of described MDC master clock signal is ignored within the described local high-frequency clock cycle of 3 subsequently, keep MDC from clock low, before the rising edge time of MDC master clock signal, keep low level thereafter.
MDC is utilized to carry out the process of MDIO bus data from clock from equipment body.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structure change made under enlightenment of the present invention, and every have identical or close technical scheme with the present invention, all falls within protection scope of the present invention.
Claims (5)
1. improve the method for MDIO bus slave antijamming capability, it is characterized in that, comprise the steps:
MDIO bus slave runs a local high-frequency clock, and described local high-frequency clock produces the reference clock signal that frequency is greater than MDC master clock signal;
Catch the rising edge of MDC master clock signal and the initial time of negative edge that receive;
According to the described rising edge of MDC master clock signal and the initial time of negative edge, described local high-frequency clock is utilized to generate MDC from clock, namely the rising edge time of described MDC master clock signal triggers described local high-frequency clock and produces the rising edge of MDC from clock, the change of described MDC master clock signal is ignored within the described local high-frequency clock cycle of 3 subsequently, keep MDC from clock high level, before the negative edge moment of described MDC master clock signal, keep high level thereafter; Local high-frequency clock described in the negative edge time trigger of described MDC master clock signal produces the negative edge of MDC from clock, the change of described MDC master clock signal is ignored within the described local high-frequency clock cycle of 3 subsequently, keep MDC from clock low, before the rising edge time of described MDC master clock signal, keep low level thereafter;
MDIO bus slave utilizes MDC to carry out the process of MDIO bus data from clock.
2. the method for claim 1, is characterized in that, the frequency of described local high-frequency clock is more than 10 times or 10 times of MDIO master clock frequency.
3.MDIO bus slave, comprise from equipment body, described have MDIO bus interface from equipment body, and described MDIO bus interface comprises the MDC clock interface for receiving the MDC master clock signal that MDIO main equipment sends, it is characterized in that, describedly to comprise from equipment body:
Local high-frequency clock, produces the reference clock signal that frequency is greater than described MDC master clock signal;
Capturing unit, for catching the described rising edge of MDC master clock signal and the initial time of negative edge;
MDC is from clock generating unit, according to the described rising edge of MDC master clock signal and the initial time of negative edge, described local high-frequency clock is utilized to generate MDC from clock, namely the rising edge time of described MDC master clock signal triggers described local high-frequency clock and produces the rising edge of MDC from clock, the change of described MDC master clock signal is ignored within the described local high-frequency clock cycle of 3 subsequently, keep MDC from clock high level, before the negative edge moment of described MDC master clock signal, keep high level thereafter; Local high-frequency clock described in the negative edge time trigger of described MDC master clock signal produces the negative edge of MDC from clock, the change of described MDC master clock signal is ignored within the described local high-frequency clock cycle of 3 subsequently, keep MDC from clock low, before the rising edge time of described MDC master clock signal, keep low level thereafter;
Describedly MDC is utilized to carry out the process of MDIO bus data from clock from equipment body.
4. MDIO bus slave as claimed in claim 3, it is characterized in that, the frequency of described local high-frequency clock is more than 10 times or 10 times of MDIO master clock frequency.
5. MDIO bus slave as claimed in claim 3, it is characterized in that, the frequency of described local high-frequency clock is 100MHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510004407.6A CN104503943A (en) | 2015-01-06 | 2015-01-06 | MDIO bus slave unit and method for improving anti-jamming capability |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510004407.6A CN104503943A (en) | 2015-01-06 | 2015-01-06 | MDIO bus slave unit and method for improving anti-jamming capability |
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| CN104503943A true CN104503943A (en) | 2015-04-08 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1758539A (en) * | 2004-10-10 | 2006-04-12 | 中兴通讯股份有限公司 | Method for filtering vein interference of low-speed clock signal |
| CN1925387A (en) * | 2005-08-29 | 2007-03-07 | 中兴通讯股份有限公司 | Data clock recovery circuit |
| US20110001533A1 (en) * | 2009-07-01 | 2011-01-06 | Ji-Wang Lee | Sampling circuit |
| CN203133826U (en) * | 2011-09-28 | 2013-08-14 | 英特尔公司 | Receiver and system for recovering data |
-
2015
- 2015-01-06 CN CN201510004407.6A patent/CN104503943A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1758539A (en) * | 2004-10-10 | 2006-04-12 | 中兴通讯股份有限公司 | Method for filtering vein interference of low-speed clock signal |
| CN1925387A (en) * | 2005-08-29 | 2007-03-07 | 中兴通讯股份有限公司 | Data clock recovery circuit |
| US20110001533A1 (en) * | 2009-07-01 | 2011-01-06 | Ji-Wang Lee | Sampling circuit |
| CN203133826U (en) * | 2011-09-28 | 2013-08-14 | 英特尔公司 | Receiver and system for recovering data |
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Application publication date: 20150408 |