CN106021151A - Signal enhancing board as well as signal enhancing method and system - Google Patents
Signal enhancing board as well as signal enhancing method and system Download PDFInfo
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- CN106021151A CN106021151A CN201610305191.1A CN201610305191A CN106021151A CN 106021151 A CN106021151 A CN 106021151A CN 201610305191 A CN201610305191 A CN 201610305191A CN 106021151 A CN106021151 A CN 106021151A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000002708 enhancing effect Effects 0.000 title claims abstract description 24
- 230000005540 biological transmission Effects 0.000 claims abstract description 25
- 230000000630 rising effect Effects 0.000 claims abstract description 14
- 238000007781 pre-processing Methods 0.000 claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 11
- 230000010355 oscillation Effects 0.000 claims abstract description 11
- 238000001228 spectrum Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 description 7
- 230000008054 signal transmission Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 230000003595 spectral effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- 230000015654 memory Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
The invention provides a signal enhancing board as well as a signal enhancing system and method. The signal enhancing board comprises a PCIE signal interface unit, a signal pre-processing unit, a signal enhancing processing unit, a conversion and transmission unit and an SAS signal interface unit, wherein the PCIE signal interface unit is used for receiving a PCIE signal from an external mainboard; the signal pre-processing unit is used for removing a shake in the PCIE signal received by the PCIE signal interface unit, resetting output parameters through a dial switch and transmitting the processed PCIE signal to the signal enhancing processing unit; the signal enhancing processing unit is used for enhancing the amplitudes of a rising edge and a falling edge of the PCIE signal, reducing the oscillation amplitude of the PCIE signal and transmitting the processed PCIE signal to the conversion and transmission unit; the conversion and transmission unit are used for converting the received PCIE signal into an SAS signal and transmitting the SAS signal to the SAS signal interface unit; and the SAS signal interface unit is used for sending the received SAS signal to an external hard disk backboard. According to the signal enhancing board as well as the signal enhancing system and method, the PCIE signal between the mainboard and the hard disk backboard can be enhanced.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a signal enhancement board, a signal enhancement method and a signal enhancement system.
Background
In a server, to solve the space utilization problem, a hard disk interface is usually placed on a backplane, and a motherboard is connected to the backplane through a cable.
In practical application, PCIE routing is too long, a cable is too long, and the like on a hard disk backplane all have the possibility of causing PCIE signal attenuation and signal distortion.
Disclosure of Invention
The embodiment of the invention provides a signal enhancement board, a signal enhancement method and a signal enhancement system, which can enhance PCIE signals.
A signal enhancement panel, comprising:
the PCIE signal interface unit is used for receiving a PCIE signal from an external mainboard;
the signal preprocessing unit is used for removing jitter in the PCIE signals received by the PCIE signal interface unit, resetting output parameters through a dial switch and transmitting the processed PCIE signals to the signal enhancement processing unit;
the signal enhancement processing unit is used for enhancing the amplitude of the rising edge and the falling edge of the PCIE signal, reducing the oscillation amplitude of the PCIE signal and transmitting the processed PCIE signal to the conversion transmission unit;
the conversion transmission unit is used for converting the received PCIE signals into SAS signals and then transmitting the SAS signals to the SAS signal interface unit;
and the SAS signal interface unit is used for sending the received SAS signal to an external hard disk backboard.
The signal enhancement processing unit is further configured to enhance the amplitude of the PCIE signal with the predetermined spectral component after the reduction of the swing of the PCIE signal is performed and before the processed PCIE signal is transmitted to the conversion transmission unit.
And the signal preprocessing unit transmits the processed PCIE signals by utilizing a PCIE signal differential transmission mode.
The PCIE signal interface unit comprises:
a first PCIE interface subunit configured to receive a PCIE RX signal;
and the second PCIE interface subunit is used for receiving the PCIE TX signal.
The SAS signal interface unit includes:
a first SAS interface subunit configured to receive a SAS RX signal;
a second SAS interface subunit for receiving SAS TX signals.
The signal preprocessing unit adjusts the dial switch by measuring the integrity of the PCIE signal, checks the signal quality of the eye pattern and determines the output parameters of the PCIE signal meeting the set requirements.
A signal enhancement system, comprising:
the system comprises a main board, a hard disk back board and any one of the signal enhancing boards; wherein,
the main board outputs a PCIE signal to a PCIE signal interface unit of the signal enhancement board through a PCIE signal interface of the main board;
the hard disk back plate is connected to the SAS signal interface unit of the signal enhancement plate through a cable.
Further comprising: a PCIE hard disk;
the at least one PCIE hard disk is connected to the hard disk backplane through an 8639 interface.
A method of signal enhancement, comprising:
receiving a PCIE signal from an external mainboard;
removing jitter in the PCIE signal;
resetting output parameters through a dial switch;
the amplitudes of the rising edge and the falling edge of the PCIE signal are enhanced, and the amplitude of oscillation of the PCIE signal is reduced;
converting the current PCIE signal into an SAS signal;
and sending the SAS signal to an external hard disk backboard.
The resetting of the output parameter by the dip switch comprises:
measuring the integrity of the PCIE signal;
and adjusting the dial switch, checking the signal quality of the eye pattern, and determining the output parameters of the PCIE signals meeting the set requirements.
The signal enhancement board, the signal enhancement system and the signal enhancement method provided by the embodiment of the invention can perform a series of processing for enhancing PCIE signals, and comprise the following steps: and removing the jitter in the PCIE signal, resetting the output parameters through the dial switch, enhancing the amplitude of the rising edge and the falling edge of the PCIE signal and reducing the amplitude of oscillation of the PCIE signal. Therefore, the PCIE signal is ensured to be enhanced before being transmitted to the hard disk backboard through the SAS signal interface, and therefore the problems of PCIE signal weakness and signal distortion can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a signal enhancement board according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a signal enhancement board according to another embodiment of the present invention.
Fig. 3 is a schematic diagram of a signal enhancement system according to an embodiment of the present invention.
Fig. 4 is a flow chart of a signal enhancement method in one embodiment of the invention.
Fig. 5 is a flow chart of a signal enhancement method in another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention, and based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the scope of the present invention.
One embodiment of the present invention provides a signal enhancement board, referring to fig. 1, including:
a PCIE signal interface unit 101, configured to receive a PCIE signal from an external motherboard;
a signal preprocessing unit 102, configured to remove jitter in a PCIE signal received by the PCIE signal interface unit 101, reset an output parameter through a dial switch, and transmit the processed PCIE signal to the signal enhancement processing unit 103;
the signal enhancement processing unit 103 is configured to enhance the amplitudes of the rising edge and the falling edge of the PCIE signal, reduce the swing amplitude of the PCIE signal, and transmit the processed PCIE signal to the conversion transmission unit 104;
a conversion transmission unit 104, configured to convert the received PCIE signal into an SAS signal, and then transmit the SAS signal to an SAS signal interface unit 105;
the SAS signal interface unit 105 is configured to send the received SAS signal to an external hard disk backplane.
The signal enhancement board provided by the embodiment of the invention can be used for performing a series of processing on PCIE signal enhancement by matching with each functional unit, and comprises the following steps: and removing the jitter in the PCIE signal, resetting the output parameters through the dial switch, enhancing the amplitude of the rising edge and the falling edge of the PCIE signal and reducing the amplitude of oscillation of the PCIE signal. Therefore, the PCIE signal is ensured to be enhanced before being transmitted to the hard disk backboard through the SAS signal interface, and therefore the problems of PCIE signal weakness and signal distortion can be reduced.
In an embodiment of the present invention, in order to further improve the effect of signal enhancement, the signal enhancement processing unit 103 is further configured to enhance the amplitude of the PCIE signal with a predetermined frequency spectrum component after the reducing the swing of the PCIE signal is performed and before the processed PCIE signal is transmitted to the conversion transmission unit 104.
In the embodiment of the present invention, the amplitude of the PCIE signal with the predetermined frequency spectrum component is enhanced, and the enhancement processing may be performed only on the amplitude of the PCIE signal with the predetermined frequency spectrum component, which is required, according to the requirement of the actual service, so that the transmission of the signal is facilitated. The signal transmission shows the characteristic of a low-pass filter, the attenuation of high-frequency components of the signal is large in the transmission process, and the attenuation of low-frequency components is small.
In an embodiment of the present invention, the signal preprocessing unit 102 transmits the processed PCIE signal by using a PCIE signal differential transmission manner. And transmitting the processed PCIE signal by utilizing a PCIE signal differential transmission mode, so that the signal-to-noise ratio can be greatly improved.
In an embodiment of the present invention, referring to fig. 2, the PCIE signal interface unit 101 includes:
a first PCIE interface subunit 201, configured to receive a PCIE RX signal;
the second PCIE interface subunit 202 is configured to receive a PCIE TX signal.
The SAS signal interface unit 105 includes:
a first SAS interface subunit 203, configured to receive a SAS RX signal;
a second SAS interface subunit 204 to receive SAS TX signals.
Through the structure shown in fig. 2, the signal enhancement unit can process the PCIE RX signal and the PCIE TX signal, and respectively and correspondingly convert the PCIE RX signal and the PCIE TX signal into the SAS RX signal and the SAS TX signal, thereby improving the practicability.
In an embodiment of the present invention, the implementation manner of the signal preprocessing unit 102 to determine the output parameter may include: the signal preprocessing unit 102 adjusts the dial switch by measuring the integrity of the PCIE signal, checks the signal quality of the eye diagram, and determines the output parameters of the PCIE signal that meet the setting requirements.
The signal preprocessing unit 102 determines the output parameters of the PCIE signal meeting the setting requirement, so that the output parameters can be reset, the signal is recoded, and further the signal is corrected.
An embodiment of the present invention further provides a signal enhancement system, referring to fig. 3, including:
a main board 301, a hard disk backplane 302, and any one of the signal enhancement boards 303 provided by the embodiments of the present invention; wherein,
the main board 301 outputs a PCIE signal to the PCIE signal interface unit of the signal enhancement board 303 through its PCIE signal interface;
the hard disk backplane 302 is connected to the SAS signal interface unit of the signal enhancement board 303 through a cable.
Therefore, any signal enhancement board provided by the embodiment of the invention is matched with the main board and the hard disk backplane, so that the signal can be enhanced while the PCIE signal of the main board is transmitted to the hard disk backplane through the SAS signal after being converted, namely, the signal transmitted to the hard disk backplane is ensured to be the enhanced signal. The signal enhancement system avoids signal distortion and other problems.
In one embodiment of the present invention, the system for signal enhancement may further comprise: a PCIE hard disk;
the at least one PCIE hard disk is connected to the hard disk backplane through an 8639 interface.
In an embodiment of the present invention, in a signal enhancement system, the main board 301 may include: important electronic components such as processors, memories, management chips, and the like; the signal enhancement board 303 is used for signal enhancement and correction in the signal transmission process; the hard disk backplane 302 is used for connecting a hard disk.
An embodiment of the present invention further provides a signal enhancement method, applied to a signal enhancement board disposed between a motherboard and a hard disk backplane, and referring to fig. 4, including:
401: receiving a PCIE signal from an external mainboard;
402: removing jitter in the PCIE signal;
403: resetting output parameters through a dial switch;
404: the amplitudes of the rising edge and the falling edge of the PCIE signal are enhanced, and the amplitude of oscillation of the PCIE signal is reduced;
405: converting the current PCIE signal into an SAS signal;
406: and sending the SAS signal to an external hard disk backboard.
The signal enhancement method shown in fig. 4 according to the embodiment of the present invention can perform a series of processing for enhancing PCIE signals, including: and removing the jitter in the PCIE signal, resetting the output parameters through the dial switch, enhancing the amplitude of the rising edge and the falling edge of the PCIE signal and reducing the amplitude of oscillation of the PCIE signal. Therefore, the PCIE signal is ensured to be enhanced before being transmitted to the hard disk backboard through the SAS signal interface, and therefore the problems of PCIE signal weakness and signal distortion can be reduced.
In an embodiment of the present invention, the specific implementation of resetting the output parameter through the dial switch in the step 403 may include: measuring the integrity of the PCIE signal; and adjusting the dial switch, checking the signal quality of the eye pattern, and determining the output parameters of the PCIE signals meeting the set requirements.
An embodiment of the present invention provides another signal enhancement method, applied to a signal enhancement board disposed between a motherboard and a hard disk backplane, and referring to fig. 5, the method includes:
501: receiving a PCIE signal from an external mainboard;
502: and the jitter of randomness and certainty in the PCIE signal is removed, and the interference between symbols is eliminated.
503: resetting output parameters through a dial switch;
the specific implementation of step 503 may include: by measuring the integrity of the signal, adjusting the dial switch, using the oscilloscope to check the signal quality of the eye pattern, and determining the optimal signal parameter as the output parameter of the PCIE signal, the PCIE signal is enhanced and corrected.
For the above steps 502 and 503, the PCIE signal is corrected and re-encoded.
Since the routing length of the PCIE GEN3 is limited to within 15inch, in practical applications, because the path is too long, the routing interference is large, or the cable is too long, the SI eye diagram will make a mistake, and even the system cannot find the device, the device will make a mistake and be lost during operation. The signal is lost during transmission, which degrades the signal quality. For high frequency signals that are switched often, the attenuation is more severe than for continuous low frequency signals. Long continuous invariant codes reach higher levels and require more time to reach the threshold level at the transition, resulting in signal jitter.
Therefore, after the PCIE signal output from the motherboard reaches the PCIE signal enhancement board, through the above steps 502 and 503, the random and deterministic jitter in the signal is removed first, so as to eliminate the inter-symbol interference, and the parameter of the output jitter is reset through the dial switch, so that the signal can be corrected to implement re-encoding.
504: enhancing the high frequency components of the signal, i.e., enhancing the amplitudes of the rising and falling edges of the PCIE signal;
here, the high frequency component of the signal is enhanced to compensate for the excessive attenuation of the high frequency component during transmission, that is, the amplitudes of the rising edge and the falling edge of the signal are enhanced, so that the loss of the signal during transmission is better compensated, and the signal quality is improved.
505: reducing the amplitude of oscillation of the PCIE signal;
this step can speed up the enhancement process by reducing the signal swing, which does not increase crosstalk, EMI and power consumption.
506: the amplitude of the PCIE signal of the predetermined frequency spectrum component is enhanced.
This step is a measure for enhancing the amplitude of some spectral components in advance in order to facilitate signal transmission. The signal transmission shows the characteristic of a low-pass filter, the attenuation of high-frequency components of the signal is large in the transmission process, and the attenuation of low-frequency components is small.
507: and transmitting the processed PCIE signal by utilizing a PCIE signal differential transmission mode.
This step enables the signal-to-noise ratio to be greatly improved.
508: converting the current PCIE signal into an SAS signal;
509: and sending the SAS signal to an external hard disk backboard.
The various embodiments of the invention have at least the following beneficial effects:
1. a series of processes for PCIE signal enhancement can be performed, including: and removing the jitter in the PCIE signal, resetting the output parameters through the dial switch, enhancing the amplitude of the rising edge and the falling edge of the PCIE signal and reducing the amplitude of oscillation of the PCIE signal. Therefore, the PCIE signal is ensured to be enhanced before being transmitted to the hard disk backboard through the SAS signal interface, and therefore the problems of PCIE signal weakness and signal distortion can be reduced.
2. In the embodiment of the invention, after the PCIE signal output from the mainboard reaches the PCIE signal enhancing board, the jitter of randomness and certainty in the signal can be removed, the interference between symbols is eliminated, and the parameter of the output jitter is reset through the dial switch, so that the signal can be corrected and recoded.
3. In the embodiment of the invention, the high-frequency component of the signal is enhanced to compensate the overlarge attenuation of the high-frequency component in the transmission process, namely the amplitudes of the rising edge and the falling edge of the signal are enhanced, the loss of the signal in the transmission process is better compensated, and the signal quality is improved.
4. In the embodiment of the invention, the amplitude of certain frequency spectrum components is enhanced in advance in order to facilitate the transmission of signals. The signal transmission shows the characteristic of a low-pass filter, the attenuation of high-frequency components of the signal is large in the transmission process, and the attenuation of low-frequency components is small.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of other similar elements in a process, method, article, or apparatus that comprises the element.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it is to be noted that: the above description is only a preferred embodiment of the present invention, and is only used to illustrate the technical solutions of the present invention, and not to limit the protection scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A signal enhancement board, comprising:
the PCIE signal interface unit is used for receiving a PCIE signal from an external mainboard;
the signal preprocessing unit is used for removing jitter in the PCIE signals received by the PCIE signal interface unit, resetting output parameters through a dial switch and transmitting the processed PCIE signals to the signal enhancement processing unit;
the signal enhancement processing unit is used for enhancing the amplitude of the rising edge and the falling edge of the PCIE signal, reducing the oscillation amplitude of the PCIE signal and transmitting the processed PCIE signal to the conversion transmission unit;
the conversion transmission unit is used for converting the received PCIE signals into SAS signals and then transmitting the SAS signals to the SAS signal interface unit;
and the SAS signal interface unit is used for sending the received SAS signal to an external hard disk backboard.
2. The signal enhancement board of claim 1, wherein the signal enhancement processing unit is further configured to enhance the amplitudes of the PCIE signals with predetermined frequency spectrum components after the reducing the swings of the PCIE signals is performed and before the processed PCIE signals are transmitted to the signal enhancement processing unit.
3. The signal enhancement board of claim 1, wherein the signal preprocessing unit transmits the processed PCIE signals by using a PCIE signal differential transmission manner.
4. The signal enhancement board of claim 1, wherein the PCIE signal interface unit includes:
a first PCIE interface subunit configured to receive a PCIE RX signal;
and the second PCIE interface subunit is used for receiving the PCIE TX signal.
5. The signal booster board of claim 4, wherein the SAS signal interface unit comprises:
a first SAS interface subunit configured to receive a SAS RX signal;
a second SAS interface subunit for receiving SAS TX signals.
6. The signal enhancement board of any one of claims 1 to 5, wherein the signal preprocessing unit determines the output parameters of the PCIE signals meeting the setting requirements by measuring the integrity of the PCIE signals, adjusting a dial switch, and checking the signal quality of an eye pattern.
7. A signal enhancement system, comprising:
a motherboard, a hard disk backplane, and the signal booster board of any of claims 1 to 6; wherein,
the main board outputs a PCIE signal to a PCIE signal interface unit of the signal enhancement board through a PCIE signal interface of the main board;
the hard disk back plate is connected to the SAS signal interface unit of the signal enhancement plate through a cable.
8. The signal enhancement system of claim 7, further comprising: a PCIE hard disk;
the at least one PCIE hard disk is connected to the hard disk backplane through an 8639 interface.
9. A method of signal enhancement, comprising:
receiving a PCIE signal from an external mainboard;
removing jitter in the PCIE signal;
resetting output parameters through a dial switch;
the amplitudes of the rising edge and the falling edge of the PCIE signal are enhanced, and the amplitude of oscillation of the PCIE signal is reduced;
converting the current PCIE signal into an SAS signal;
and sending the SAS signal to an external hard disk backboard.
10. The method of claim 9, wherein the resetting the output parameter via a dip switch comprises:
measuring the integrity of the PCIE signal;
and adjusting the dial switch, checking the signal quality of the eye pattern, and determining the output parameters of the PCIE signals meeting the set requirements.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610305191.1A CN106021151A (en) | 2016-05-09 | 2016-05-09 | Signal enhancing board as well as signal enhancing method and system |
| PCT/CN2017/075913 WO2017193683A1 (en) | 2016-05-09 | 2017-03-08 | Signal enhancement board, and signal enhancement method and system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610305191.1A CN106021151A (en) | 2016-05-09 | 2016-05-09 | Signal enhancing board as well as signal enhancing method and system |
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| CN106021151A true CN106021151A (en) | 2016-10-12 |
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| WO (1) | WO2017193683A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017193683A1 (en) * | 2016-05-09 | 2017-11-16 | 浪潮电子信息产业股份有限公司 | Signal enhancement board, and signal enhancement method and system |
| CN108874712A (en) * | 2018-05-30 | 2018-11-23 | 郑州云海信息技术有限公司 | A kind of PCIE Riser card and hard disk VPP ignition device |
| CN109947685A (en) * | 2019-03-19 | 2019-06-28 | 浪潮商用机器有限公司 | A kind of signal enhancing device and OpenPOWER server |
| CN113722255A (en) * | 2021-09-01 | 2021-11-30 | 浙江大华技术股份有限公司 | Signal quality processing method, device and system |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0818735A2 (en) * | 1996-07-09 | 1998-01-14 | Fujitsu Limited | Input buffer circuit coping with high-frequency clock signal |
| CN101667151A (en) * | 2009-09-04 | 2010-03-10 | 浪潮电子信息产业股份有限公司 | Signal integrity testing method based on server PCI-Express |
| CN101923531A (en) * | 2009-06-12 | 2010-12-22 | 芯发威达电子(上海)有限公司 | Interface card with extensible output/input interface |
| CN102255773A (en) * | 2011-06-27 | 2011-11-23 | 中兴通讯股份有限公司 | Method for testing back board signal of communication equipment and testing board |
| CN102751639A (en) * | 2012-07-27 | 2012-10-24 | 曙光信息产业(北京)有限公司 | PCIe (peripheral component interface express) electric signal transmission cable |
| CN202904469U (en) * | 2012-06-29 | 2013-04-24 | 中国船舶重工集团公司第七0九研究所 | Reinforced computer high-speed serial interface signal integrity device |
| CN103987191A (en) * | 2014-05-16 | 2014-08-13 | 浪潮电子信息产业股份有限公司 | Method for reducing influence of AC coupling capacitor PAD on transmission of high-speed serial signals |
| CN104951268A (en) * | 2015-06-12 | 2015-09-30 | 山东超越数控电子有限公司 | Method for implementing extended high-performance graphics card based on CPCI |
| CN104994687A (en) * | 2015-06-29 | 2015-10-21 | 浪潮电子信息产业股份有限公司 | Design method for improving impedance mismatch of differential routing |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8484631B2 (en) * | 2011-03-30 | 2013-07-09 | Phoenix Technologies Ltd. | Supporting hardware configuration changes in a UEFI firmware component |
| CN102566680A (en) * | 2011-12-31 | 2012-07-11 | 曙光信息产业股份有限公司 | SAS (serial attached small computer system interface) back board |
| CN203616749U (en) * | 2013-10-23 | 2014-05-28 | 北大方正集团有限公司 | Device for realizing high-speed board level communication |
| CN203552155U (en) * | 2013-11-22 | 2014-04-16 | 浪潮电子信息产业股份有限公司 | Hard disc plug device based on PCIE slots |
| CN204904151U (en) * | 2015-09-09 | 2015-12-23 | 浪潮电子信息产业股份有限公司 | Built -in switching card |
| CN106021151A (en) * | 2016-05-09 | 2016-10-12 | 浪潮电子信息产业股份有限公司 | Signal enhancing board as well as signal enhancing method and system |
-
2016
- 2016-05-09 CN CN201610305191.1A patent/CN106021151A/en active Pending
-
2017
- 2017-03-08 WO PCT/CN2017/075913 patent/WO2017193683A1/en active Application Filing
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0818735A2 (en) * | 1996-07-09 | 1998-01-14 | Fujitsu Limited | Input buffer circuit coping with high-frequency clock signal |
| CN101923531A (en) * | 2009-06-12 | 2010-12-22 | 芯发威达电子(上海)有限公司 | Interface card with extensible output/input interface |
| CN101667151A (en) * | 2009-09-04 | 2010-03-10 | 浪潮电子信息产业股份有限公司 | Signal integrity testing method based on server PCI-Express |
| CN102255773A (en) * | 2011-06-27 | 2011-11-23 | 中兴通讯股份有限公司 | Method for testing back board signal of communication equipment and testing board |
| CN202904469U (en) * | 2012-06-29 | 2013-04-24 | 中国船舶重工集团公司第七0九研究所 | Reinforced computer high-speed serial interface signal integrity device |
| CN102751639A (en) * | 2012-07-27 | 2012-10-24 | 曙光信息产业(北京)有限公司 | PCIe (peripheral component interface express) electric signal transmission cable |
| CN103987191A (en) * | 2014-05-16 | 2014-08-13 | 浪潮电子信息产业股份有限公司 | Method for reducing influence of AC coupling capacitor PAD on transmission of high-speed serial signals |
| CN104951268A (en) * | 2015-06-12 | 2015-09-30 | 山东超越数控电子有限公司 | Method for implementing extended high-performance graphics card based on CPCI |
| CN104994687A (en) * | 2015-06-29 | 2015-10-21 | 浪潮电子信息产业股份有限公司 | Design method for improving impedance mismatch of differential routing |
Non-Patent Citations (1)
| Title |
|---|
| 袁焱: "PCIE2.0远距离传输的研究与实现", 《中国优秀博硕士学位论文全文数据库 信息科技辑》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017193683A1 (en) * | 2016-05-09 | 2017-11-16 | 浪潮电子信息产业股份有限公司 | Signal enhancement board, and signal enhancement method and system |
| CN108874712A (en) * | 2018-05-30 | 2018-11-23 | 郑州云海信息技术有限公司 | A kind of PCIE Riser card and hard disk VPP ignition device |
| CN109947685A (en) * | 2019-03-19 | 2019-06-28 | 浪潮商用机器有限公司 | A kind of signal enhancing device and OpenPOWER server |
| CN109947685B (en) * | 2019-03-19 | 2020-12-18 | 浪潮商用机器有限公司 | Signal enhancement device and OpenPOWER server |
| CN113722255A (en) * | 2021-09-01 | 2021-11-30 | 浙江大华技术股份有限公司 | Signal quality processing method, device and system |
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