CN104486624B - A kind of CAVLC entropy decoders - Google Patents
A kind of CAVLC entropy decoders Download PDFInfo
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Abstract
The invention discloses a kind of CAVLC entropy decoders and entropy decoding method.The decoder includes CAVLC controllers, decoder module and memory module and data concatenation module.The decoder situation less to nonzero coefficient in code stream has done special optimization；Bypass circuit is added in CAVLC controllers and decoding intermodule and carries out the judgement that decoded state redirects in advance, to save the clock cycle；And completed by the decoding of the preceding distance of swimming with amplitude prefix decoder and in a module.The present invention has saved area overhead while entropy decoding efficiency is improved.
Description
Technical field
The present invention relates to video coding and decoding technology field, relates more specifically to CAVLC entropy decoders and entropy decoding method.
Background technology
CAVLC is a kind of for reducing bit rate and making full use of the entropy coding of statistical redundancy.Decoded as video
The first step in frame, entropy decoding have video decoding performance very big influence.Using most in current coding and decoding video
Widely H.264 in standard, it is specified that entropy coding can use the adaptive variable length based on context to encode (CAVLC) and based on upper
Adaptive arithmetic code (CABAC) hereafter.Wherein, the more previous MPEG-1 of the code efficiency of CAVLC and Moving Picture Experts Group-2 have
Significantly improve, and implementation complexity is then low much compared with for CABAC, be used widely in Video coding.
In CAVLC decoders, it is usually directed to the decoding of following six kinds of syntactic elements：The number of nonzero coefficient, hangover system
The amplitude of nonzero coefficient beyond several number, the symbol of each hangover coefficient, hangover coefficient, last nonzero coefficient leading zero
Zero number between number, current non-zero coefficient and previous nonzero coefficient.
General decoding step is as follows：Table look-up first and solve the number of nonzero coefficient and the number of hangover coefficient, then solve
The sign bit of each hangover coefficient, then solves the amplitude of the nonzero coefficient in addition to the coefficient that trails, then solve last nonzero coefficient
The number of leading zero, finally solves before each nonzero coefficient 0 number.
Traditional CAVLC entropy decoders are usually by louver moudling before coefficient flags position module, hangover coefficient symbols module, amplitude
Block, amplitude suffix module, total zero digital-to-analogue block, preceding distance of swimming module totally six function modules, plus a CAVLC control module, with
And corresponding memory module is composed.Since decoding step and module are more, the decoding of each module again relies on above mould
Block output as a result, causing that each module stand-by period is longer, and overall decoding efficiency is relatively low.
At present, the optimization for CAVLC decoders, which is concentrated mainly on, improves its decoding efficiency and improves on decoding speed.With
It is the representational scheme of two of which down：
1) method [2] of bypass circuit module is added.The decoding parametric that this method is obtained upper level decoder module
Next stage decoder state machine is transferred to from bypass circuit unit and redirects control module and next stage decoder module, and the condition of reducing is sentenced
The time waited when disconnected, improves decoding efficiency to a certain extent, but its structure is more complicated, between module and module, module with
More line is needed between register, brings larger area overhead.
2) method [3] of the look-up table based on optimization.This method is by the number according to preceding zero setting in code word by coeff_
Token look-up tables are grouped again, during decoding before zero setting number and code word suffix table look-up for index, table look-up time so as to reduce
Number.But when QP is larger, the number of the preceding zero setting of coeff_token code words is less, and the method is to decoded acceleration effect unobvious.
The content of the invention
(1) technical problems to be solved
Present invention seek to address that optimization efficiency is not high when QP is larger in code stream and area for decoder of the prior art
The problem of expense is big.
(2) technical solution
In view of the problem of mentioned above, realization and method the present invention provides a kind of new CAVLC entropy decoders, to being
The less situation of number has done special optimization, judges whether to enter next decoded state in advance using less bypass circuit, and
The decoding of the preceding distance of swimming is rebuild to merge with coefficient block and is completed in a module.It can efficiently be decoded and reduce area overhead.
In order to solve the above technical problems, the present invention proposes a kind of CAVLC entropy decoders, including CAVLC controllers, decoding mould
Block, memory module and data concatenation module, wherein：It is defeated that the CAVLC controllers include state transition control module, hangover symbol
Go out module, coefficient amplitude computing module, inputted for control stream, coordinate the work of each module, decode to obtain according to each module
Syntactic element carry out hangover symbol and amplitude decoding；The decoder module is used for the coefficient flags that code word is solved from code stream
Position and the prefix and the preceding distance of swimming of total zero number and each amplitude；The memory module is for temporarily storing decoder module and CAVLC
The syntax element value that controller solves；The data concatenation module exports after coefficient amplitude is reconfigured splicing.
Embodiment according to the present invention, the decoder module include coefficient flags position decoder module, total zero number solution
Code module, amplitude prefix decoder module and preceding distance of swimming decoder module.
Embodiment according to the present invention, the memory module include nonzero coefficient register, hangover coefficient register
Device, amplitude prefix register, total zero number register, suffix code length register, residue zero count register, preceding distance of swimming register, non-
Zero coefficient amplitude memory and coefficient amplitude memory.
Embodiment according to the present invention, the CAVLC controllers are after coefficient flags position is solved, to the coefficient that trails
Number is judged in advance, if hangover coefficient number is 0, decoder skips hangover symbol decoding, carries out amplitude decoding.
Embodiment according to the present invention, the CAVLC controllers are after hangover symbol has been solved, to nonzero coefficient
The number of number and the coefficient that trails is judged, if equal, shows that there is no the nonzero coefficient in addition to the coefficient that trails, decoder to jump
Amplitude decoding is crossed, carries out total zero number decoder.
Embodiment according to the present invention, the CAVLC controllers further include amplitude suffix decoder module, it is used
Suffix code length is initialized in the nonzero coefficient and hangover coefficient in coefficient flags decoded state, obtained according to decoding,
In amplitude decoded state, dynamic is made to suffix code length according to decoded coefficient amplitude and is updated.
Embodiment according to the present invention, the CAVLC controllers and decoding intermodule, further include parameter transmission
Circuit, it is used for the parameter value that will be obtained in decoder module, passes to CAVLC controllers in current period, carries out state in advance
Machine redirects judgement.
Embodiment according to the present invention, includes the amplitude prefix decoder module in preceding distance of swimming decoder module,
When the distance of swimming decodes before progress, it is more than 6 situations for the number of residue zero, the value of the preceding distance of swimming can be calculated according to amplitude prefix decoder module
Arrive.
The present invention also proposes a kind of CAVLC entropy decoding methods, and applied in CAVLC decoders, CAVLC decoders include
CAVLC controllers, decoder module, memory module and data concatenation module, the coding/decoding method include the following steps：Step S1：
The nonzero coefficient number and hangover symbol numbers tabled look-up in definite code stream, and the initial value of suffix code length is set according to its value；Step
Rapid S2：When symbol numbers of trailing are more than zero, the value of symbol of each hangover coefficient is sequentially solved；Step S3：Solve Current Transform
The prefix code and suffix code of coefficient, are calculated amplitude and judge whether to need decoded nonzero coefficient, if being repeated in the presence of if
This step, until solving all nonzero coefficients；Step S4：Table look-up and solve total zero value, as the initial value of the number of residue zero；
Step S5：Counted according to residue zero, table look-up and solve the value of the preceding distance of swimming, and dynamic updates residue zero and counts, and repeats the step, up to
Only remain last nonzero coefficient or the number of residue zero is equal with the preceding distance of swimming；Step S6：According to hangover value of symbol, the coefficient solved
Amplitude and preceding run value reconstructed coefficients block, export after zig-zag is scanned.
(3) beneficial effect
During the present invention is to CAVLC entropy decodings, the less situation of nonzero coefficient has done special optimization in code stream, is controlling
Bypass circuit is added between module and decoder module carry out state machine in advance and redirect judgement, and by the decoding of the preceding distance of swimming and coefficient block weight
Build merging to complete in a module, so as to improve the work efficiency of entropy decoder, also have to its area overhead and delay certain
Improve, overall decoded speed can be effectively improved.
Brief description of the drawings
Fig. 1 is the CAVLC entropy decoder structure diagrams that the present invention realizes；
Fig. 2 is that the CAVLC entropy decoder state machines that the present invention realizes redirect schematic diagram；
Fig. 3 is that hangover coefficient condition judges schematic diagram；
Fig. 4 is nonzero coefficient number condition judgment schematic diagram；
Fig. 5 is the prefix_value code tables [1] H.264 provided in standard；
Fig. 6 is the run_before code tables [1] H.264 provided in standard.
Embodiment
CAVLC entropy decoders proposed by the present invention include CAVLC controllers, decoder module, data concatenation module and storage
Module.
The CAVLC controllers include state transition control module, hangover symbol output module, coefficient amplitude and calculate mould
Block.
The decoder module includes coefficient flags position decoder module (coeff_token), total zero number decoder module (total_
Zero), amplitude prefix decoder module (level_prefix) and preceding distance of swimming decoder module (run_before).
The memory module includes nonzero coefficient register (TotalCoeff), hangover coefficient register
(TrailingOnes), amplitude prefix register (level_prefix), total zero number register (total_zeros), suffix code
Long register (suffix_length), residue zero count register (zeros_left), preceding distance of swimming register (run_before),
Nonzero coefficient amplitude memory (LevelVal) and coefficient amplitude memory (coeff_level).
The CAVLC controllers are inputted for control stream, coordinate the work of each module by state machine, according to each module
The decoding that obtained syntactic element carries out hangover symbol and amplitude is decoded, finally after the completion of the decoding of all syntactic elements, will be
Number amplitude exports after reconfiguring splicing.
The CAVLC controllers, when carrying out state transition control, the situation less to coefficient has done special optimization：
1) under the decoded state of coefficient flags position, nonzero coefficient number and hangover coefficient number are judged in advance.If not
Zero coefficient number is 0, then terminates current block decoding；If coefficient number of trailing is 0, hangover symbol decoded state is directly skipped, such as
Shown in Fig. 3.
2) under symbol decoded state of trailing, the judgement to nonzero coefficient number is added, if total nonzero coefficient number
It is equal with the number for the coefficient that trails, show there is no the nonzero coefficient in addition to the coefficient that trails, state machine skips amplitude decoding, directly
Tap into total zero number decoder state, as shown in Figure 4.
Parameter transmission circuit is further included between CAVLC controllers and each decoder module, for the ginseng that will be obtained in decoder module
Numerical value, CAVLC controllers are passed in current period, and carry out state machine in advance redirects judgement, avoids register amplitude from completing
Judge that state transition causes unnecessary wait again afterwards.
The amplitude prefix decoder module, when realizing as submodule, included in preceding distance of swimming decoder module.By scheming
5th, code table can be seen that when zeros_left is more than 6, if front two is that the value of zero, run_before is straight in code stream in Fig. 6
Connect and add 4 to provide by the value of level_prefix, without by tabling look-up or combinational logic obtains, having saved expense again.
The present invention also proposes the CAVLC entropy decoding methods applied to CAVLC decoders, includes the following steps：
Step S1：The nonzero coefficient number and hangover symbol numbers tabled look-up in definite code stream, and suffix is set according to its value
The initial value of code length；
Step S2：When symbol numbers of trailing are more than zero, the value of symbol of each hangover coefficient is sequentially solved；
Step S3：The prefix code and suffix code of current transform coefficient are solved, amplitude is calculated and judges whether to need
Decoded nonzero coefficient, if repeating this step in the presence of if, until solving all nonzero coefficients；
Step S4：Table look-up and solve total zero value, as the initial value of the number of residue zero；
Step S5：Counted according to residue zero, table look-up and solve the value of the preceding distance of swimming, and dynamic updates residue zero and counts, and repeats this
Step, until only surplus last nonzero coefficient or the number of residue zero are equal with the preceding distance of swimming；
Step S6：According to the hangover value of symbol, coefficient amplitude and preceding run value reconstructed coefficients block solved, by zig-zag
Exported after scanning.
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in further detail.
As shown in Figure 1, the entropy decoder that the present invention realizes includes CAVLC controllers, decoder module and memory module sum number
According to concatenation module.The CAVLC controllers include state transition control module (11), hangover symbol output module (12), coefficient
Amplitude computing module (13).The decoder module, including coefficient flags position decoder module (21), total zero number decoder module (22),
Amplitude prefix decoder module (23) and preceding distance of swimming decoder module (24).
The memory module, including nonzero coefficient register (31), hangover coefficient register (32), amplitude prefix register
(33), it is total zero number register (34), suffix code length register (35), residue zero count register (36), preceding distance of swimming register (37),
Nonzero coefficient amplitude memory (38) and coefficient amplitude memory (39).
A state machine, the state representation of state machine are constituted together with CAVLC controllers, decoder module and memory module
The decoding residing stage.State machine includes initialization, the decoding of coefficient flags position, the decoding of hangover symbol, amplitude decoded state, amplitude
Output state, total zero number decoder, the preceding distance of swimming decode this seven states, and it is as shown in Figure 2 to redirect relation between each state.Complete solution
Code step is as follows：
Step 1：Entropy decoder receives enable signal, and into init state, each register and memory is cleared, just
After the completion of beginningization, state machine jumps to coefficient flags position decoded state.
Step 2：In the decoded state of coefficient flags position, decoder decodes coefficient flags position decoder module
Coeff_token_TotalCoeff, coeff_token_TrailingOnes are transferred to respectively by bypass circuit
TotalCoeff and TrailingOnes registers.
Value according to flag bit initializes the value of amplitude suffix lengths register, works as coeff_token_
When TotalCoeff is more than 10 and coeff_token_TrailingOnes and is less than 3, the value of suffix_length is assigned to 1, no
Then it is assigned to 0.
State transition judgement is carried out, if nonzero coefficient number is zero, terminates the decoding of current residual block, state machine redirects
Init state is returned to, waits for next decoding residual block.
If nonzero coefficient number is not zero, as shown in figure 3, carrying out state transition judgement according to the number of hangover coefficient：
If coefficient number of trailing is zero, state machine skips hangover Coefficient decoding state, jumps directly to amplitude decoded state,
Perform step 4；
If hangover coefficient number is not zero, state machine is redirected into hangover Coefficient decoding state.
Step 3：In symbol decoded state of trailing, CAVLC controllers are successively to each hangover coefficient in incoming bit stream
Symbol decoded, and result is output in LevelVal.
Process as shown in Figure 4, the value of TrailingOnes and TotalCoeff are compared, and state is carried out according to result
Redirect：
If equal, show to need to decode without other nonzero coefficients in addition to the coefficient that trails, state machine directly redirects entrance
Total zero number decoder state, performs step 6；
If the value of TrailingOnes is less than TotalCoeff, state machine is redirected into amplitude decoded state.
Step 4：In amplitude decoded state, level_ that CAVLC control modules first solve prefix amplitude module
Prefix_value is transferred to level_prefix registers, and updates levelSuffixSize's according to suffix_length
Value.
Then first is solved on high frequency position according to the value of level_prefix_value and suffix_length not solve
The amplitude of the non-hangover coefficient of code, and it is output to the corresponding positions of LevelVal.State machine is finally set to jump to amplitude output
State.
Step 5：In amplitude output state, the number of current decoded nonzero coefficient is judged first, if also having
Not decoded nonzero coefficient, then state machine jump back to amplitude decoded state, continue to solve next non-hangover coefficient amplitude.
If all coefficient amplitudes are decoded, then judge the result of startIdx-endIdx+1, state jump is carried out
Turn：
If being equal to TotalCoeff, CAVLC controller output factor amplitudes are into coeff_level, after splicing again
Output, completes the decoding of current residual block, state machine jumps back to original state；
If differing, into total zero number decoder state.
Step 6：Under total zero number decoder state, total_ that CAVLC control modules solve total zero number decoder module
Zeros_value is transferred to zeros_left registers.
The value of total zero number is judged again, state transition is carried out according to result：
If total_zeros_value is 0, i.e., no coefficient is 0 situation, and the value of LevelVal is transferred directly to
Coeff_level, exports after splicing, completes the decoding of current residual block, and state machine jumps back to original state.
If total_zeros_value is not 0, then the number of nonzero coefficient is judged.
If TotalCoeff is equal to 1, show an only nonzero coefficient, it is not necessary to run_before is solved, by LevelVal
In unique zero coefficient values be passed directly on the correspondence position of coeff_level, exported after splicing, complete the solution of current residual block
Code, state machine jump back to original state.
If TotalCoeff is not equal to 1, show there are multiple nonzero coefficients to need to decode, distance of swimming decoding before state machine jumps to
State.
Step 7：Under preceding distance of swimming decoded state, run_ that CAVLC controllers are solved according to preceding distance of swimming decoder module
The value of before_value, updates the value of zeros_left registers, then by each coefficient amplitude in LevelVal, according to trip
Journey, the corresponding positions of write-in coeff_level.
Remaining nonzero coefficient number is judged：
When only remaining last nonzero coefficient, it is not necessary to continue to solve the value of run_before, directly by lowest frequency
LevelVal is assigned to the relevant position of coefficient amplitude memory coeff_level.Complete the decoding of current residual block
Sentence when remaining nonzero coefficient more than one, then to the size of zeros_left and run_before_value
It is disconnected：
If equal, show in addition to current non-zero coefficient,, can be suitable successively there is no leading zero before remaining nonzero coefficient
Sequence output factor amplitude gives coeff_level memories.Complete the decoding of current residual block.
If differing, show that also there are leading zero to be decoded, state machine cycles to perform the work of step 7, until current residual
Poor block decoding is completed.
16 coefficient amplitudes in coeff_level memories reorder it through data concatenation module by zig-zag scannings
Afterwards, it is spliced into full line output.CAVLC controllers will decode completion signal and draw high, and jump to original state, wait next residual
The decoding of poor block.
The present invention adds the mode of bypass circuit between control module and decoder module, and progress state machine, which redirects, in advance sentences
It is disconnected；The situation less to nonzero coefficient in code stream adds corresponding Rule of judgment, to skip unnecessary decoded state；And by before
The distance of swimming is decoded to rebuild to merge with coefficient block and completed in a module.The entropy decoder realized by above method possesses decoding efficiency
The characteristics of height, area overhead is small.
Particular embodiments described above, has carried out the purpose of the present invention, technical solution and beneficial effect further in detail
Describe in detail bright, it should be understood that the foregoing is merely the present invention specific embodiment, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done, should be included in the protection of the present invention
Within the scope of.
Claims (4)
1. a kind of CAVLC entropy decoders, it is characterised in that spelled including CAVLC controllers, decoder module, memory module and data
Connection module, wherein：
The CAVLC controllers include state transition control module, hangover symbol output module, coefficient amplitude computing module, use
Inputted in control stream, coordinate the work of each module, the syntactic element decoded according to each module carries out hangover symbol and width
The decoding of value；
The decoder module be used for the coefficient flags position that code word is solved from code stream and total zero number and each amplitude prefix and
The preceding distance of swimming；
The syntax element value that the memory module solves for temporarily storing decoder module and CAVLC controllers；
The data concatenation module exports after coefficient amplitude is reconfigured splicing,
The CAVLC controllers judge hangover coefficient number after coefficient flags position is solved in advance, if hangover coefficient
Number is 0, and decoder skips hangover symbol decoding, carries out amplitude decoding,
The CAVLC controllers solved hangover symbol after, to nonzero coefficient number with hangover coefficient number judge, if
It is equal, show there is no the nonzero coefficient in addition to the coefficient that trails, decoder skips amplitude decoding, carries out total zero number decoder,
The CAVLC controllers and decoding intermodule, further include parameter transmission circuit, it is used to obtain in decoder module
Parameter value, CAVLC controllers are passed in current period, and carry out state machine in advance redirects judgement.
2. CAVLC entropy decoders according to claim 1, it is characterised in that
The decoder module includes coefficient flags position decoder module, total zero number decoder module, amplitude prefix decoder module and preceding trip
Journey decoder module.
3. CAVLC entropy decoders according to claim 1, it is characterised in that
The memory module includes nonzero coefficient register, hangover coefficient register, amplitude prefix register, total zero number deposit
Device, suffix code length register, residue zero count register, preceding distance of swimming register, nonzero coefficient amplitude memory and coefficient amplitude and deposit
Reservoir.
4. CAVLC entropy decoders according to claim 2, it is characterised in that the width is included in preceding distance of swimming decoder module
It is worth prefix decoder module, when the distance of swimming decodes before progress, is more than 6 situations for the number of residue zero, the value of the preceding distance of swimming can be according to amplitude
Prefix decoder module is calculated.
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Address after: Room 701, 7th Floor, Building 56, No. 2, Jingyuan North Street, Beijing Economic and Technological Development Zone, Daxing District, Beijing 100176 (Beijing Pilot Free Trade Zone High-end Industry Zone Yizhuang Group) Patentee after: Beijing Jilang Semiconductor Technology Co., Ltd. Address before: 519031 room 532, building 18, No. 1889, Huandao East Road, Hengqin District, Zhuhai City, Guangdong Province Patentee before: Zhuhai Jilang Semiconductor Technology Co.,Ltd. |
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