CN103227924A - Arithmetic coder and coding method - Google Patents
Arithmetic coder and coding method Download PDFInfo
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Abstract
The invention discloses a design method of an arithmetic coder, and a realization device, which comprise a front-buffer design, algorithm structure joint optimization, a muti-bin processing technology and a hybrid context storage mechanism, wherein the front-buffer design is used for solving the problems that the number of binary sequences (bin) generated by a macroblock after binary conversion can fluctuate within a very wide range, but the number of the binary sequences (bin) processed by a binary arithmetic coding module (BAC) in unit time is limited; the algorithm structure joint optimization mainly uses a time borrowing technology to place low processing after range processing; the muti-bin processing technology utilizes MPS (microprocessor system) computation more easily compared with an LPS (lean process solution), so that people can process multiple MPSs in a clock period; and the hybrid context storage mechanism is a storage method invented for a special application of a 2bins/cycle throughput rate, can store a large number of context models, and can conduct quick memory on the models. The arithmetic coder and the coding method are applicable to coding of a multi-stage pipeline structure, in particular to real-time coding of high-definition resolution.
Description
Technical field
The present invention relates to the digital video decoding technical field, relate in particular to senior entropy coder of a kind of AVS and coding method.
Background technology
Video coding technique and video encoding standard are the technical foundation that comprises audio frequency and video industries such as Digital Television, Internet video, mobile TV, MP3.The source encoding standard that present audio frequency and video industry can be selected has four: MPEG-2, MPEG-4, MPEG-4AVC(are called for short AVC, also claim JVT, H.264), AVS, AVS(Audio Video coding Standard wherein, audio/video encoding standard) be the abbreviation of " information technology advanced audio/video coding " series standard, being the second generation source encoding standard that China possesses independent intellectual property right, also is the general character basic standard of digital audio/video industry.These source encoding standards generally adopt a kind of hybrid coding method removing the redundant information between huge information source data, as: spatial redundancy, time redundancy, comentropy redundancy.
Entropy coding is the requisite key link of video coding system, and it is responsible for utilizing the comentropy principle to remove the comentropy redundancy, has reached the purpose of data compression.Wherein, MPEG-2 adopts huffman coding (Huffman Code), H.264 adopts based on context-adaptive variable-length encoding (CAVLC) with based on context adaptive binary arithmetic coding (CABAC) with AVS.CABAC is a kind of novel efficient entropy coding method, and its design is based on 3 steps such as binarization, context modeling, binary arithmetic codings.CABAC is code period with the sheet, the bin that the syntactic element binarization of whole piece is obtained carries out interval iteration and divides, thereby obtain a subinterval, in this subinterval, appoint then and get a value and represent this sheet grammer element, so, on average meaning, the bit number that obtains behind the independent bin value coding may be mark, overcome the shortcoming that the CAVLC coding is necessary for the code word of single allocation of symbols integer code length, the easier limit entropy that approaches, obtain higher code efficiency, therefore, the encoder that the AVS standard will adopt CABAC to encode is called senior entropy coder.But the computational complexity of CABAC is apparently higher than CAVLC.
For coding HD video that can be real-time, we need increase the throughput of encoder, must take into account system delay simultaneously, and present arithmetic encoder is paid close attention to throughput mostly, pays close attention to lessly to system delay.
Summary of the invention
In order to overcome the above problems, the object of the present invention is to provide a kind of comprising: front-buffer design, algorithm structure combined optimization, muti-bin treatment technology and the encoder and the coding method that mix the context memory mechanism.
In the middle of the design of arithmetic encoder, because Binary Conversion module (binarizer) can produce a large amount of binary sequences (bin) by handling a plurality of syntactic elements simultaneously, thereby the throughput of binary arithmetic coding module (BAC) becomes the bottleneck of design.For increasing throughput, reduce to postpone, we adopt the scheme of macro-block level flowing water, but, because a macro block can fluctuate in a very big scope through binary sequence (bin) number that produces after the Binary Conversion, and the binary sequence (bin) that binary arithmetic coding module (BAC) was handled in unit interval number is limited, cushions so we have added a buffer between Binary Conversion module (binarizer) and binary arithmetic coding module (BAC).Certainly, buffer is big more, and the input of binary arithmetic coding module (BAC) is level and smooth more, and it is easier that design is got up, but that the negative effect that brings like this is the delay of system is big more, and chip area has also become greatly simultaneously.So we need do a compromise, it be easy to show that, in Fig. 3, if for zero-time t arbitrarily, at a regular time section T
0In, there is a maximum total amount Q who imports buffer
0, we only need the size of buffer to be set to Q so
0, and the output of buffer is made as
Can guarantee buffer overflow never.
The employing of the binary arithmetic coding module (BAC) of the present invention's structure is the basic structure of 2bins/cycle throughput fixedly.The critical path of binary arithmetic coding module (BAC) is the calculating of low among the LPS in the iterative process, thereby the difficult point of this design is how two LPS occur continuously finishes dealing with in a clock cycle.Find by observing us, the iterative computation of range is only relevant with self, and its operating time is far smaller than operating time to low, so, as shown in Figure 5, we can fulfil some calculation procedures of low ahead of schedule behind the intact range of the iterative computation first time, this just can reduce the operating time of the second time of low during iterative computation.In addition, at log-domain, range is assigned to represent that when LPS occurred, we carried out the renormalization operation to the integer part of range by integer part and fractional part, and this can simplify the calculating of low in the iterative computation second time.By the effective utilization to these two features, we have obtained a fixedly 2bins/cycle throughput, and system delay is than the basic framework of the encoder few 33% of 1bin/cycle.
As shown in Figure 6, we adopt the muti-bin treatment technology further to improve throughput.This technology is mainly used in producing the maximum residual error coefficient optimization of bin number.With AVS is example, and we are encoded to Level(absLevel and sign with residual error coefficient) and the Run number right, it is adopted a primitive encoding (unary) scheme.Bin indexes uses identical context greater than 1 absLevel or bin indexes greater than 0 Run, and we claim that such bins is SC bins.Owing to SC bins forms by 0 and one 1 of several successive, so under most of situation, the contextual MPS of SC bins is 0, and the calculating of MPS is much simple than LPS, so we can handle a plurality of 0 a clock cycle.
The present invention adopts the two-stage storage organization of being made up of context RAM and local context buffer, and because the throughput of the binary arithmetic coding module (BAC) that the present invention adopts is 2bins/cycle, two continuous bin may belong to different syntactic elements (SE), mapping to context RAM has caused certain difficulty like this, for this reason, we have designed dual-port RAM and corresponding local buffer.Further observe, we find, belong to different syntactic element (SE) two bin second bin bin index often 0(that is to say first bin that often belongs to a syntactic element), so the present invention proposes mixing memory mechanism as shown in Figure 7: all context models of first bin that belong to two bin of different syntactic element (SE) are stored in registers group (register group) lining, other context model is stored in the dual-port RAM, and we just can realize the quick storage of context model like this.
Description of drawings
Fig. 1 is the present invention residing position in whole encoder;
Fig. 2 is the main functional modules block diagram based on contextual binary arithmetic coder that the present invention adopts;
Fig. 3 is binary arithmetic coding module (BAC) the buffer model before that the present invention proposes;
Fig. 4 is the arithmetic encoder whole design and framework that the present invention proposes;
Fig. 5 the first half is the optimization method to the worst case of continuous two LPS that the present invention proposes, and the latter half is a muti-bin signal sequential chart;
Fig. 6 is the muti-bin embodiment that the present invention takes residual error coefficient;
Fig. 7 is the mixing storage means that the present invention proposes;
Fig. 8 is the selection foundation of front buffer size in the embodiment of the invention.
Embodiment
The position of present embodiment in the whole video coded system as shown in Figure 1, adopt the scheme of macro-block level flowing water, its concrete module architectures as shown in Figure 4, wherein A represents Binary Conversion module (binarizer), B represents context management module (CM), and C represents binary arithmetic coding module (BAC).The technical scheme that proposes in these 3 modules with regard to the present invention is respectively done the example elaboration below.
Because a macro block can fluctuate in a very big scope through binary sequence (bin) number that produces after the Binary Conversion, and the binary sequence (bin) that binary arithmetic coding module (BAC) was handled in unit interval number is limited, cushions so we have added a buffer between Binary Conversion module (binarizer) and binary arithmetic coding module (BAC).Certainly, buffer is big more, and the input of binary arithmetic coding module (BAC) is level and smooth more, and it is easier that design is got up, but that the negative effect that brings like this is the delay of system is big more, and chip area has also become greatly simultaneously.So we need do a compromise, it be easy to show that, in Fig. 3, if for zero-time t arbitrarily, at a regular time section T
0In, there is a maximum total amount Q who imports buffer
0, we only need the size of buffer to be set to Q so
0, and the output of buffer is made as
Can guarantee buffer overflow never.So we just must find Q when specifically implementing
0And T
0, we have tested a series of video sequence for this reason, concrete outcome as shown in Figure 8, as can be seen from the figure, the T of the present invention design
0Adopt macro-block line of coding (is 120 macro blocks) required time for resolution is the video sequence of 1080P, buffer size Q
0It is just passable to store 100657 bin, and for the sake of assurance, the buffer that the present invention adopts can store 110000 bin.
The employing of the binary arithmetic coding module (BAC) of the present invention's structure is the basic structure of 2bins/cycle throughput fixedly.The critical path of binary arithmetic coding module (BAC) is the calculating of low among the LPS in the iterative process, thereby the difficult point of this design is how two LPS occur continuously finishes dealing with in a clock cycle.Find by observing us, the iterative computation of range is only relevant with self, and its operating time is far smaller than operating time to low, so, as shown in Figure 5, we can fulfil some calculation procedures of low ahead of schedule behind the intact range of the iterative computation first time, this just can reduce the operating time of the second time of low during iterative computation.In addition, at log-domain, range is assigned to represent that when LPS occurred, we carried out the renormalization operation to the integer part of range by integer part and fractional part, and this can simplify the calculating of low in the iterative computation second time.By the effective utilization to these two features, we have obtained a fixedly 2bins/cycle throughput, and system delay is than the basic framework of the encoder few 33% of 1bin/cycle.
As shown in Figure 6, we adopt the muti-bin treatment technology further to improve throughput.This technology is mainly used in producing the maximum residual error coefficient optimization of bin number.With AVS is example, and we are encoded to Level(absLevel and sign with residual error coefficient) and the Run number right, it is adopted a primitive encoding (unary) scheme.Bin indexes uses identical context greater than 1 absLevel or bin indexes greater than 0 Run, and we claim that such bins is SC bins.Owing to SC bins forms by 0 and one 1 of several successive, so under most of situation, the contextual MPS of SC bins is 0, and the calculating of MPS is much simple than LPS, so we can handle a plurality of 0 a clock cycle.In the present embodiment, consider that the circuit delay with the worst case of two LPS of continuous programming code is complementary, we adopt the MPS processing scheme of 4-bin, can handle 3-4 continuous MPS in a clock cycle.The muti-bin processing scheme that present embodiment is adopted on average can improve 15% throughput, because quantization parameter (QP) is when diminishing, it is many that residual error coefficient becomes, the bin number that produces increases thereupon, so when diminishing, the throughput that this scheme can improve is all the more obvious at quantization parameter (QP).
The present invention adopts the two-stage storage organization of being made up of context RAM and local context buffer, and because the throughput of the binary arithmetic coding module (BAC) that the present invention adopts is 2bins/cycle, two continuous bin may belong to different syntactic elements (SE), mapping to context RAM has caused certain difficulty like this, for this reason, we have designed dual-port RAM and corresponding local buffer.Further observe, we find, belong to different syntactic element (SE) two bin second bin bin index often 0(that is to say first bin that often belongs to a syntactic element), so the present invention proposes mixing storage means as shown in Figure 7: all context models of first bin that belong to two bin of different syntactic element (SE) are stored in registers group (register group) lining, other context model is stored in the dual-port RAM, and we just can realize the quick storage of context model like this.The AVS standard that adopts specific to the present invention, for two bin that belong to different syntactic element (SE) of quick storage continuous programming code in a clock cycle, we have distributed 5 dual-port RAM and corresponding local buffer.Consider that simultaneously the bin of context weighting technique coding that adopts in the AVS standard may use two context models, and can not two such bin of continuous programming code in the coding method of we 2bins/cycle, so we adopt single-port RAM and corresponding local buffer to store the context model of such bin correspondence, we have used 324 context models altogether.
It should be noted that at last: obviously, the foregoing description only is for example of the present invention clearly is described, and is not the qualification to execution mode.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here need not also can't give exhaustive to all execution modes.And conspicuous variation of being amplified out thus or change still are among protection scope of the present invention.
Claims (7)
1. arithmetic encoder, mainly comprise Binary Conversion module, binary arithmetic coding module and context modeling module, data flow is separate between the three, there is not feedback, adopt the mode of three class pipeline to realize, it is characterized in that: the effect of described Binary Conversion module be with non-binary syntactic element unique be mapped as a binary sequence, wherein said non-binary syntactic element comprises the residual error data behind motion vector, macro block (mb) type, sub-macro block (mb) type, reference frame number and the change quantization; The effect of described context modeling module is that syntax elements encoded is set up probabilistic model, is used for the coding of current syntactic element, and after finishing coding, probabilistic model upgrades; The effect of described binary arithmetic coding module is with binary sequence and is that the context model that current syntactic element is selected is carried out arithmetic coding, the probabilistic model that binary value that described Binary Conversion module produces and context modeling module provide is sent into the binary arithmetic coding module together, and upgrades the context model of context modeling module according to the binary value that the Binary Conversion module produces.
2. arithmetic encoder according to claim 1, it is characterized in that: described Binary Conversion module can be handled a plurality of syntactic elements simultaneously, being provided with a buffer between itself and binary arithmetic coding module is the binary value buffer, is used to handle the unsettled binary sequence number that each macro block produces.
3. a kind of arithmetic encoder according to claim 1 is characterized in that: it is SE line buffer that described context modeling module adopts a buffer, stores adjacent syntax element value, is used for context and selects.
4. a kind of arithmetic encoder according to claim 1, it is characterized in that: described context modeling module adopts the two-stage storage, comprise context RAM and local caches, wherein local caches is used to store the context that nearest meeting is used, and context RAM is used to deposit all contextual informations.
5. a kind of arithmetic encoder according to claim 1, it is characterized in that: described binary arithmetic coding module adopts the processing of many bits, and utilizing MPS fully is the computation complexity of maximum possible symbol these characteristics of computation complexity far below the promptly minimum possibility symbol of LPS.
6. a kind of arithmetic encoder according to claim 5, it is characterized in that: described many bit process are that to utilize range for the processing method of continuous two LPS be that the calculating of scope only relies on self, and the calculating treatmenting time of range is the characteristics of lower limit well below low, after handling range, the part operation of preliminary treatment low.
7. the coding method that counts is characterized in that: comprise the steps
The first step: the syntactic element of judging input is non-binary syntactic element, if binary syntactic element is then skipped the Binary Conversion module, non-binary syntactic element then needs to carry out binarization by the Binary Conversion module;
Second step, the string of binary characters that the first step obtains, according to the type selecting context of syntactic element, the context model of binary value and selection enters the binary arithmetic coding module together then;
In the 3rd step, according to the type of syntactic element, decision is to carry out fast coding, still directly enters the bypass encoder, encode with fixing probabilistic model, and output encoder code stream then, and upgrade context model according to coded identification.
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| CN103873870A (en) * | 2014-02-28 | 2014-06-18 | 芯原微电子(上海)有限公司 | Optimized AEC decoder |
| CN104918049A (en) * | 2015-06-03 | 2015-09-16 | 复旦大学 | Binary arithmetic coding module suitable for HEVC (high efficiency video coding) standards |
| CN105025296A (en) * | 2014-04-30 | 2015-11-04 | 北京大学 | Advance arithmetic coder and realization method thereof |
| CN107347159A (en) * | 2016-05-05 | 2017-11-14 | 谷歌公司 | The motion vector encoder carried out using dynamic reference motion vector |
| WO2018127167A1 (en) * | 2017-01-06 | 2018-07-12 | Mediatek Inc. | Method and apparatus for range derivation in context adaptive binary arithmetic coding |
| CN110419216A (en) * | 2017-03-22 | 2019-11-05 | 高通股份有限公司 | Binary arithmetic decoding is carried out by parametrization probability Estimation finite state machine |
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| JP4962476B2 (en) * | 2008-11-28 | 2012-06-27 | ソニー株式会社 | Arithmetic decoding device |
| CN102186075B (en) * | 2011-04-28 | 2012-10-10 | 北京大学 | Entropy coder and realization method thereof |
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| CN103873870B (en) * | 2014-02-28 | 2017-03-29 | 芯原微电子(上海)有限公司 | A kind of AEC decoders of optimization |
| CN103873870A (en) * | 2014-02-28 | 2014-06-18 | 芯原微电子(上海)有限公司 | Optimized AEC decoder |
| CN105025296A (en) * | 2014-04-30 | 2015-11-04 | 北京大学 | Advance arithmetic coder and realization method thereof |
| CN105025296B (en) * | 2014-04-30 | 2018-02-23 | 北京大学 | A kind of advanced mathematical encoder and its implementation |
| CN104918049A (en) * | 2015-06-03 | 2015-09-16 | 复旦大学 | Binary arithmetic coding module suitable for HEVC (high efficiency video coding) standards |
| CN107347159B (en) * | 2016-05-05 | 2020-05-19 | 谷歌有限责任公司 | Method and equipment for coding and decoding video bit stream |
| CN107347159A (en) * | 2016-05-05 | 2017-11-14 | 谷歌公司 | The motion vector encoder carried out using dynamic reference motion vector |
| WO2018127167A1 (en) * | 2017-01-06 | 2018-07-12 | Mediatek Inc. | Method and apparatus for range derivation in context adaptive binary arithmetic coding |
| US11265561B2 (en) | 2017-01-06 | 2022-03-01 | Mediatek Inc. | Method and apparatus for range derivation in context adaptive binary arithmetic coding |
| CN110419216A (en) * | 2017-03-22 | 2019-11-05 | 高通股份有限公司 | Binary arithmetic decoding is carried out by parametrization probability Estimation finite state machine |
| CN110419216B (en) * | 2017-03-22 | 2021-12-17 | 高通股份有限公司 | Binary arithmetic decoding by parameterized probability estimation finite state machines |
| US11006117B2 (en) | 2017-07-14 | 2021-05-11 | Mediatek Inc. | Method and apparatus for range derivation in context adaptive binary arithmetic coding |
| US11425386B2 (en) | 2017-07-14 | 2022-08-23 | Hfi Innovation Inc. | Method and apparatus for range derivation in context adaptive binary arithmetic coding |
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