CN101090503A - Entropy code control method and circuit - Google Patents
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Abstract
This invention discloses an entropy-coding control method and an entropy coding circuit, which generates a process result at each logic functional unit and provides it to its adjacent latter logic functional unit when the logic process in the adjacent latter logic functional unit is finished so as to avoid jam of pipelines and error entropy coding at the time when realizing pipeline way and increase process efficiency.
Description
Technical field
The present invention relates to video coding technique, particularly based on H.264 a kind of entropy coding control method and a kind of entropy coding circuit of standard.
Background technology
Based in the video encoding and decoding standard H.264, coded object is the syntactic element (SE) in the vision signal, is divided into residual error SE and non-residual error SE.
Wherein, residual error SE comprises: whether whether the expression current block has the absolute value of CBF, non-0 coefficient of expression on the current location of nonzero coefficient to subtract 1 CALM, the coefficient on the expression current location is whether 0 SCF, the coefficient on the expression current location are the data etc. of the classifications such as LSCF of last non-0 coefficient; Non-residual error SE comprises: the expression front and back are to the data of the classifications such as CBP of the non-zero situation of the refIdx of the reference picture index of prediction, the direct current of representing current brightness and chrominance block and alternating current component.
In the existing entropy coding process, adopt different coded systems to encode to non-residual error SE and residual error SE respectively.
For example, the non-residual error SE of part is adopted fixed length (Fix-length) coding, the non-residual error SE of another part is adopted Ge Lumu (Exp-golomb) coding, residual error SE is adopted adaptive variable length (Cavlc) coding; Perhaps, the non-residual error SE of part is adopted fixed length (Fix-length) coding, the non-residual error SE of part is adopted Ge Lumu (Exp-golomb) coding, other non-residual error SE and all residual error SE are adopted self adaptation arithmetic (Cabac) coding.
That is to say, generally include in the entropy coding circuit by block code, Ge Lumu coding and the required logic function unit of adaptive variable length coding; Perhaps comprise by block code, Ge Lumu coding and the required logic function unit of adaptive arithmetic code; Be that adaptive variable length coding and adaptive arithmetic code are the coded system of alternative.
As shown in Figure 1, be that the block code process of coded object comprises with non-residual error SE in the prior art: receive non-residual error SE; Search fixed length table, promptly will represent the binary bits string segmentation output of non-residual error SE according to pre-set length, the Bit String of segmentation output is coding result; Coding result to output carries out the code stream splicing.
As shown in Figure 2, be that the Ge Lumu cataloged procedure of coded object comprises with non-residual error SE in the prior art: receive non-residual error SE; Search among the Ge Lumubiao, with non-residual error SE corresponding codes result output; Coding result to output carries out the code stream splicing.
As shown in Figure 3, be that the adaptive variable length cataloged procedure of coded object comprises with residual error SE in the prior art: receive residual error SE; Residual error SE is carried out data analysis and takes absolute value; Search in the elongated table, with non-residual error SE corresponding codes result output; Coding result to output carries out the code stream splicing.Wherein, comprise Coeff_token table, Trailing_ones_sign_flag table, Level table, Run_before table in the elongated table, respectively at different residual error SE.
As shown in Figure 4, be that the adaptive arithmetic code process of coded object comprises with residual error SE and non-residual error SE in the prior art: receive residual error SE or non-residual error SE; If the SE of current reception is residual error SE, then, carry out binarization again and table look-up the residual error SE line data analysis of going forward side by side that takes absolute value, if the SE of current reception is non-residual error SE, then directly carries out binarization and table look-up; Carry out probabilistic model inquiry, promptly, search the probabilistic model table, obtain the probabilistic model of each Bit String correspondence according to binarization table look-up the expression residual error SE that obtains or the binary bits string of non-residual error SE; Upgrade corresponding probability space according to the probabilistic model that finds; Upgrade the result according to probability space and carry out normalized generation code stream; Code stream as coding result is carried out the code stream splicing.
Yet each above-mentioned coded system all is to adopt the serial process mode, after promptly the SE coding that receives being finished and being carried out code stream splicing output, just receives next SE, thereby makes that the efficient of entropy coding is not high.That is to say,, comprise the logic function unit of the realization Different Logic processing procedure that a plurality of orders link to each other for the circuit of realizing each coded system.After first logic function unit receives and handles the data that receive, export to a back logic function unit that is adjacent and begin and wait for, by follow-up one or more logic function unit orders these data are handled, after last logic function unit finishes its processing and output result, first logic function unit just stops to wait for, receives the pending data of outside input once more.Like this, make that each logic function unit in the circuit all needs to wait for for a long time, thereby reduced entropy-coding efficiency.
And, there is the identical logical process process of part between the above-mentioned different coded system, but in the prior art, still realize above-mentioned identical logical process process respectively by a plurality of logic function unit independently, promptly realize between the circuit of each coded system separate, thereby caused the waste of hardware resource.
Summary of the invention
In view of this, a main purpose of the present invention is, a kind of entropy coding control method is provided, and can improve the efficient of entropy coding.
Another main purpose of the present invention is, a kind of entropy coding circuit is provided, and can improve the efficient of entropy coding.
Another main purpose of the present invention is, another kind of entropy coding circuit is provided, and can improve the efficient of entropy coding.
A main purpose according to above-mentioned the invention provides a kind of entropy coding control method, and each logic function unit is carried out corresponding logical process process, comprising:
Each logic function unit, produced result and the logical process process of the back logic function unit that is adjacent when having finished at it, the described result that this logic function unit is obtained offers a back logic function unit that is adjacent.
Further, store the described result that this logic function unit produces for each logic function unit is provided with a register;
Described register comprises a flag bit, is used for representing whether a back logic function unit adjacent with this logic function unit can read described result from this register;
Each logic function unit further when its corresponding logic processing process has been finished, produces the completed control signal of presentation logic processing procedure;
The described result that this logic function unit is obtained offers a back logic function unit that is adjacent:
When numerical value, this logic function unit that each logic function unit can read for expression at the register flag bit of the previous logic function unit that is adjacent produced described result and a back logic function unit adjacent with this logic function unit and produced described control signal, this logic function unit is stored described result, and its corresponding register flag bit is set to represent the numerical value that can read, and a back logic function unit that allows to be adjacent reads described result from the register of this logic function unit correspondence.
Each logic function unit does not produce described result at it, but when a back logic function unit that is adjacent has produced described control signal, then the register flag bit of this logic function unit correspondence is set to represent the numerical value that not can read, otherwise, keep the value of register flag bit constant.
Described coded system is an adaptive arithmetic code, and described logic function unit comprises: receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, binarization lookup unit, probabilistic model query unit, probability space updating block, normalized generate code stream unit, code stream concatenation unit;
Perhaps, described coded system is variable-length encoding, and described logic function unit comprises: receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, the inquiry of elongated table generate code stream unit, code stream concatenation unit;
Perhaps, described coded system is the Ge Lumu coding, and described logic function unit comprises: receiving data units, Ge Lumubiao query unit, code stream concatenation unit;
Perhaps, described coded system is a block code, and described logic function unit comprises: receiving data units, fixed length table query unit, code stream concatenation unit.
According to another above-mentioned main purpose, the invention provides a kind of entropy coding circuit, order comprises following logic function unit: receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, binarization lookup unit, probabilistic model query unit, probability space updating block, normalized generate code stream unit, code stream concatenation unit;
Each logic function unit has produced when having finished as the logical process process of the result of the pending data of a back logic function unit that is adjacent and the back logic function unit that is adjacent at it, its result that obtains is exported to a back logic function unit that is adjacent;
Wherein, the input that the previous logic function unit adjacent with described receiving data units is external circuit, a back logic function unit adjacent with described code stream concatenation unit is the output to external circuit.
Further at the output of each logic function unit register 1～register 8 is set respectively, respectively the described result that produces of the corresponding logic function unit of storage;
Register 1～the register 8 of the corresponding Different Logic functional unit of difference, also the input of adjacent with a corresponding logic function unit respectively back logic function unit links to each other;
Described register 1～register 8 comprises flag bit 1～flag bit 8 respectively, represents respectively whether register 1～register 8 can read;
Each logic function unit further when its corresponding logic processing process has been finished, produces the completed control signal of presentation logic processing procedure respectively;
The logic function unit that output links to each other with register i, when numerical value, this logic function unit that can read for expression at the flag bit of register i-1 produced logic function unit that described result and output link to each other with register i+1 and produced described control signal, the flag bit of register i is set to represent the numerical value that can read, and stores described result; Wherein, i is more than or equal to 1 and smaller or equal to 8 positive integer.
Further the output at receiving data units is provided with a register 1 ', and register 1 ' links to each other with the input of binarization look-up table unit, has a described flag bit;
If it is non-residual error SE that the data of pre-treatment are worked as in binarization look-up table unit, determine that then the previous logic function unit that is adjacent is a receiving data units; If it is residual error SE that the data of pre-treatment are worked as in binarization look-up table unit, determine that then the previous logic function unit that is adjacent is a data analysis unit;
Receiving data units stores residual error SE in the register 1 into according to the SE type that receives, and non-residual error SE is stored in the register 1 '; If the data that received are residual error SE, determine that then a back logic function unit that is adjacent is the signed magnitude arithmetic(al) unit; If the data that received are non-residual error SE, determine that then a back logic function unit that is adjacent is binarization look-up table unit.
The logic function unit that output links to each other with register i, do not produce described result but logic function unit that output links to each other with register i+1 when having produced described control signal at it, further the flag bit of register i is set to represent the numerical value that not can read, otherwise the value of the flag bit of maintenance register i is constant.
This circuit further comprises multilist look-up table unit between receiving data units and code stream concatenation unit, be used to carry out fixed length look-up table and Ge Lumu look-up table;
The output of multilist look-up table unit connects a register, and this register has a described flag bit.
Described multilist look-up table unit is further used for carrying out elongated look-up table.
Another main purpose according to above-mentioned the invention provides another kind of entropy coding circuit, and order comprises following logic function unit: receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, elongated look-up table unit, code stream concatenation unit;
It is characterized in that,
Each logic function unit has produced result and the logical process process of the back logic function unit that is adjacent when having finished at it, its result that obtains is exported to a back logic function unit that is adjacent;
Wherein, the input that the previous logic function unit adjacent with described receiving data units is external circuit, a back logic function unit adjacent with described code stream concatenation unit is the output to external circuit.
Further at the output of each logic function unit register 1～register 5 is set respectively, respectively the described result that produces of the corresponding logic function unit of storage;
Register 1～the register 5 of the corresponding Different Logic functional unit of difference, also the input of adjacent with a corresponding logic function unit respectively back logic function unit links to each other;
Described register 1～register 5 comprises flag bit 1～flag bit 5 respectively, represents respectively whether register 1～register 5 can read;
Each logic function unit further when its corresponding logic processing process has been finished, produces the completed control signal of presentation logic processing procedure respectively;
The logic function unit that output links to each other with register j, when numerical value, this logic function unit that can read for expression at the flag bit of register j-1 produced logic function unit that described result and output link to each other with register j+1 and produced described control signal, the flag bit of register j is set to represent the numerical value that can read, and stores described result; Wherein, j is more than or equal to 1 and smaller or equal to 5 positive integer.
The logic function unit that output links to each other with register j, do not produce described result but logic function unit that output links to each other with register j+1 when having produced described control signal at it, further the flag bit of register i is set to represent the numerical value that not can read, otherwise the value of the flag bit of maintenance register j is constant.
This circuit further comprises fixed length look-up table unit between receiving data units and code stream concatenation unit, be used to carry out the fixed length look-up table; Ge Lumubiao look-up table unit is used to carry out the Ge Lumu look-up table;
Fixed length look-up table unit is connected a register with the output of Ge Lumubiao look-up table unit, and this register is the register that links to each other with the output of elongated look-up table unit.
As seen from the above technical solution, it is that logical process process in the pending data of the back logic function unit that is adjacent and the back logic function unit that is adjacent is when having finished that the present invention has produced result, this result in each logic function unit, the result that this logic function unit is produced offers a back logic function unit that is adjacent, thereby when having realized pipeline system, avoided streamline to stop up and the entropy coding erroneous results, entropy coding than existing serial mode is handled, and has improved treatment effeciency.
The present invention can be used to represent whether this logic function unit finishes its corresponding logic processing process by for each logic function unit is provided with a control signal; Simultaneously, for each logic function unit is provided with a register, be used to store the result of the pending data of next logic function unit that conduct that this logic function unit generates is adjacent, and have a flag bit in this register, be used for representing that whether the next logic function unit that is adjacent can read result as its pending data from this register.Like this, need not increases other hardware in circuit, get final product simple realization technical scheme of the present invention, thereby makes that technical scheme of the present invention is easy to realize, and cost is lower.
The present invention is also with the identity logic processing procedure in the multiple coded system in the entropy coding, and is multiplexing in identical hardware resource, thereby saved hardware resource.
Description of drawings
Fig. 1 is the schematic diagram of block code process in the prior art.
Fig. 2 is the schematic diagram of Ge Lumu cataloged procedure in the prior art.
Fig. 3 is the elongated schematic diagram that becomes the sign indicating number process in the prior art.
Fig. 4 is the schematic diagram of adaptive arithmetic code process in the prior art.
Fig. 5 is the flow chart of entropy coding control method in the embodiment of the invention.
Fig. 6 is the schematic diagram of adaptive arithmetic code circuit in the embodiment of the invention.
Fig. 7 is the schematic diagram for adaptive variable length coding circuit in the inventive embodiments.
Fig. 8 is for comprising the entropy coding circuit schematic diagram of 4 kinds of coding circuits in the embodiment of the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
In the embodiment of the invention, in the existing entropy coding as Fig. 1～4 kinds of coded systems shown in Figure 4, all adopt pipeline system to substitute serial mode, thereby can improve entropy-coding efficiency.And, for the identity logic processing procedure that exists between the different coded systems, realize by multiplexing identical hardware resource, thereby can improve hardware resource utilization.
Below, earlier the entropy coding control method based on pipeline system in the embodiment of the invention is elaborated.
For in the existing entropy coding as Fig. 1～4 kinds of coded systems shown in Figure 4, can be respectively wherein a plurality of logical process processes be divided into a plurality of pipeline stages, thus the cataloged procedure of realization pipeline system.
But,, all may have the shared mutually different problem of unit time quantity of Different Logic processing procedure for above-mentioned 4 kinds of coded systems.Therefore, if simply that each logical process process is shared unit time quantity is as the transmission cycle of this pipeline stages, promptly with concluding time deadline of each logical process process as the cycle of transmission, then can cause the transmission in the streamline to block owing to transmission cycle of each pipeline stages is different, thereby can't realize the normal delivery of streamline between at different levels.
Yet, if according to existing mode, in all pipeline stages corresponding logic processing processes, the longest required processing cycle of a logical process process consuming time is as the unified transmission cycle, then can make the pairing pipeline stages of other logical process carry out unnecessary wait, thereby make that the transmission cycle of streamline is longer, reduce the efficient of streamline, and, can make that also mistake appears in the entropy coding result.
With as shown in Figure 4 adaptive arithmetic code is example, and its data analysis logical process process is consuming time the longest, takies 16 unit times usually, and other logical process processes generally all only need take 1～2 unit time.Therefore, if the transmission cycle between each pipeline stages be set to 16 unit times, thereby make the pairing pipeline stages of other logical process processes wait for a large amount of unit time.
And data analysis logical process process each unit time before it finishes final processing all may produce a result, as the pending data of the binarization look-up table logical process of its next stage.That is to say, if the concluding time of data analysis logical process process is as the concluding time in the cycle of transmission, though can guarantee the synchronous of each pipeline stages corresponding logic processing process, but for binarization look-up table process, be merely able to realize 1 binarization look-up table, thereby make that final entropy coding result is incorrect in 16 pending data.
And, for different SE, the shared unit interval quantity of each logical process process also may be different, for example, the logical process process that generates code stream for the normalized of current SE may take 6 unit times, and may only need 4 unit times for the logical process process that the normalized of next SE generates code stream, therefore, if the length that the transmission cycle is set to fix also can cause waiting as long for of part pipeline stages, caused the waste of time and hardware resource.
Therefore, in the embodiment of the invention, realize that the transmission between the pipeline stages should be satisfied following condition:
Logic function unit for each logical process process of realization, if it is that logical process process in the pending data of the back logic function unit that is adjacent and the back logic function unit that is adjacent is finished that this logic function unit has produced result, this result, then the result that this logic function unit is produced offers a back logic function unit that is adjacent.
If regard each logical process process or logic function unit as a pipeline stages, previous logic function unit that will be adjacent with each logic function unit is regarded its upper level pipeline stages as, back logic function unit that will be adjacent with each logic function unit is regarded its next stage pipeline stages as, then for each level production line level, if this pipeline stages has produced the result as the pending data of next stage, and the pairing logical process process of the next stage of this pipeline stages is finished, and then this pipeline stages passes to its next stage with the result that obtains.
It should be explicitly made clear at this point that in the entropy coding process, when each logical process process had produced as the result of the pending data of next stage, this logical process process might not be finished.
Be example still with as shown in Figure 4 adaptive arithmetic code, suppose that current SE is one 4 * 4 a chrominance matrix, then for the pipeline stages of data analysis logical process process correspondence, its absolute calculation logical process process is calculated the absolute value of 16 elements in the matrix that once receives one by one, obtains the absolute value of 16 elements through 16 unit Time Calculation; The data analysis logical process process of this pipeline stages correspondence, one by one 16 element absolute values in the matrix that once receives are carried out data analysis, obtain 16 data analysis results continuously through 16 unit times as the pending data of binarization look-up table process; Its next stage binarization look-up table logical process process, per 1 unit time can be finished the binary lookup table 1 time.
Therefore, data analysis result of the every generation of pipeline stages when data analysis logical process process correspondence, absolute calculation logical process process also produces an absolute value simultaneously, and binarization look-up table logical process process is finished, then the data analysis result who obtains is passed to the pairing pipeline stages of binarization look-up table logical process process; If absolute calculation logical process process has produced 16 absolute values, absolute calculation logical process process one-level is from it obtained next SE, and data analysis logical process process is finished, and the pipeline stages of then data analysis logical process process correspondence can obtain the result that the pipeline stages transmission of absolute calculation logical process process correspondence is got off.
As seen, if current SE is one 4 * 4 a chrominance matrix, absolute calculation logical process process is distinguished between the corresponding two-stage pipeline stages with data analysis logical process process, the transmission cycle is 16 unit times, and data analysis logical process process is distinguished between the corresponding two-stage pipeline stages with binarization look-up table logical process process, and the transmission cycle is 1 unit time.
Like this,, the normal operation of entropy coding process can be guaranteed, the entropy coding erroneous results can be do not occurred though the transmission cycle between the different two-stage pipeline stages can be different.And for different SE, the transmission cycle between the pipeline stages can dynamic change.
Based on above-mentioned principle, the embodiment of the invention is provided with a control signal for each level production line level, is used to represent whether this pipeline stages finishes its corresponding logic processing process; Simultaneously, for each level production line level is provided with a register, be used to store the result that this pipeline stages generates as the pending data of next stage, and have a flag bit in this register, be used for representing that whether the next stage pipeline stages can read result as its pending data from this register.
Below, above-mentioned control signal and register are illustrated.
During the control signal DONEi=1 of i level production line level correspondence, represent that i level production line level corresponding logic processing process finished; During DONEi=0, represent that i level production line level corresponding logic processing process do not finish, i is greater than 0 and less than the positive integer of pipeline stages sum.
During the flag bit VALIDi=1 of the register i of i level production line level correspondence, expression can be read the result as its pending data from register i, the i.e. numerical value that can read of 1 bit representation, i+1 level production line level can be carried out the transmission between i level production line level and the i+1 level production line level; During VALIDi=0, represent that i+1 level production line level can not read the result as its pending data from register i, the i.e. numerical value that not can read of 0 bit representation, i+1 level production line level can not be carried out the transmission between i level production line level and the i+1 level production line level.
According to the condition that the transmission between the above-mentioned pipeline stages should be satisfied, the assignment procedure of VALIDi can for:
Produce pending data, DONE (i+1)=1 and VALID (i-1)=1 o'clock of its next stage in i level production line level, made VALIDi=1;
Do not produce the pending data of its next stage and at DONE (i+1)=1 o'clock in i level production line level, make VALIDi=0;
All the other situations keep the current value of VALIDi constant.
Like this, i+1 level production line level can be when VALIDi=1, obtain pending data from i level production line level, thereby realized that all pipeline stages realize transmission each other simultaneously, the processing speed of pipeline stages that guarantees every two-stage neighboring is identical, can guarantee that stopping up does not appear in streamline.
And control signal produces in real time according to current disposition, thereby makes that the length in transmission cycle is dynamic change along with the difference of actual conditions, thereby can avoid the waste of time and hardware resource to greatest extent.
Below, the entropy coding control method in the embodiment of the invention is elaborated.
Fig. 5 is the flow chart of entropy coding control method in the embodiment of the invention.As shown in Figure 5, the entropy coding control method in the present embodiment may further comprise the steps:
Step 501, a plurality of logical process processes in the coded system are divided into a plurality of pipeline stages, and a register is set for each level production line level, be used to store the result that the pairing logical process process of corresponding pipeline stages produces, this register comprises a flag bit, is used for representing that whether the next stage pipeline stages can read result as its pending data from this register.
Wherein, be divided into pipeline stages and be the logic function unit of determining to realize the Different Logic processing procedure.
In this step, if in adaptive arithmetic code mode as shown in Figure 4 is example, then the pipeline stages of Hua Fening can be 8 grades at most, respectively corresponding following logical process process: reception data, signed magnitude arithmetic(al), data analysis, binarization are tabled look-up, probabilistic model is inquired about, probability space upgrades, normalized generates code stream, the code stream splicing.
In like manner, if be example in as shown in Figure 3 variable-length encoding mode in this step, then the pipeline stages of Hua Fening can be 5 grades at most, respectively corresponding following logical process process: receive data, signed magnitude arithmetic(al), data analysis, elongated table inquiry generation code stream, code stream splicing; Ge Lumu coded system as shown in Figure 2 is an example, and then the pipeline stages of Hua Fening can be 3 grades at most, respectively corresponding following logical process process: receive data, Ge Lumubiao inquiry generation code stream, code stream splicing; Block code mode as shown in Figure 1 is an example, and then the pipeline stages of Hua Fening can be 3 grades at most, respectively corresponding following logical process process: receive data, fixed length table inquiry generation code stream, code stream splicing.
In this step, if this pipeline stages does not produce the result as the pending data of next stage, but its next stage pipeline stages has produced a completed control signal of presentation logic processing procedure, then the register flag bit of this pipeline stages correspondence is set to represent the numerical value that not can read, otherwise, keep the value of register flag bit constant.
After this step, each level production line level thereon the one-level register flag bit for the expression can read numerical value the time, promptly can read the result of storing in this register, begin pairing logical process process of next transmission cycle.
So far, this flow process finishes.
Step 502～step 503 in the above-mentioned flow process is a process that can repeatedly circulate and carry out.In this process, when each level production line level all can produce at the upper level that this pipeline stages has produced result as the pending data of next stage, this pipeline stages and finish as the pairing logical process process of next stage of the result of the pending data of this pipeline stages and this pipeline stages, realize and its next stage pipeline stages between transmission; The upper level that each level production line level all can produce result as the pending data of this pipeline stages, this pipeline stages at the upper level of this pipeline stages is when one-level obtains pending data and the pairing logical process process of this pipeline stages and finished from it, realize and its upper level pipeline stages between transmission.Thereby under the prerequisite that streamline obstruction and entropy coding erroneous results do not occur, realized that the entropy coding of pipeline system is handled.Entropy coding than existing serial mode is handled, and has improved treatment effeciency.
In the practical application, shared unit time of adaptive arithmetic code mode as shown in Figure 4 is maximum, therefore, if above-mentioned control method is applied in this circuit, then can improve the efficient of entropy coding greatly.
Fig. 6 is the schematic diagram of adaptive arithmetic code circuit in the embodiment of the invention.As shown in Figure 6, adaptive arithmetic code circuit in the present embodiment is according to the logical process process in the adaptive arithmetic code mode, be divided into following logical block: receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, binarization lookup unit, probabilistic model query unit, probability space updating block, normalized generate code stream unit, code stream concatenation unit, the corresponding pipeline stages 1～8 of difference, and the logical block of each pipeline stages correspondence takies independent hardware resource.
In the adaptive arithmetic code mode as shown in Figure 4, same hardware resource is used in signed magnitude arithmetic(al) and data analysis, but in order to shorten the transmission cycle of streamline generally, the two is divided into 2 pipeline stages, and utilizes different hardware resources to realize.
In the foregoing circuit, output at difference receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, binarization lookup unit, probabilistic model query unit, probability space updating block, normalized generation code stream unit, code stream concatenation unit is provided with register 1～register 8; And register 1～register 8, the input with signed magnitude arithmetic(al) unit, data analysis unit, binarization lookup unit, probabilistic model query unit, probability space updating block, normalized generation code stream unit, code stream concatenation unit and external circuit links to each other respectively.
Register 1～register 8 has a flag bit VALID1～VALID8 respectively, and its value represents respectively whether register 1～register 8 can read, and when value was 1, expression can read, and when value was 0, expression not can read.
The receiving data units of the 1st level production line level correspondence receives the SE that external circuit is imported;
If received the existing SE to be imported of SE, external circuit of external circuit input and received control signal DONE2=1, then made VALID1=1, and the SE that receives is stored in the register 1; Wherein, external circuit has SE to be imported, and promptly is equal to the numerical value 1 of register flag bit for representing can read of upper level;
If finished the reception to the SE of input, external circuit has SE to be imported and receives control signal DONE2=1, then exports control signal DONE1=1, receives the SE of external circuit input once more;
If do not receive the SE of external circuit input and receive control signal DONE2=1, then make VALID1=0;
Otherwise, continue to receive the SE of input, and keep the current numerical value of VALID1 constant from external circuit.
The signed magnitude arithmetic(al) unit of the 2nd level production line level correspondence carries out signed magnitude arithmetic(al) to the SE that reads from register 1;
If produced at least one signed magnitude arithmetic(al) result, VALID1=1 and received control signal DONE3=1, then make VALID2=1, and one or more signed magnitude arithmetic(al) results that will produce store in the register 2 into;
If finished signed magnitude arithmetic(al), VALID1=1 and received control signal DONE3=1, then exported control signal DONE2=1, and from register 1, read SE once more;
If do not produce the signed magnitude arithmetic(al) result and receive control signal DONE3=1, then make VALID2=0;
Otherwise, proceed signed magnitude arithmetic(al), and keep the current numerical value of VALID2 constant.
The data analysis unit of 3rd level pipeline stages correspondence is carried out data analysis to the signed magnitude arithmetic(al) result who reads from register 2;
If produced at least one data analysis result, VALID2=1 and received control signal DONE4=1, then make VALID3=1, and one or more data analysis results that will produce store in the register 3 into;
If finished data analysis, VALID2=1 and received control signal DONE4=1, then export control signal DONE3=1, and from register 2, read the signed magnitude arithmetic(al) result once more;
If do not produce the data analysis result and receive control signal DONE4=1, then make VALID3=0;
Otherwise, proceed data analysis, and keep the current numerical value of VALID3 constant.
The binarization look-up table unit of the 4th level production line level correspondence carries out the binarization look-up table to the data analysis result who reads from register 3;
If produced look-up table result, VALID3=1 and received control signal DONE5=1, then make VALID4=, and store in the register 4 the look-up table result who produces into 1;
If finished binarization look-up table, VALID3=1 and received control signal DONE5=1, then export control signal DONE4=1, and reading of data analysis result from register 3 once more;
If do not produce the look-up table result and receive control signal DONE5=1, then make VALID4=0;
Otherwise, proceed the binarization look-up table, and keep the current numerical value of VALID4 constant.
The probabilistic model query unit of the 5th level production line level correspondence is carried out the probabilistic model inquiry according to the look-up table result who reads from register 4;
If produced Query Result, VALID4=1 and received control signal DONE6=1, then make VALID5=1, and the Query Result that produces is stored in the register 5;
If finished probabilistic model inquiry, VALID4=1 and received control signal DONE6=1, then export control signal DONE5=1, and from register 4, read the look-up table result once more;
If do not produce Query Result and receive control signal DONE6=1, then make VALID5=0;
Otherwise, proceed the probabilistic model inquiry, and keep the current numerical value of VALID5 constant.
The probability space updating block of the 6th level production line level correspondence carries out probability space according to the Query Result that reads and upgrades from register 5;
If produced renewal result, VALID5=1 and received control signal DONE7=1, then make VALID6=1, and the renewal result that will produce stores in the register 6 into;
If finished probability space renewal, VALID5=1 and received control signal DONE7=1, then exported control signal DONE6=1, and from register 5, read Query Result once more;
Do not upgrade the result and receive control signal DONE7=1 if produce, then make VALID6=0;
Otherwise, proceed probability space and upgrade, and keep the current numerical value of VALID6 constant.
The normalized of the 7th level production line level correspondence generates the code stream unit, carries out normalized according to the renewal result who reads from register 6;
If produced code stream, VALID6=1 and received control signal DONE8=1, then make VALID7=1, and the code stream that produces is stored in the register 7;
If finished normalized, VALID6=1 and received control signal DONE8=1, then export control signal DONE7=1, and from register 6, read the renewal result once more;
If do not produce code stream and receive control signal DONE8=1, then make VALID7=0;
Otherwise, proceed normalized, and keep the current numerical value of VALID7 constant.
The code stream concatenation unit of the 8th level production line level correspondence carries out the code stream splicing to the code stream that reads from register 7;
Wait for that it exports spliced code stream if obtained spliced code stream, VALID7=1 and external circuit, then make VALID8=1, and spliced code stream is stored in the register 8; Wherein, external circuit waits for that it exports spliced code stream, promptly is equal to its next stage and has finished the corresponding logic processing process;
Wait for that it exports spliced code stream if finished splicing, VALID7=1 and the external circuit of code stream, then export control signal DONE8=1, and from register 7, read code stream once more;
Do not wait for that it exports spliced code stream if carry out code stream splicing and external circuit, then make VALID8=0;
Otherwise, proceed the code stream splicing, and keep the current numerical value of VALID8 constant.
In the practical application,, also non-residual error SE is carried out encoding process, and, do not need to carry out signed magnitude arithmetic(al) and data analysis for non-residual error SE because the adaptive arithmetic code circuit both carried out encoding process to residual error SE.Therefore, a register 1 ' can further be set at the output of receiving data units, register 1 ' also links to each other with the input of binarization look-up table unit, has a flag bit VALID1 '.
Like this, the binarization look-up table unit of the 4th level production line level correspondence further carries out the binarization look-up table to the non-residual error SE that reads from register 1 ', and the look-up table result who produces is stored in the register 4; If produced look-up table result, VALID1 '=1 and received control signal DONE5=1, then made VALID4=1; If finished binarization look-up table, VALID1 '=1 and received control signal DONE5=1, then export control signal DONE4=1, and reading of data analysis result from register 1 ' once more; If do not produce the look-up table result and receive control signal DONE5=1, then make VALID4=0; Otherwise, proceed the binarization look-up table, and keep the current numerical value of VALID4 constant.
Need to prove that binarization look-up table unit is not to obtain the result of storage from register 1 ' and register 3 simultaneously.Owing among the SE of input, sign of its order of sign is arranged all, thereby binarization look-up table unit indicates according to this, judgement should be earlier from register 1 ' still register 3 obtain the result of storage.That is to say, if the non-residual error SE of storage should come before the pairing residual error SE of data analysis result of storage in the register 3 in the register 1 ', then binarization look-up table unit obtains the result of storage from register 1 ', otherwise, obtain the result of storage from register 3.
If binarization look-up table unit when the data of pre-treatment be non-residual error SE, corresponding receiving data units of its corresponding upper level pipeline stages then; If it is residual error SE that the data of pre-treatment are worked as in binarization look-up table unit, then its corresponding upper level pipeline stages corresponding data analytic unit.
Receiving data units can store residual error SE in the register 1 into according to the SE type that receives, and non-residual error SE is stored in the register 1 '; If the data that received are residual error SE, the corresponding signed magnitude arithmetic(al) of its corresponding next stage pipeline stages unit then; If the data that received are non-residual error SE, the corresponding binarization look-up table of its corresponding next stage pipeline stages unit then.
As seen, above-mentioned adaptive arithmetic code circuit has been realized the processing of pipeline system, thereby under the prerequisite that streamline obstruction and coding result mistake do not occur, has improved its treatment effeciency, and then improved the treatment effeciency of entropy coding.
In like manner, block code circuit, Ge Lumu coding circuit and adaptive variable length coding circuit also all can be realized pipeline processes in the manner described above.
Fig. 7 is the schematic diagram for adaptive variable length coding circuit in the inventive embodiments.Becoming decoding circuit with adaptive variable length is example, as shown in Figure 7, the block code circuit is divided into 5 pipeline stages, respectively corresponding following logic function unit: receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, elongated look-up table unit, code stream concatenation unit.
Output in each logic function unit is provided with register 1～register 5 respectively, stores the described result that the pairing logic function unit of corresponding pipeline stages produces respectively;
Register 1～register 5 links to each other with the input of the logic function unit of the coupled pairing next stage pipeline stages of logic function unit of output respectively;
Register 1～register 5 comprises flag bit 1～flag bit 5 respectively, represents respectively whether register 1～register 5 can read;
When each logic function unit has been finished in its corresponding logic processing process, export the completed control signal of presentation logic processing procedure respectively, DONEj=1, j are more than or equal to 1 and smaller or equal to 5 positive integer;
With the corresponding logic function unit of j level production line level, when numerical value, this logic function unit that can read for expression at the flag bit of register j-1 produced result and the logic function unit corresponding with j+1 level production line level and produced the completed control signal DONEj+1=1 of presentation logic processing procedure, the flag bit of register j is set to represent the numerical value that can read, the result that storage produces, and read described result from register j-1 once more.
With the corresponding logic function unit of j level production line level, do not produce described result but the logic function unit of j+1 level production line level correspondence when having produced the completed control signal DONEj+1=1 of presentation logic processing procedure at it, the flag bit of register j is set to represent the numerical value that not can read, otherwise the value of the flag bit of maintenance register j is constant.
Identical with the adaptive arithmetic code circuit, the upper level pipeline stages of receiving data units correspondence is the input of external circuit, and the next stage pipeline stages of code stream concatenation unit correspondence is the output to external circuit.
Like this, each circuit that comprises in the entropy coding circuit all can be realized streamline control, if one of them circuit or all circuit have all been realized streamline control, can improve the efficient of entropy coding.
As previously mentioned, between the coded system as Fig. 1～shown in Figure 4, there is the identical logical process process of part.Therefore, in the embodiment of the invention, the identical logical process that the different coding circuit is required, multiplexing on identical hardware resource.
Entropy coding circuit in the present embodiment can comprise adaptive arithmetic code circuit as shown in Figure 6, and on this basis, further comprise the multilist look-up table unit that is used for block code and Ge Lumu coding, and required receiving data units and the code stream concatenation unit of block code and Ge Lumu coding, receiving data units and code stream concatenation unit in can multiplexing adaptive arithmetic code circuit.
Wherein, comprise fixed length look-up table unit and Ge Lumubiao look-up table unit in the multilist look-up table unit.
Like this, output at receiving data units, a register 1 further is set "; this register 1 " link to each other with the input of multilist look-up table unit, can simultaneously link to each other register 1 with the output of fixed length look-up table unit with Ge Lumubiao look-up table unit " have a flag bit VALID1 "; Output in multilist look-up table unit is provided with a register a, and register a links to each other with the input of code stream concatenation unit, and has a flag bit a.
Be the corresponding receiving data units of upper level pipeline stages of multilist look-up table unit correspondence, the corresponding code stream concatenation unit of its next stage pipeline stages.
Like this, multilist look-up table unit is to from register 1 " the non-residual error SE that reads carry out fixed length table or Ge Lumubiao look-up table, and the look-up table result who produces is stored among the register a; If produced look-up table result, VALID1 "=1 and receive control signal DONE8=1, VALIDa=1 then made; If finished look-up table, VALID1 "=1 and receive control signal DONE8=1, then export control signal DONEa=1, and once more from register 1 " the reading of data analysis result; If do not produce the look-up table result and receive control signal DONE8=1, then make VALIDa=0; Otherwise, proceed the binarization look-up table, and keep the current numerical value of VALIDa constant.
Owing among the SE of input, the sign of its order of sign is all arranged, thereby the code stream concatenation unit can indicate that judgement should still be the result that register a obtains storage from register 7 earlier according to this.That is to say, if the pairing residual error SE of code stream of storage should come before the pairing non-residual error SE of the code stream of storing among the register a in the register 7, then the code stream concatenation unit obtains the result of storage from register 7, otherwise, obtain the result of storage from register a.
As seen, because the block code in the entropy coding, Ge Lumu coding, adaptive arithmetic code not necessarily carry out simultaneously, thereby the hardware resource of multiplexing realization identity logic processing procedure can not produce the conflict between each cataloged procedure, and can save the hardware resource in the entropy coding circuit.
In like manner, also block code, Ge Lumu coding and adaptive variable length can be become in the sign indicating number, realize that the hardware resource of identity logic processing procedure is multiplexing.
Like this, entropy coding circuit in the present embodiment can comprise adaptive variable length coding circuit as shown in Figure 7, and on this basis, further comprise the multilist look-up table unit that is used for block code and Ge Lumu coding, and required receiving data units and the code stream concatenation unit of block code and Ge Lumu coding, receiving data units and code stream concatenation unit in can multiplexing adaptive variable length coding circuit.The output of receiving data units also connects two registers, links to each other with the input of signed magnitude arithmetic(al) unit with multilist look-up table unit respectively, and is identical with the implementation of above-mentioned entropy coding circuit, do not repeat them here.
Consider the versatility of entropy coding circuit, entropy coding circuit in the present embodiment comprises adaptive arithmetic code circuit, adaptive variable length coding circuit as shown in Figure 7 and block code and Ge Lumu coding circuit as shown in Figure 6, promptly can be in actual applications, select arbitrarily a kind of in adaptive arithmetic code circuit and the adaptive variable length coding circuit, realize coding to residual error SE, and in above-mentioned 4 coding circuits, realize that the hardware resource of identity logic processing procedure is multiplexing.
Fig. 8 is for comprising the entropy coding circuit schematic diagram of 4 kinds of coding circuits in the embodiment of the invention.As shown in Figure 8, on the basis of as shown in Figure 6 adaptive arithmetic code circuit, further comprise: the multilist look-up table unit that is used for block code, Ge Lumu coding and adaptive variable length coding, and block code, Ge Lumu coding and required receiving data units and the code stream concatenation unit of adaptive variable length coding, receiving data units and code stream concatenation unit in can multiplexing adaptive variable length coding circuit; Signed magnitude arithmetic(al) unit and data analysis unit that adaptive variable length coding is required, signed magnitude arithmetic(al) unit and data analysis unit in can multiplexing adaptive variable length coding circuit.
Wherein, comprise fixed length look-up table unit, Ge Lumubiao look-up table unit and elongated look-up table unit in the multilist look-up table unit, three's output can connect a register simultaneously.
Wherein, the register of each logic function unit correspondence is not shown in the drawings.
Owing in the practical application, can not use adaptive variable length coding and adaptive arithmetic code usually simultaneously, therefore, the pairing register 3 of data analysis unit can link to each other with the input of binarization look-up table unit with multilist look-up table unit simultaneously.
Like this, in the process of entropy coding, therefore the each several part combinational logic can dwindle total processing time greatly according to the pipeline system parallel processing.For high definition 1920 * 1080 videos, the macro block that average treatment is one 16 * 16 needs 300～400 clock cycle, therefore, guaranteeing that circuit operates under the clock frequency of 200Mhz, can handle 200M/ (400 * 1920 * 1080 * 1.5/ (16 * 16))=41 hardwood/seconds by per second, satisfy the requirement of real-time coding.Simultaneously, also reduced the shared hardware resource of entropy coding circuit, further provided cost savings.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (14)
1, a kind of entropy coding control method, each logic function unit is carried out corresponding logical process process, it is characterized in that, comprising:
Each logic function unit, produced result and the logical process process of the back logic function unit that is adjacent when having finished at it, the described result that this logic function unit is obtained offers a back logic function unit that is adjacent.
2, the method for claim 1 is characterized in that, further for each logic function unit is provided with a register, stores the described result that this logic function unit produces;
Described register comprises a flag bit, is used for representing whether a back logic function unit adjacent with this logic function unit can read described result from this register;
Each logic function unit further when its corresponding logic processing process has been finished, produces the completed control signal of presentation logic processing procedure;
The described result that this logic function unit is obtained offers a back logic function unit that is adjacent:
When numerical value, this logic function unit that each logic function unit can read for expression at the register flag bit of the previous logic function unit that is adjacent produced described result and a back logic function unit adjacent with this logic function unit and produced described control signal, this logic function unit is stored described result, and its corresponding register flag bit is set to represent the numerical value that can read, and a back logic function unit that allows to be adjacent reads described result from the register of this logic function unit correspondence.
3, method as claimed in claim 2, it is characterized in that, each logic function unit does not produce described result at it, but when a back logic function unit that is adjacent has produced described control signal, then the register flag bit of this logic function unit correspondence is set to represent the numerical value that not can read, otherwise, keep the value of register flag bit constant.
4, as any described method in the claim 1 to 3, it is characterized in that, described coded system is an adaptive arithmetic code, and described logic function unit comprises: receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, binarization lookup unit, probabilistic model query unit, probability space updating block, normalized generate code stream unit, code stream concatenation unit;
Perhaps, described coded system is variable-length encoding, and described logic function unit comprises: receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, the inquiry of elongated table generate code stream unit, code stream concatenation unit;
Perhaps, described coded system is the Ge Lumu coding, and described logic function unit comprises: receiving data units, Ge Lumubiao query unit, code stream concatenation unit;
Perhaps, described coded system is a block code, and described logic function unit comprises: receiving data units, fixed length table query unit, code stream concatenation unit.
5, a kind of entropy coding circuit, order comprises following logic function unit: receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, binarization lookup unit, probabilistic model query unit, probability space updating block, normalized generate code stream unit, code stream concatenation unit;
It is characterized in that,
Each logic function unit has produced when having finished as the logical process process of the result of the pending data of a back logic function unit that is adjacent and the back logic function unit that is adjacent at it, its result that obtains is exported to a back logic function unit that is adjacent;
Wherein, the input that the previous logic function unit adjacent with described receiving data units is external circuit, a back logic function unit adjacent with described code stream concatenation unit is the output to external circuit.
6, circuit as claimed in claim 5 is characterized in that, further at the output of each logic function unit register 1～register 8 is set respectively, respectively the described result that produces of the corresponding logic function unit of storage;
Register 1～the register 8 of the corresponding Different Logic functional unit of difference, also the input of adjacent with a corresponding logic function unit respectively back logic function unit links to each other;
Described register 1～register 8 comprises flag bit 1～flag bit 8 respectively, represents respectively whether register 1～register 8 can read;
Each logic function unit further when its corresponding logic processing process has been finished, produces the completed control signal of presentation logic processing procedure respectively;
The logic function unit that output links to each other with register i, when numerical value, this logic function unit that can read for expression at the flag bit of register i-1 produced logic function unit that described result and output link to each other with register i+1 and produced described control signal, the flag bit of register i is set to represent the numerical value that can read, and stores described result; Wherein, i is more than or equal to 1 and smaller or equal to 8 positive integer.
7, circuit as claimed in claim 6 is characterized in that,
Further the output at receiving data units is provided with a register 1 ', and register 1 ' links to each other with the input of binarization look-up table unit, has a described flag bit;
If it is non-residual error SE that the data of pre-treatment are worked as in binarization look-up table unit, determine that then the previous logic function unit that is adjacent is a receiving data units; If it is residual error SE that the data of pre-treatment are worked as in binarization look-up table unit, determine that then the previous logic function unit that is adjacent is a data analysis unit;
Receiving data units stores residual error SE in the register 1 into according to the SE type that receives, and non-residual error SE is stored in the register 1 '; If the data that received are residual error SE, determine that then a back logic function unit that is adjacent is the signed magnitude arithmetic(al) unit; If the data that received are non-residual error SE, determine that then a back logic function unit that is adjacent is binarization look-up table unit.
8, as claim 6 or 7 described circuit, it is characterized in that,
The logic function unit that output links to each other with register i, do not produce described result but logic function unit that output links to each other with register i+1 when having produced described control signal at it, further the flag bit of register i is set to represent the numerical value that not can read, otherwise the value of the flag bit of maintenance register i is constant.
As claim 6 or 7 described circuit, it is characterized in that 9, this circuit further comprises multilist look-up table unit between receiving data units and code stream concatenation unit, be used to carry out fixed length look-up table and Ge Lumu look-up table;
The output of multilist look-up table unit connects a register, and this register has a described flag bit.
10, circuit as claimed in claim 9 is characterized in that, described multilist look-up table unit is further used for carrying out elongated look-up table.
11, a kind of entropy coding circuit, order comprises following logic function unit: receiving data units, signed magnitude arithmetic(al) unit, data analysis unit, elongated look-up table unit, code stream concatenation unit;
It is characterized in that,
Each logic function unit has produced result and the logical process process of the back logic function unit that is adjacent when having finished at it, its result that obtains is exported to a back logic function unit that is adjacent;
Wherein, the input that the previous logic function unit adjacent with described receiving data units is external circuit, a back logic function unit adjacent with described code stream concatenation unit is the output to external circuit.
12, circuit as claimed in claim 11 is characterized in that, further at the output of each logic function unit register 1～register 5 is set respectively, respectively the described result that produces of the corresponding logic function unit of storage;
Register 1～the register 5 of the corresponding Different Logic functional unit of difference, also the input of adjacent with a corresponding logic function unit respectively back logic function unit links to each other;
Described register 1～register 5 comprises flag bit 1～flag bit 5 respectively, represents respectively whether register 1～register 5 can read;
Each logic function unit further when its corresponding logic processing process has been finished, produces the completed control signal of presentation logic processing procedure respectively;
The logic function unit that output links to each other with register j, when numerical value, this logic function unit that can read for expression at the flag bit of register j-1 produced logic function unit that described result and output link to each other with register j+1 and produced described control signal, the flag bit of register j is set to represent the numerical value that can read, and stores described result; Wherein, j is more than or equal to 1 and smaller or equal to 5 positive integer.
13, as claim 11 or 12 described circuit, it is characterized in that,
The logic function unit that output links to each other with register j, do not produce described result but logic function unit that output links to each other with register j+1 when having produced described control signal at it, further the flag bit of register j is set to represent the numerical value that not can read, otherwise the value of the flag bit of maintenance register j is constant.
As claim 11 or 12 described circuit, it is characterized in that 14, this circuit further comprises fixed length look-up table unit between receiving data units and code stream concatenation unit, be used to carry out the fixed length look-up table; Ge Lumubiao look-up table unit is used to carry out the Ge Lumu look-up table;
Fixed length look-up table unit is connected a register with the output of Ge Lumubiao look-up table unit, and this register is the register that links to each other with the output of elongated look-up table unit.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102186075A (en) * | 2011-04-28 | 2011-09-14 | 北京大学 | Entropy coder and realization method thereof |
| CN102325253A (en) * | 2011-08-15 | 2012-01-18 | 复旦大学 | A kind of CAVLC encoder of four road parallel encodings |
| CN104081772A (en) * | 2011-10-06 | 2014-10-01 | 弗兰霍菲尔运输应用研究公司 | Entropy coding buffer arrangement |
| CN109379591A (en) * | 2018-10-23 | 2019-02-22 | 深圳市网心科技有限公司 | Picture code-transferring method, electronic device and computer readable storage medium |
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| US6677868B2 (en) * | 2001-03-16 | 2004-01-13 | Sharp Laboratories Of America, Inc. | Entropy coding with adaptive syntax to replace high probability symbols with lower probabilities symbols |
| KR100604986B1 (en) * | 2004-07-26 | 2006-07-28 | 삼성전자주식회사 | Variable length coding method with 4 stage pipeline and variable length coder using the same |
| CN100466742C (en) * | 2006-08-07 | 2009-03-04 | 清华大学 | Combined processing method for entropy decoding and converting flow line stage |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102186075A (en) * | 2011-04-28 | 2011-09-14 | 北京大学 | Entropy coder and realization method thereof |
| CN102325253A (en) * | 2011-08-15 | 2012-01-18 | 复旦大学 | A kind of CAVLC encoder of four road parallel encodings |
| CN102325253B (en) * | 2011-08-15 | 2013-10-16 | 复旦大学 | CAVLC (context-adaptive variable-length coding) coder for four-channel parallel coding |
| CN104081772A (en) * | 2011-10-06 | 2014-10-01 | 弗兰霍菲尔运输应用研究公司 | Entropy coding buffer arrangement |
| CN104081772B (en) * | 2011-10-06 | 2018-04-10 | 弗劳恩霍夫应用研究促进协会 | Entropy code buffer configures |
| CN110971905A (en) * | 2014-03-14 | 2020-04-07 | Vid拓展公司 | System and method for RGB video coding enhancement |
| CN110971905B (en) * | 2014-03-14 | 2023-11-17 | Vid拓展公司 | Method, apparatus and storage medium for encoding and decoding video content |
| CN109379591A (en) * | 2018-10-23 | 2019-02-22 | 深圳市网心科技有限公司 | Picture code-transferring method, electronic device and computer readable storage medium |
| CN109379591B (en) * | 2018-10-23 | 2021-08-06 | 深圳市网心科技有限公司 | Image transcoding method, electronic device and computer readable storage medium |
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