CN104469190A - Stable biasing amplification image processing system - Google Patents
Stable biasing amplification image processing system Download PDFInfo
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- CN104469190A CN104469190A CN201410709020.6A CN201410709020A CN104469190A CN 104469190 A CN104469190 A CN 104469190A CN 201410709020 A CN201410709020 A CN 201410709020A CN 104469190 A CN104469190 A CN 104469190A
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Abstract
The invention discloses a stable biasing amplification image processing system. The stable biasing amplification image processing system mainly comprises an image sensor, an image processing circuit connected with the image sensor, a signal screening circuit connected with the image processing circuit, a time base generating circuit connected with the signal screening circuit and a biasing amplification circuit and is characterized in that a linear drive circuit is further connected between the image processing circuit and the time base generating circuit and consists of a drive chip U, an audion VT4, an audion VT5, an audion VT6, an audion VT7, a polar capacitor C11 and the like, the positive pole of the polar capacitor C11 is connected with the image processing circuit, and the negative pole of the polar capacitor C11 is connected with the pin IN1 of the drive chip U through a resistor R14. The stable biasing amplification image processing system is provided with the linear drive circuit, so that the image processing system can be more stable.
Description
Technical field
The present invention relates to a kind of image processing system, specifically refer to a kind of stable biased enlarged image treatment system.
Background technology
Display is also referred to as monitor usually.Display is the I/O equipment belonging to computer, i.e. input-output equipment.It a kind ofly certain e-file is shown to show tools screen reflexing to again human eye by specific transmission equipment.Its application widely, arrives satellite monitoring greatly, little of seeing VCD, and can say in modern society, its figure is ubiquitous.As the electrical equipment such as television set, computer all can use.Usually all need signal to amplify in the image processing system of display, but current image processing system there will be the situation of distorted signals when signal is amplified, thus affect the display effect of display.
Summary of the invention
The object of the invention is to overcome conventional images treatment system there will be distorted signals defect when signal is amplified, a kind of stable biased enlarged image treatment system is provided.
Object of the present invention is achieved through the following technical solutions: a kind of stable biased enlarged image treatment system, mainly comprise imageing sensor, the image processing circuit be connected with imageing sensor, the signal screening circuit be connected with image processing circuit, the time base circuit for generating be connected with signal screening circuit, with time base circuit for generating the bias amplifier that is connected of output, also linear drive circuit is connected with between image processing circuit and Shi Ji circuit for generating, described linear drive circuit is by driving chip U, triode VT4, triode VT5, triode VT6, triode VT7, positive pole is connected with image processing circuit, the polar capacitor C11 that negative pole is connected with the IN1 pin of driving chip U after resistance R14, one end is connected with the collector electrode of triode VT4, the resistance R15 that the other end is connected with the base stage of triode VT6 after resistance R16, positive pole is connected with the base stage of triode VT4, the polar capacitor C13 that negative pole is connected with the IN1 pin of driving chip U, positive pole is connected with the IN2 pin of driving chip U, the polar capacitor C12 of minus earth, one end is connected with the emitter of triode VT4, the resistance R18 that the other end is connected with the base stage of triode VT5, one end is connected with the base stage of triode VT5, the resistance R17 that the other end is connected with the base stage of triode VT6, N pole is connected with the collector electrode of triode VT4, the diode D1 that P pole is connected with the collector electrode of triode VT5, positive terminal is connected with the collector electrode of triode VT4, the not gate K that end of oppisite phase is connected with triode VT7 collector electrode, one end is connected with triode VT7 emitter, the resistance R20 that the other end is connected with the emitter of triode VT6 after resistance R19, the end of oppisite phase of P pole NAND gate K is connected, the diode D2 that N pole is connected with the tie point of resistance R19 with resistance R20 forms, the VCC pin of described driving chip U is connected with the base stage of triode VT4, END pin ground connection, OUT pin are connected with the collector electrode of triode VT5, the collector electrode of triode VT5 is also connected with the base stage of triode VT5, its emitter is connected with the base stage of triode man VT6, the grounded collector of triode VT6, the N pole of diode D2 with time base circuit for generating be connected.
Described image processing circuit is by process chip U1, triode VT1, the inductance L 2 that one end is connected with the base stage of triode VT1, the other end is then connected with the FX pin of process chip U1, the polar capacitor C1 that negative pole is connected with the BE pin of process chip U1, positive pole is then connected with the emitter of triode VT1 after inductance L 1, the polar capacitor C2 that negative pole is connected with the FC pin of process chip U1, positive pole is then connected with the FI pin of process chip U1 after inductance L 3 forms; The F2 pin of described process chip U1 is connected with imageing sensor, and M1 pin is then connected with the positive pole of polar capacitor C11, and M2 pin is connected with signal screening circuit, the grounded collector of triode VT1.
Time described, base circuit for generating is by triode VT2, one end is connected with bias amplifier, the resistance R5 that the other end is then connected with the base stage of triode VT2, positive pole is connected with the base stage of triode VT2 after resistance R4, the polar capacitor C5 that negative pole is connected with the emitter of triode VT2, positive pole is connected with the positive pole of polar capacitor C5, the polar capacitor C3 of minus earth, one end is connected with the positive pole of polar capacitor C3, the resistance R2 that the other end is then connected with the emitter of triode VT2 after potentiometer R3, and positive pole is connected with the N pole of diode D2, the polar capacitor C4 that negative pole is then connected with the positive pole of polar capacitor C3 after resistance R1 forms, the collector electrode of described triode VT2 is connected with signal screening circuit.
Described signal screening circuit comprises triode VT3, resistance R6, resistance R7, resistance R8, polar capacitor C6; The positive pole of polar capacitor C6 is connected with the collector electrode of triode VT2, minus earth, one end of resistance R7 is connected with the base stage of triode VT3, its other end ground connection, one end of resistance R8 is connected with the collector electrode of triode VT3 after resistance R6, its other end ground connection, and the collector electrode of triode VT3 is connected with the collector electrode of triode VT2, its base stage is then connected with the M2 pin of process chip U1, grounded emitter.
Described bias amplifier is by field effect transistor Q, positive pole is connected with the grid of field effect transistor Q after resistance R10, the polar capacitor C7 of minus earth, one end is connected with the positive pole of polar capacitor C7, the resistance R9 of other end ground connection, one end is connected with the positive pole of polar capacitor C7, the resistance R12 that the other end is connected with the drain electrode of field effect transistor Q after resistance R13, negative pole is connected with the grid of field effect transistor Q, the polar capacitor C8 that positive pole is then connected with resistance R5, positive pole is connected with the drain electrode of field effect transistor Q, negative pole is as the polar capacitor C10 of signal output part, one end is connected with the source electrode of field effect transistor Q, the resistance R11 of other end ground connection, and positive pole is connected with the source electrode of field effect transistor Q, the polar capacitor C9 of minus earth forms, resistance R12 is connected with external power source with the tie point of resistance R13.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) the present invention is provided with bias amplifier, and it adopts external voltage to be biased, signal is amplified time with better bias condition can be obtained, make the signal after amplifying keep undistorted, have better display effect.
(2) the present invention is applicable to different displays, as TV, computer etc.
(3) image processing circuit of the present invention is high-speed processing circuits, and it can make the speed of system process images greatly accelerate.
(4) the present invention is provided with linear drive circuit, and image processing system can be made more stable.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present invention.
Fig. 2 is the structural representation of linear drive circuit of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment
As shown in Figure 1, a kind of stable biased enlarged image treatment system of the present invention, mainly comprise imageing sensor, the image processing circuit be connected with imageing sensor, the signal screening circuit be connected with image processing circuit, the time base circuit for generating be connected with signal screening circuit, with time base circuit for generating the bias amplifier that is connected of output; Also linear drive circuit is connected with between image processing circuit and Shi Ji circuit for generating.
As shown in Figure 2, described linear drive circuit is by driving chip U, triode VT4, triode VT5, triode VT6, triode VT7, positive pole is connected with image processing circuit, the polar capacitor C11 that negative pole is connected with the IN1 pin of driving chip U after resistance R14, one end is connected with the collector electrode of triode VT4, the resistance R15 that the other end is connected with the base stage of triode VT6 after resistance R16, positive pole is connected with the base stage of triode VT4, the polar capacitor C13 that negative pole is connected with the IN1 pin of driving chip U, positive pole is connected with the IN2 pin of driving chip U, the polar capacitor C12 of minus earth, one end is connected with the emitter of triode VT4, the resistance R18 that the other end is connected with the base stage of triode VT5, one end is connected with the base stage of triode VT5, the resistance R17 that the other end is connected with the base stage of triode VT6, N pole is connected with the collector electrode of triode VT4, the diode D1 that P pole is connected with the collector electrode of triode VT5, positive terminal is connected with the collector electrode of triode VT4, the not gate K that end of oppisite phase is connected with triode VT7 collector electrode, one end is connected with triode VT7 emitter, the resistance R20 that the other end is connected with the emitter of triode VT6 after resistance R19, the end of oppisite phase of P pole NAND gate K is connected, the diode D2 that N pole is connected with the tie point of resistance R19 with resistance R20 forms, the VCC pin of described driving chip U is connected with the base stage of triode VT4, END pin ground connection, OUT pin are connected with the collector electrode of triode VT5, the collector electrode of triode VT5 is also connected with the base stage of triode VT5, its emitter is connected with the base stage of triode man VT6, the grounded collector of triode VT6, the N pole of diode D2 with time base circuit for generating be connected.Linear drive circuit, can make image processing system more stable.In order to ensure implementation result, described driving chip U is preferably LM387 integrated chip, its highly sensitive and low price.
Described image processing circuit is by process chip U1, triode VT1, the inductance L 2 that one end is connected with the base stage of triode VT1, the other end is then connected with the FX pin of process chip U1, the polar capacitor C1 that negative pole is connected with the BE pin of process chip U1, positive pole is then connected with the emitter of triode VT1 after inductance L 1, the polar capacitor C2 that negative pole is connected with the FC pin of process chip U1, positive pole is then connected with the FI pin of process chip U1 after inductance L 3 forms; The F2 pin of described process chip U1 is connected with imageing sensor, and M1 pin is then connected with the positive pole of polar capacitor C11, and M2 pin is connected with signal screening circuit, the grounded collector of triode VT1.
Time described, base circuit for generating is by triode VT2, one end is connected with bias amplifier, the resistance R5 that the other end is then connected with the base stage of triode VT2, positive pole is connected with the base stage of triode VT2 after resistance R4, the polar capacitor C5 that negative pole is connected with the emitter of triode VT2, positive pole is connected with the positive pole of polar capacitor C5, the polar capacitor C3 of minus earth, one end is connected with the positive pole of polar capacitor C3, the resistance R2 that the other end is then connected with the emitter of triode VT2 after potentiometer R3, and positive pole is connected with the N pole of diode D2, the polar capacitor C4 that negative pole is then connected with the positive pole of polar capacitor C3 after resistance R1 forms, the collector electrode of described triode VT2 is connected with signal screening circuit.
Described signal screening circuit comprises triode VT3, resistance R6, resistance R7, resistance R8, polar capacitor C6; The positive pole of polar capacitor C6 is connected with the collector electrode of triode VT2, minus earth, one end of resistance R7 is connected with the base stage of triode VT3, its other end ground connection, one end of resistance R8 is connected with the collector electrode of triode VT3 after resistance R6, its other end ground connection, and the collector electrode of triode VT3 is connected with the collector electrode of triode VT2, its base stage is then connected with the M2 pin of process chip U1, grounded emitter.
Described bias amplifier is by field effect transistor Q, positive pole is connected with the grid of field effect transistor Q after resistance R10, the polar capacitor C7 of minus earth, one end is connected with the positive pole of polar capacitor C7, the resistance R9 of other end ground connection, one end is connected with the positive pole of polar capacitor C7, the resistance R12 that the other end is connected with the drain electrode of field effect transistor Q after resistance R13, negative pole is connected with the grid of field effect transistor Q, the polar capacitor C8 that positive pole is then connected with resistance R5, positive pole is connected with the drain electrode of field effect transistor Q, negative pole is as the polar capacitor C10 of signal output part, one end is connected with the source electrode of field effect transistor Q, the resistance R11 of other end ground connection, and positive pole is connected with the source electrode of field effect transistor Q, the polar capacitor C9 of minus earth forms, resistance R12 is connected with external power source with the tie point of resistance R13.
As mentioned above, just well the present invention can be implemented.
Claims (5)
1. a stable biased enlarged image treatment system, mainly comprise imageing sensor, the image processing circuit be connected with imageing sensor, the signal screening circuit be connected with image processing circuit, the time base circuit for generating be connected with signal screening circuit, with time base circuit for generating the bias amplifier that is connected of output, it is characterized in that: between image processing circuit and Shi Ji circuit for generating, be also connected with linear drive circuit, described linear drive circuit is by driving chip U, triode VT4, triode VT5, triode VT6, triode VT7, positive pole is connected with image processing circuit, the polar capacitor C11 that negative pole is connected with the IN1 pin of driving chip U after resistance R14, one end is connected with the collector electrode of triode VT4, the resistance R15 that the other end is connected with the base stage of triode VT6 after resistance R16, positive pole is connected with the base stage of triode VT4, the polar capacitor C13 that negative pole is connected with the IN1 pin of driving chip U, positive pole is connected with the IN2 pin of driving chip U, the polar capacitor C12 of minus earth, one end is connected with the emitter of triode VT4, the resistance R18 that the other end is connected with the base stage of triode VT5, one end is connected with the base stage of triode VT5, the resistance R17 that the other end is connected with the base stage of triode VT6, N pole is connected with the collector electrode of triode VT4, the diode D1 that P pole is connected with the collector electrode of triode VT5, positive terminal is connected with the collector electrode of triode VT4, the not gate K that end of oppisite phase is connected with triode VT7 collector electrode, one end is connected with triode VT7 emitter, the resistance R20 that the other end is connected with the emitter of triode VT6 after resistance R19, the end of oppisite phase of P pole NAND gate K is connected, the diode D2 that N pole is connected with the tie point of resistance R19 with resistance R20 forms, the VCC pin of described driving chip U is connected with the base stage of triode VT4, END pin ground connection, OUT pin are connected with the collector electrode of triode VT5, the collector electrode of triode VT5 is also connected with the base stage of triode VT5, its emitter is connected with the base stage of triode man VT6, the grounded collector of triode VT6, the N pole of diode D2 with time base circuit for generating be connected.
2. a kind of stable biased enlarged image treatment system according to claim 1, it is characterized in that: described image processing circuit is by process chip U1, triode VT1, one end is connected with the base stage of triode VT1, the inductance L 2 that the other end is then connected with the FX pin of process chip U1, negative pole is connected with the BE pin of process chip U1, the polar capacitor C1 that positive pole is then connected with the emitter of triode VT1 after inductance L 1, negative pole is connected with the FC pin of process chip U1, the polar capacitor C2 that positive pole is then connected with the FI pin of process chip U1 after inductance L 3 forms, the F2 pin of described process chip U1 is connected with imageing sensor, and M1 pin is then connected with the positive pole of polar capacitor C11, and M2 pin is connected with signal screening circuit, the grounded collector of triode VT1.
3. a kind of stable biased enlarged image treatment system according to claim 2, it is characterized in that: time described, base circuit for generating is by triode VT2, one end is connected with bias amplifier, the resistance R5 that the other end is then connected with the base stage of triode VT2, positive pole is connected with the base stage of triode VT2 after resistance R4, the polar capacitor C5 that negative pole is connected with the emitter of triode VT2, positive pole is connected with the positive pole of polar capacitor C5, the polar capacitor C3 of minus earth, one end is connected with the positive pole of polar capacitor C3, the resistance R2 that the other end is then connected with the emitter of triode VT2 after potentiometer R3, and positive pole is connected with the N pole of diode D2, the polar capacitor C4 that negative pole is then connected with the positive pole of polar capacitor C3 after resistance R1 forms, the collector electrode of described triode VT2 is connected with signal screening circuit.
4. a kind of stable biased enlarged image treatment system according to claim 3, is characterized in that: described signal screening circuit comprises triode VT3, resistance R6, resistance R7, resistance R8, polar capacitor C6; The positive pole of polar capacitor C6 is connected with the collector electrode of triode VT2, minus earth, one end of resistance R7 is connected with the base stage of triode VT3, its other end ground connection, one end of resistance R8 is connected with the collector electrode of triode VT3 after resistance R6, its other end ground connection, and the collector electrode of triode VT3 is connected with the collector electrode of triode VT2, its base stage is then connected with the M2 pin of process chip U1, grounded emitter.
5. a kind of stable biased enlarged image treatment system according to claim 4, it is characterized in that: described bias amplifier is by field effect transistor Q, positive pole is connected with the grid of field effect transistor Q after resistance R10, the polar capacitor C7 of minus earth, one end is connected with the positive pole of polar capacitor C7, the resistance R9 of other end ground connection, one end is connected with the positive pole of polar capacitor C7, the resistance R12 that the other end is connected with the drain electrode of field effect transistor Q after resistance R13, negative pole is connected with the grid of field effect transistor Q, the polar capacitor C8 that positive pole is then connected with resistance R5, positive pole is connected with the drain electrode of field effect transistor Q, negative pole is as the polar capacitor C10 of signal output part, one end is connected with the source electrode of field effect transistor Q, the resistance R11 of other end ground connection, and positive pole is connected with the source electrode of field effect transistor Q, the polar capacitor C9 of minus earth forms, resistance R12 is connected with external power source with the tie point of resistance R13.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410709020.6A CN104469190A (en) | 2014-11-29 | 2014-11-29 | Stable biasing amplification image processing system |
| CN201510325374.5A CN104980624A (en) | 2014-11-29 | 2015-06-14 | Biased and amplified image processing system based on non-isolated output step-down |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410709020.6A CN104469190A (en) | 2014-11-29 | 2014-11-29 | Stable biasing amplification image processing system |
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| CN104469190A true CN104469190A (en) | 2015-03-25 |
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| CN201410709020.6A Pending CN104469190A (en) | 2014-11-29 | 2014-11-29 | Stable biasing amplification image processing system |
| CN201510325374.5A Withdrawn CN104980624A (en) | 2014-11-29 | 2015-06-14 | Biased and amplified image processing system based on non-isolated output step-down |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510325374.5A Withdrawn CN104980624A (en) | 2014-11-29 | 2015-06-14 | Biased and amplified image processing system based on non-isolated output step-down |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104700350A (en) * | 2015-03-31 | 2015-06-10 | 宁波摩米创新工场电子科技有限公司 | High-precision image processing system |
| CN104820107A (en) * | 2015-05-06 | 2015-08-05 | 成都诚邦动力测试仪器有限公司 | Motor speed test system based on phase-locked loop circuit |
| CN104833817A (en) * | 2015-05-06 | 2015-08-12 | 成都诚邦动力测试仪器有限公司 | Motor speed measuring system based on linear drive |
| CN104897920A (en) * | 2015-05-06 | 2015-09-09 | 成都诚邦动力测试仪器有限公司 | Motor rotating speed testing system based on double field-effect transistor oscillating circuit |
| CN104950127A (en) * | 2015-05-06 | 2015-09-30 | 成都诚邦动力测试仪器有限公司 | Motor speed testing system based on logical amplifying circuit |
| CN105545146A (en) * | 2015-12-22 | 2016-05-04 | 成都雷纳斯科技有限公司 | Smart theft protection system |
-
2014
- 2014-11-29 CN CN201410709020.6A patent/CN104469190A/en active Pending
-
2015
- 2015-06-14 CN CN201510325374.5A patent/CN104980624A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104700350A (en) * | 2015-03-31 | 2015-06-10 | 宁波摩米创新工场电子科技有限公司 | High-precision image processing system |
| CN104820107A (en) * | 2015-05-06 | 2015-08-05 | 成都诚邦动力测试仪器有限公司 | Motor speed test system based on phase-locked loop circuit |
| CN104833817A (en) * | 2015-05-06 | 2015-08-12 | 成都诚邦动力测试仪器有限公司 | Motor speed measuring system based on linear drive |
| CN104897920A (en) * | 2015-05-06 | 2015-09-09 | 成都诚邦动力测试仪器有限公司 | Motor rotating speed testing system based on double field-effect transistor oscillating circuit |
| CN104950127A (en) * | 2015-05-06 | 2015-09-30 | 成都诚邦动力测试仪器有限公司 | Motor speed testing system based on logical amplifying circuit |
| CN105545146A (en) * | 2015-12-22 | 2016-05-04 | 成都雷纳斯科技有限公司 | Smart theft protection system |
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| Publication number | Publication date |
|---|---|
| CN104980624A (en) | 2015-10-14 |
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Application publication date: 20150325 |