CN105049677A - Intelligent high-definition multi-screen image processing system based on noise reduction processing - Google Patents
Intelligent high-definition multi-screen image processing system based on noise reduction processing Download PDFInfo
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Abstract
The present invention discloses an intelligent high-definition multi-screen image processing system based on noise reduction processing. The system is formed by an image collector (1), a digital signal processor (5), an amplifying unit (2) which is connected to the image collector (1), an image converting unit (3) which is connected to the amplifying unit (2), an FIFO memory (4) which is connected to the digital signal processor (5), a memory (6), a data output unit (7) and more than two monitors (8) which are connected to the data output unit (7). The system is characterized in that a noise reduction processing unit is arranged between the image converting unit (3) and the FIFO memory (4), the noise interference signal generated by the system can be filtered, and thus the processing precision can be improved. At the same time, the system has good linearity, and so the definition of an image is high in display.
Description
Technical field
The present invention relates to a kind of image processing system, specifically refer to a kind of intelligent high-definition multi-screen image treatment system based on noise reduction process.
Background technology
Image processing techniques is widely used in computer vision association area, and such as based on the face identification of image, expression recognition, gender classification and face age are estimated.Meanwhile, the new technology of the link such as along with the development of digital technology, image is shot with video-corder, store, transmit, display emerges in an endless stream, and society is more strong to the demand of reappearing nature living scene by audio-visual aids more really.The industries such as engineering design, military affairs, medical treatment are also increasing for the demand of the display screen of ultrahigh resolution.Therefore, on the HDTV Systems generally applied at present and display specification, the audiovisual standard of ultrahigh resolution and application can become the new focus in digital audio-video field.
Ultrahigh resolution refers to higher than current high definition resolution 1920 × 1080, reach 4 times of high definition resolution i.e. 3840 × 2160 (or 4096 × 2160), even the 16 times of high definition resolution i.e. display format of 7680 × 4320 (or 8192 × 4320).Also under test in the ultrahigh resolution program record and broadcast of digital television broadcasting field at present, in display field, be proposed ultrahigh resolution display model machine.In order to adapt to this situation, schedule just put on by ultrahigh resolution signal generator.
Now, the present situation on over-large screen display system is, the first, and owing to not having the signal source of ultrahigh resolution, namely signal source is easily subject to noise jamming.The second, adopt Video processing and splicing, a high definition or standard definition signal are passed through segmentation, each tiled display shows, such method, usually can increase with display screen, and reduce the resolution of image.No matter which kind of scheme above-mentioned, does not all adopt the real signal source having ultrahigh resolution information, cannot show superelevation complete image content clearly, impair final bandwagon effect.
Summary of the invention
The object of the invention is to overcome traditional image processing system be easily subject to noise jamming and cause the defect that its display precision is not high, a kind of intelligent high-definition multi-screen image treatment system based on noise reduction process is provided.
Object of the present invention is achieved through the following technical solutions: a kind of intelligent high-definition multi-screen image treatment system based on noise reduction process, it is by image acquisition device, digital signal processor, the amplifying unit be connected with image acquisition device, the image conversion unit be connected with amplifying unit, the FIFO memory be connected with digital signal processor, memory and data outputting unit, the display of more than 2 that are connected with data outputting unit, and be arranged on the noise reduction processing unit composition between image conversion unit and FIFO memory.
Further, described noise reduction processing unit is by triode VT3, triode VT4, triode VT5, triode VT6, one end is connected with the emitter of triode VT6, the resistance R13 of the other end then ground connection, one end is connected with the emitter of triode VT6, the resistance R16 that the other end is then connected with the base stage of triode VT3 after resistance R17, one end is connected with the emitter of triode VT6, the resistance R14 that the other end is then connected with the base stage of triode VT3 after resistance R15, one end is connected with the emitter of triode VT3, the resistance R18 that the other end is then connected with the base stage of triode VT4, positive pole is connected with the base stage of triode VT3, the polar capacitor C11 that negative pole is then connected with the tie point of resistance R17 with resistance R16 after polar capacitor C10, and one end is connected with the negative pole of polar capacitor C11, the other end then after inductance L 2 inductance L 1 of ground connection form, the output that the collector electrode of described triode VT4 is connected with the tie point of inductance L 2 with inductance L 1, its grounded emitter, base stage then form this noise reduction processing unit, the base stage of described triode VT5 is connected with the tie point of resistance R15 with resistance R14, its collector electrode is then connected with the emitter of triode VT6, and its emitter is then connected with collector electrode with the base stage of triode VT3 simultaneously, the collector electrode of described triode VT6 connects the input that its base stage of+12V voltage then forms this noise reduction processing unit.
Described amplifying unit is by amplifier P1, amplifier P2, positive pole is connected with the positive pole of amplifier P1 after resistance R1, negative pole then forms the polar capacitor C1 of the input of this amplifying unit, be serially connected in the polar capacitor C3 between the positive pole of amplifier P1 and output, be serially connected in the resistance R5 between the negative pole of amplifier P2 and output, be serially connected in the resistance R4 between the output of amplifier P1 and the positive pole of amplifier P2, one end is ground connection after resistance R3, the other end then meets the resistance R2 of 15V voltage, positive pole is connected with the negative pole of amplifier P1, the polar capacitor C2 of minus earth, and input is connected with the negative pole of amplifier P2, output then after diode D1 ground connection biasing circuit composition, the negative pole of described amplifier P2 respectively with resistance R2 and the tie point of resistance R3 and the positive pole of polar capacitor C2 is connected, its output then forms this amplifying unit output.
Described biasing circuit is by field effect transistor MOS1, triode VT1, positive pole is connected with the grid of field effect transistor MOS1 after resistance R6, the polar capacitor C4 that negative pole is then connected with the negative pole of amplifier P2, positive pole is connected with the drain electrode of field effect transistor MOS1, negative pole is the polar capacitor C6 of ground connection after diode D1 then, positive pole is connected with the positive pole of polar capacitor C4, the polar capacitor C5 of minus earth, P pole is connected with the positive pole of polar capacitor C5, N pole is then through diode D3 that resistance R8 is connected with the collector electrode of triode VT1 after resistance R7, and form with the voltage stabilizing didoe D2 that resistance R8 is in parallel, the emitter of described triode VT1 is connected with the source electrode of field effect transistor MOS1 and the P pole of diode D3 respectively, and its base stage is then connected with the N pole of diode D3.
Described image conversion unit is by amplifier P3, NAND gate A1, NAND gate A2, triode VT2, N pole is connected with the positive pole of amplifier P3, P pole then forms the diode D4 of the input of this image conversion unit, positive pole is connected with the P pole of diode D4, the polar capacitor C7 of minus earth, the resistance R9 be in parallel with polar capacitor C7, positive pole connects 15V voltage after resistance R10, the polar capacitor C8 of minus earth, the potentiometer R11 be in parallel with polar capacitor C8, P pole is connected with the negative pole of amplifier P3, the diode D5 that N pole is then connected with the positive pole of NAND gate A1 after inverting amplifier D6, be serially connected in the resistance R12 between the output of amplifier P3 and the collector electrode of triode VT2, and the polar capacitor C9 be serially connected between the emitter of triode VT2 and the output of NAND gate A2 forms, the positive pole of described amplifier P3 is all connected with the positive pole of polar capacitor C8 with negative pole, its negative pole is also connected with the base stage of triode VT2, its output is then connected with the negative pole of NAND gate A2, the negative pole of described NAND gate A1 is connected with the output of NAND gate A2, and its output forms the output of this image conversion unit while being then connected with the positive pole of NAND gate A2.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) recognition speed of the present invention is fast, and accuracy of identification is high, can be widely used in real-time industrial application and public utility field, and replacing prior art becomes mainstream technology, reduces equipment cost, numerous field boundarys is closed and is applied, obvious economic.
(2) the present invention has the good linearity, and therefore image definition when showing is very high.
(3) the present invention can filter out the noise jamming signal that system self produces, thus can improve its place
Reason precision.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present invention.
Fig. 2 is amplifying unit electrical block diagram of the present invention.
Fig. 3 is bias circuit construction schematic diagram of the present invention.
Fig. 4 is image conversion unit electrical block diagram of the present invention.
Fig. 5 is noise reduction processing unit circuit diagram of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, the present invention is by image acquisition device 1, the amplifying unit 2 be connected with image acquisition device 1, the image conversion unit 3 be connected with amplifying unit 2, the noise reduction processing unit 9 be connected with image conversion unit 3, the FIFO memory 4 be connected with noise reduction processing unit 9, the digital signal processor 5 be connected with FIFO memory 4, the memory 6 be connected with digital signal processor 5 and data outputting unit 7, and the display 8 of more than 2 be connected with data outputting unit 7 forms.The present embodiment adopts 3 displays 8 to be described.
Wherein, image acquisition device 1 is for gathering echo signal, and it can adopt video camera or camera to realize.Amplifying unit 2 for image acquisition device 1 gather come signal carry out amplifications process; Image conversion unit 3 is then for being converted into the form that computer and memory module can identify and process by the picture signal collected.Noise reduction processing unit 9 can filtration system produce interfering noise; FIFO memory 4 can carry out Quick Acquisition, sequential storage and transmission to the data of high-speed transfer, namely first data first entered in FIFO memory 4 is moved out of, therefore it can carry out buffer memory to continuous print data, prevent the obliterated data when entering machine operation, bus operation frequently can be avoided, the burden of mitigation system simultaneously.In order to reach better implementation result, the IDT7203 series memory that this FIFO memory preferentially adopts Integrated Device Technology, Inc. to produce realizes.
Digital signal processor 5 can be measured picture signal and filtering process, and it adopts prior art to realize.Memory 6 can do to the picture signal after process the storage carrying out a step, avoids picture signal to lose.This data outputting unit 7, for being divided into more than 2 tunnels to picture signal, namely being split the picture signal received for the multiway images signal equal with display 8 quantity, and is flowed to display 8.Display 8 then forms display array, and it is for receiving the picture signal after segmentation, and the picture signal content after tiled display segmentation.This memory 6, data outputting unit 7 and display 8 all adopt prior art to realize.
As shown in Figure 2,3, this amplifying unit 2 is by amplifier P1, and amplifier P2, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, polar capacitor C1, polar capacitor C2, polar capacitor C3, diode D1 and biasing circuit form.
Described biasing circuit is then by field effect transistor MOS1, and triode VT1, resistance R6, resistance R7, resistance R8, polar capacitor C4, polar capacitor C5, polar capacitor C6, diode D2 and diode D3 form.
During connection, the positive pole of polar capacitor C4 is connected with the grid of field effect transistor MOS1 after resistance R6, its negative pole is then connected with the negative pole of amplifier P2, the positive pole of polar capacitor C6 is connected with the drain electrode of field effect transistor MOS1, its negative pole then ground connection after diode D1, the positive pole of polar capacitor C5 is connected with the positive pole of polar capacitor C4, its minus earth, the P pole of diode D3 is connected with the positive pole of polar capacitor C5, its N pole is then connected with the collector electrode of triode VT1 after resistance R7 through resistance R8, and voltage stabilizing didoe D2 is then in parallel with resistance R8.Meanwhile, the emitter of described triode VT1 is connected with the source electrode of field effect transistor MOS1 and the P pole of diode D3 respectively, and its base stage is then connected with the N pole of diode D3.The tie point of resistance R8 and resistance R7 also needs ground connection.
The positive pole of polar capacitor C1 is connected with the positive pole of amplifier P1 after resistance R1, its negative pole then forms the input of this amplifying unit 2, between the positive pole that polar capacitor C3 is then serially connected in amplifier P1 and output, between the negative pole that resistance R5 is serially connected in amplifier P2 and output, resistance R4 is serially connected between the output of amplifier P1 and the positive pole of amplifier P2, one end ground connection after resistance R3 of resistance R2, its other end then connects 15V voltage, the positive pole of polar capacitor C2 is connected with the negative pole of amplifier P1, its minus earth, the N pole of diode D1 connects, its P pole is then connected with the negative pole of polar capacitor C6.
The negative pole of described amplifier P2 respectively with resistance R2 and the tie point of resistance R3 and the positive pole of polar capacitor C2 is connected, its output then forms this amplifying unit 2 output.Therefore, amplifier P1, amplifier P2, resistance R1, polar capacitor C2, resistance R4 and resistance R5 then form a dual-stage amplifier, and this biasing circuit then guarantees that this dual-stage amplifier can distortionlessly amplify picture signal.
As shown in Figure 4, this image conversion unit 3 by amplifier P3, NAND gate A1, NAND gate A2, resistance R9, resistance R10, potentiometer R11, resistance R12, polar capacitor C7, polar capacitor C8, polar capacitor C9, diode D4, diode D5, inverting amplifier D6 and triode VT2 form.
During connection, the input that the N pole of diode D4 is connected with the positive pole of amplifier P3, its P pole then forms this image conversion unit 3, the positive pole of polar capacitor C7 is connected with the P pole of diode D4, its minus earth, resistance R9 is then in parallel with polar capacitor C7, and this polar capacitor C7 and resistance R9 then forms a RC filter circuit thus.
The positive pole of polar capacitor C8 connects 15V voltage, its minus earth after resistance R10, potentiometer R11 and polar capacitor C8 is in parallel, the P pole of diode D5 is connected with the negative pole of amplifier P3, its N pole is then connected with the positive pole of NAND gate A1 after inverting amplifier D6, resistance R12 is serially connected between the output of amplifier P3 and the collector electrode of triode VT2, between the emitter that polar capacitor C9 is serially connected in triode VT2 and the output of NAND gate A2.
Meanwhile, the positive pole of described amplifier P3 is all connected with the positive pole of polar capacitor C8 with negative pole, its negative pole is also connected with the base stage of triode VT2, its output is then connected with the negative pole of NAND gate A2.The negative pole of described NAND gate A1 is connected with the output of NAND gate A2, and its output forms the output of this image conversion unit 3 while being then connected with the positive pole of NAND gate A2.
As shown in Figure 5, this noise reduction processing unit by triode VT3, triode VT4, triode VT5, triode VT6, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, inductance L 1, inductance L 2, polar capacitor C10 and polar capacitor C11 forms.
Wherein, this resistance R16, resistance R17, polar capacitor C10, polar capacitor C11, inductance L 1 and an inductance L 2 composition trapper, this trapper can filter away high frequency noise.Its concrete structure is that one end of resistance R16 is connected with the emitter of triode VT6, its other end is then connected with the base stage of triode VT3 after resistance R17, the positive pole of polar capacitor C11 is connected with the base stage of triode VT3, its negative pole is then connected with the tie point of resistance R17 with resistance R16 after polar capacitor C10, and one end of inductance L 1 is connected with the negative pole of polar capacitor C11, its other end then ground connection after inductance L 2.
Simultaneously, one end of this resistance R13 is connected with the emitter of triode VT6, its other end then ground connection, one end of resistance R14 is connected with the emitter of triode VT6, its other end is then connected with the base stage of triode VT3 after resistance R15, and one end of resistance R18 is connected with the emitter of triode VT3, its other end is then connected with the base stage of triode VT4.
Described triode VT5 is switching tube, it is by the control of noise reduction switching signal, during connection its base stage be connected with the tie point of resistance R15 with resistance R14, its collector electrode be then connected with the emitter of triode VT6 its emitter then while be connected with collector electrode with the base stage of triode VT3; Then cancel decrease of noise functions when triode VT5 conducting, when it ends, frequency-selecting signal is then through this trapper filter away high frequency noise.
In order to enable this noise reduction processing unit work normally, the collector electrode of described triode VT6 connects the input that its base stage of+12V voltage then forms this noise reduction processing unit 9.The output that the collector electrode of this triode VT4 then needs to be connected with the tie point of inductance L 2 with inductance L 1, its grounded emitter, base stage then form this noise reduction processing unit.
As mentioned above, just the present invention can well be realized.
Claims (4)
1. the intelligent high-definition multi-screen image treatment system based on noise reduction process, it is by image acquisition device (1), digital signal processor (5), the amplifying unit (2) be connected with image acquisition device (1), the image conversion unit (3) be connected with amplifying unit (2), the FIFO memory (4) be connected with digital signal processor (5), memory (6) and data outputting unit (7), and the display (8) of more than 2 be connected with data outputting unit (7) forms, it is characterized in that, between image conversion unit (3) and FIFO memory (4), be also provided with noise reduction processing unit (9), described noise reduction processing unit (9) is by triode VT3, triode VT4, triode VT5, triode VT6, one end is connected with the emitter of triode VT6, the resistance R13 of the other end then ground connection, one end is connected with the emitter of triode VT6, the resistance R16 that the other end is then connected with the base stage of triode VT3 after resistance R17, one end is connected with the emitter of triode VT6, the resistance R14 that the other end is then connected with the base stage of triode VT3 after resistance R15, one end is connected with the emitter of triode VT3, the resistance R18 that the other end is then connected with the base stage of triode VT4, positive pole is connected with the base stage of triode VT3, the polar capacitor C11 that negative pole is then connected with the tie point of resistance R17 with resistance R16 after polar capacitor C10, and one end is connected with the negative pole of polar capacitor C11, the other end then after inductance L 2 inductance L 1 of ground connection form, the output that the collector electrode of described triode VT4 is connected with the tie point of inductance L 2 with inductance L 1, its grounded emitter, base stage then form this noise reduction processing unit (9), the base stage of described triode VT5 is connected with the tie point of resistance R15 with resistance R14, its collector electrode is then connected with the emitter of triode VT6, and its emitter is then connected with collector electrode with the base stage of triode VT3 simultaneously, the collector electrode of described triode VT6 connects the input that its base stage of+12V voltage then forms this noise reduction processing unit (9).
2. a kind of intelligent high-definition multi-screen image treatment system based on noise reduction process according to claim 1, it is characterized in that: described amplifying unit (2) is by amplifier P1, amplifier P2, positive pole is connected with the positive pole of amplifier P1 after resistance R1, negative pole then forms the polar capacitor C1 of the input of this amplifying unit (2), be serially connected in the polar capacitor C3 between the positive pole of amplifier P1 and output, be serially connected in the resistance R5 between the negative pole of amplifier P2 and output, be serially connected in the resistance R4 between the output of amplifier P1 and the positive pole of amplifier P2, one end is ground connection after resistance R3, the other end then meets the resistance R2 of 15V voltage, positive pole is connected with the negative pole of amplifier P1, the polar capacitor C2 of minus earth, and input is connected with the negative pole of amplifier P2, output then after diode D1 ground connection biasing circuit composition, the negative pole of described amplifier P2 respectively with resistance R2 and the tie point of resistance R3 and the positive pole of polar capacitor C2 is connected, its output then forms this amplifying unit (2) output.
3. a kind of intelligent high-definition multi-screen image treatment system based on noise reduction process according to claim 2, it is characterized in that: described biasing circuit is by field effect transistor MOS1, triode VT1, positive pole is connected with the grid of field effect transistor MOS1 after resistance R6, the polar capacitor C4 that negative pole is then connected with the negative pole of amplifier P2, positive pole is connected with the drain electrode of field effect transistor MOS1, negative pole is the polar capacitor C6 of ground connection after diode D1 then, positive pole is connected with the positive pole of polar capacitor C4, the polar capacitor C5 of minus earth, P pole is connected with the positive pole of polar capacitor C5, N pole is then through diode D3 that resistance R8 is connected with the collector electrode of triode VT1 after resistance R7, and form with the voltage stabilizing didoe D2 that resistance R8 is in parallel, the emitter of described triode VT1 is connected with the source electrode of field effect transistor MOS1 and the P pole of diode D3 respectively, and its base stage is then connected with the N pole of diode D3.
4. a kind of intelligent high-definition multi-screen image treatment system based on noise reduction process according to claim 3, it is characterized in that: described image conversion unit (3) is by amplifier P3, NAND gate A1, NAND gate A2, triode VT2, N pole is connected with the positive pole of amplifier P3, P pole then forms the diode D4 of the input of this image conversion unit (3), positive pole is connected with the P pole of diode D4, the polar capacitor C7 of minus earth, the resistance R9 be in parallel with polar capacitor C7, positive pole connects 15V voltage after resistance R10, the polar capacitor C8 of minus earth, the potentiometer R11 be in parallel with polar capacitor C8, P pole is connected with the negative pole of amplifier P3, the diode D5 that N pole is then connected with the positive pole of NAND gate A1 after inverting amplifier D6, be serially connected in the resistance R12 between the output of amplifier P3 and the collector electrode of triode VT2, and the polar capacitor C9 be serially connected between the emitter of triode VT2 and the output of NAND gate A2 forms, the positive pole of described amplifier P3 is all connected with the positive pole of polar capacitor C8 with negative pole, its negative pole is also connected with the base stage of triode VT2, its output is then connected with the negative pole of NAND gate A2, the negative pole of described NAND gate A1 is connected with the output of NAND gate A2, and its output forms the output of this image conversion unit (3) while being then connected with the positive pole of NAND gate A2.
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| CN105486876A (en) * | 2015-12-21 | 2016-04-13 | 成都尼奥尔电子科技有限公司 | Novel alcohol content tester based on signal noise reduction circuit |
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