CN104467769B - Signal pin drive circuit on piece upper switch gradual control circuit and method, piece - Google Patents
Signal pin drive circuit on piece upper switch gradual control circuit and method, piece Download PDFInfo
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Abstract
The present invention provides signal pin drive circuit in a kind of piece upper switch gradual control circuit and method, piece, and described upper switch gradual control circuit comprises at least：Tube module is switched, the switch tube module comprises at least the switching tube that n levels are connected in parallel；Control terminal drive module, the control terminal drive module comprise at least n level drivers, and the control terminal of the output ends of drivers at different levels respectively with switching tubes at different levels is connected, for driving switching tubes at different levels；Time delay chain, the time delay chain comprises at least 1 grade of time delay module being connected in series of n, the wherein input of the input of first order time delay module and first order driver accesses a control logic input signal jointly, and the output end of the n-th 1 grades of time delay modules is connected with the input of n-th grade of driver.The piece upper switch gradual control circuit of the present invention, current changing rate can be effectively reduced, and on the premise of equally current changing rate is reduced, there is most short on or off process, switching speed is maximized.
Description
Technical field
The present invention relates to VLSI Design technical field, more particularly to a kind of piece upper switch gradual control electricity
Signal pin drive circuit on road and method, piece.
Background technology
With the raising of modern chips integrated level, there is increasing signal pin to need to drive on same chip.This
A little signal pin loads to be driven are possibly different from, such as it is electric capacity that common cmos digital signal pipe is foot-powered, is opened
It is inductance that powered-down source signal pipe is foot-powered, and it is the transmission line of resistive load that high-speed interface DDR signal pipe is foot-powered.But nothing
By be which kind of load, its function to be completed in itself of output stage switch control circuit be all allow electric current signal pin with
It is switched fast between power line or ground wire.And all these current switches can all face one it is common the problem of, be exactly to chip
The disturbance of interior power line (or ground wire).
As shown in figure 1, the pin of chip physically generally by pressure welding line and package tube payment to a porter with outside chip
Wire is connected, and power line (or ground wire) is also such.Pressure welding line and package tube payment to a porter can in chip VDD (or GND) and chip
The self-induction LVDD (or LGND) of parasitism is introduced between outer power line (or ground wire), should be from inductance value size and packing forms, pressure welding
Line is related to the physical size of pin, common in 1~10nH or so.When the electric current acute variation passed through in the self-induction, i.e.,
Chip exterior is set to be preferably stable power line (or ground wire), VDD (or GND) current potential also can be in self induction electromotive force in chip
Lower produce of effect significantly disturbs.This disturbance would generally produce larger interference to other sensitive circuits on chip, can when serious
Unexpected capability error can be caused, so as to reduce the overall performance of chip.
We can simply estimate the amplitude of transient-upset voltage according to self induction electromotive force, using below equation (1)：
Assuming that parasitic self-induction L=10nH, its electric current passed through increases to 100mA, i.e. current changing rate within the 1ns timesThen moment is superimposed upon the self induction electromotive force on VDD in chip (or GND)
If output current is very big or has multiple pins while is exporting, the amplitude of this disturbance will also be more serious.From formula
(1) we are it is also seen that there is the interference that two approach can reduce self induction electromotive force：First, reduce parasitic self-induction, second, reducing
Current changing rate.The former needs to select smaller encapsulation, distributes more pins to power and ground, but for system core
This means higher packaging cost for piece；And the latter is only the core objective of actual circuit solution.
Existing technology is typically all to reduce current changing rate by delaying the slope of switch controlled end signal.Such as figure
It is a method using RC delays shown in 2 to delay to control terminal voltage VG piece upper switch control circuit.Fig. 3 is switching tube M
During turn-on and turn-off everywhere voltage x current over time t change schematic diagram.When control logic input signal IN is from " 0 "
When jumping to " 1 ", expression will allow switching tube M to become to turn on from shut-off；Logical signal " 1 " is converted into switch by drive module DRV
Supply voltage VDD needed for pipe M, terminal voltage VG is then controlled gradually to rise to VDD from 0V in the presence of RC delays；Due to RC
The speed that the waveform of delay rises voltage is slower and slower, so (control terminal voltage VG surpasses switching tube M electric current ID after switch
Cross cut-in voltage VON) and rise slower and slower；Deng control terminal voltage VG through longer delay reach supply voltage VDD with
Afterwards, electric current ID just reaches fully on electric current ION.When control logic input signal IN jumps to " 0 " from " 1 ", expression will allow
Switching tube M becomes to turn off from conducting；Logical signal " 0 " is converted into the voltage 0V needed for switching tube M by drive module DRV, then
Control terminal voltage VG gradually drops to 0V in the presence of RC delays from supply voltage VDD；Because the waveform of RC delays makes voltage
The speed of decline is slower and slower, and switching tube M electric current ID is also that the speed declined is slower and slower；When the low mistakes of control terminal voltage VG
During VON, electric current ID is 0, but controls terminal voltage VG to still need by dropping to 0V from VON compared with long delay, and arrival complete switches off state.
Since the analysis of above turn-on and turn-off process as can be seen that the peak value of current changing rate is led always occurring from just
It is logical and at the time of begin to turn off, in order to reduce current changing rate must just reduce control terminal voltage VG begin to ramp up or declines at the beginning of
Beginning speed.But because the effect of RC delays is to control terminal voltage VG speed slower and slower, so control terminal voltage VG is upper
The delay that liter or the latter stage declined need to grow gets to supply voltage VDD or 0V very much.Come from the effect for reducing current changing rate
Weigh, at the time of this section of delay does not act on peak value, simply add the time of on or off process in vain, reduce
Switching speed.This is exactly the disadvantage of prior art.
Therefore, a kind of switch control that can be effectively reduced current changing rate and can and keep very fast switching speed is needed badly now
Method, to reduce the interference of self induction electromotive force, improve the overall performance of chip.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of piece upper switch gradual control electricity
Signal pin drive circuit on road and method, piece, for solving that current changing rate can not be effectively reduced in the prior art, so as to nothing
Method reduces the interference of self induction electromotive force, adds time of on or off process on the contrary, the problem of causing switching speed to reduce.
In order to achieve the above objects and other related objects, the present invention provides a kind of piece upper switch gradual control circuit, wherein,
Described upper switch gradual control circuit comprises at least：
Tube module is switched, the switch tube module comprises at least the switching tube that n levels are connected in parallel；
Control terminal drive module, the control terminal drive module comprise at least n level drivers, the output end of drivers at different levels
The control terminal with switching tubes at different levels is connected respectively, for driving switching tubes at different levels；
Time delay chain, the time delay module that the time delay chain is connected in series including at least n-1 levels, wherein first order time delay module
The input of input and first order driver accesses a control logic input signal jointly, and (n-1)th grade of time delay module is defeated
Go out end with the input of n-th grade of driver to be connected, for prolonging according to the control logic input signal and time delay module at different levels
When driver described in time gradual control, to drive the switching tube on or off step by step；
Wherein, n is the natural number more than or equal to 2.
Preferably, time delay modules at different levels have identical or different delay time, and the delay time of time delay module at different levels
The rise time or fall time of the control terminal voltage of the switching tubes at different levels of driver drivings respectively less than at different levels.
Preferably, the switching tube is nmos pass transistor or PMOS transistor.
Preferably, the driver comprises at least the CMOS inverter of two-stage series connection connection.
Preferably, the time delay module comprises at least the CMOS inverter of two-stage series connection connection.
The present invention also provides signal pin drive circuit on a kind of piece, for driving load, wherein, described upper signal pipe
Pin drive circuit comprises at least：
Piece upper switch gradual control circuit as described above.
Preferably, described upper signal pin drive circuit also includes：Ground wire parasitism self-induction；The ground wire parasitism self-induction
One end is connected with described upper switch gradual control circuit, the other end ground connection of the ground wire parasitism self-induction or supply voltage.
The present invention also provides a kind of piece upper switch gradual control method, wherein, described upper switch gradual control method is adopted
With piece upper switch gradual control circuit as described above, it comprises at least following steps：
Drivers at different levels are set, make the control terminal voltage of the switching tubes at different levels of drivers at different levels driving rise time or under
Time meet demand drops；
Time delay modules at different levels are set, the delay time of time delay modules at different levels is respectively less than at different levels the opening of driver drivings at different levels
Close the rise time or fall time of the control terminal voltage of pipe；
The driver according to the delay time gradual control of the control logic input signal and time delay module at different levels, with
The switching tube on or off is driven step by step.
Preferably, the drive according to the delay time gradual control of the control logic input signal and time delay module at different levels
Dynamic device, to drive the switching tube on or off step by step, specific method is：
The control logic input signal from low transition be high level when, control logic input signal control
First order driver, to drive first order switching tube, the control terminal voltage of the first order switching tube is set to be raised to power supply from above freezing
Voltage, so that the first order switching tube turns on；
While the control logic input signal controls first order driver, the control logic input signal is also entered
Enter first order time delay module, after the delay time of the first order time delay module, first order time delay module output the
One-level delay control signal, the first order delay control signal control second level driver, to drive second level switching tube, made
The control terminal voltage of the second level switching tube is raised to supply voltage from above freezing, so that the second level switching tube turns on；
With this gradual control, while the n-th -2 grades delay control signals control (n-1)th grade of driver, described the
N-2 levels delay control signal is also into (n-1)th grade of time delay module, after the delay time of (n-1)th grade of time delay module, institute
State (n-1)th grade of time delay module and export (n-1)th grade of delay control signal, (n-1)th grade of delay control signal controls n-th grade of driving
Device, to drive n-th grade of switching tube, the control terminal voltage of n-th grade of switching tube is set to be raised to supply voltage from above freezing, so that institute
N-th grade of switching tube conducting is stated, completes the conducting step by step of piece upper switch.
Preferably, the drive according to the delay time gradual control of the control logic input signal and time delay module at different levels
Dynamic device, to drive the switching tube on or off step by step, specific method is：
The control logic input signal from high level saltus step be low level when, control logic input signal control
First order driver, to drive first order switching tube, the control terminal voltage of the first order switching tube is set to decline from supply voltage
To zero, so that the first order switching tube turns off；
While the control logic input signal controls first order driver, the control logic input signal is also entered
Enter first order time delay module, after the delay time of the first order time delay module, first order time delay module output the
One-level delay control signal, the first order delay control signal control second level driver, to drive second level switching tube, made
The control terminal voltage of the second level switching tube drops to zero from supply voltage, so that the second level switching tube turns off；
With this gradual control, while the n-th -2 grades delay control signals control (n-1)th grade of driver, described the
N-2 levels delay control signal is also into (n-1)th grade of time delay module, after the delay time of (n-1)th grade of time delay module, institute
State (n-1)th grade of time delay module and export (n-1)th grade of delay control signal, (n-1)th grade of delay control signal controls n-th grade of driving
Device, to drive n-th grade of switching tube, the control terminal voltage of n-th grade of switching tube is set to drop to zero from supply voltage, so that institute
N-th grade of switching tube shut-off is stated, completes the shut-off step by step of piece upper switch.
As described above, signal pin drive circuit on the piece upper switch gradual control circuit and method, piece of the present invention, has
Following beneficial effect：
The piece upper switch gradual control circuit of the present invention, using the switch tube module being made up of multiple-pole switch pipe, and is used
These switching tubes of the delay effect gradual control of time delay chain, current changing rate can be effectively reduced, and become equally reducing electric current
On the premise of rate, there is most short on or off process, switching speed is maximized.
Signal pin drive circuit on the piece of the present invention, using above-mentioned piece upper switch gradual control circuit, can make electricity
Rheology rate effectively reduces, while the speed for making electric current switch between signal pin and power line or ground wire is accelerated, so as to big
The big interference for reducing current switch to chip power supply line and ground wire.
The piece upper switch gradual control method of the present invention, passes through the method for on or off multiple-pole switch pipe step by step so that
The overall electric current passed through in switch tube module linearly rises or falls with the time, evenly effectively reduces curent change
Rate；Relative to the method for existing RC delay control switch, the time of switching process shortens dramatically；In the feelings of same switching speed
Under condition, the significantly more efficient interference reduced during high-current switch to chip power supply line and ground wire, chip is improved
Overall performance.
Brief description of the drawings
Fig. 1 is shown as the schematic diagram of signal pin drive circuit on present invention chip of the prior art.
Fig. 2 is shown as the schematic diagram of the present invention piece upper switch control circuit of the prior art using RC delays.
The switching tube that Fig. 3 is shown as in Fig. 2 signal that voltage x current changes over time everywhere during turn-on and turn-off
Figure.
Fig. 4 is shown as the schematic diagram of the piece upper switch gradual control circuit of first embodiment of the invention.
Fig. 5 is shown as switching tubes at different levels in the piece upper switch gradual control circuit of first embodiment of the invention and is turning on and closing
The schematic diagram that voltage x current changes over time everywhere during disconnected.
Fig. 6 is shown as the schematic diagram of driver in the piece upper switch gradual control circuit of first embodiment of the invention.
Fig. 7 is shown as the schematic diagram of time delay module in the piece upper switch gradual control circuit of first embodiment of the invention.
Fig. 8 is shown as the schematic diagram of signal pin drive circuit on the piece of second embodiment of the invention.
Fig. 9 is shown as the schematic flow sheet of the piece upper switch gradual control method of third embodiment of the invention.
Figure 10 is shown as Fig. 2 Simulation results schematic diagram.
Figure 11 is shown as Fig. 4 Simulation results schematic diagram.
Component label instructions
1 switch tube module
2 control terminal drive modules
3 time delay chains
MP p-type switching tubes
The drive module of PDRV p-type switching tubes
MN N type switch tubes
The drive module of NDRV N type switch tubes
VDD power lines/supply voltage
GND ground wires
Z is loaded
LVDD VDD pin parasitism self-inductions
LSIGNAL signal pin parasitism self-inductions
LGND GND pin parasitism self-inductions
M、M1~MnSwitching tube
G、G1~GnThe control terminal of switching tube
The drain electrode of D switching tubes
The source electrode of S switching tubes
VG、VG1~VGnThe control terminal voltage of switching tube
DRV、DRV1~DRVnDrive module
IN control logic input signals
ID flows into the total current of switching tube drain electrode
The fully on electric currents of ION
The cut-in voltage of VON switching tubes
TD1~TDn-1Time delay module
IN1~INn-1:Delay control signal
MP1~MP4 PMOS transistors
MN1~MN4 nmos pass transistors
S1~S3, S301~S303, S301 '~S303 ' steps
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Referring to Fig. 4, first embodiment of the invention is related to a kind of piece upper switch gradual control circuit.It should be noted that
Diagram provided in the present embodiment only illustrates the basic conception of the present invention in a schematic way, only display and the present invention in schema then
In relevant component rather than drawn according to component count, shape and the size during actual implement, each component during its actual implementation
Kenel, quantity and ratio can be a kind of random change, and its assembly layout kenel may also be increasingly complex.
The piece upper switch gradual control circuit of the present embodiment comprises at least：
Tube module 1 is switched, switch tube module 1 comprises at least the switching tube that n levels are connected in parallel.
Control terminal drive module 2, control terminal drive module 2 comprise at least n level drivers, the output end point of drivers at different levels
Control terminal not with switching tubes at different levels is connected, for driving switching tubes at different levels.
Time delay chain 3, time delay chain 3 comprise at least the time delay module that n-1 levels are connected in series, and wherein first order time delay module is defeated
The input for entering end and first order driver accesses a control logic input signal, and the output of (n-1)th grade of time delay module jointly
End is connected with the input of n-th grade of driver, for the delay time according to control logic input signal and time delay module at different levels
Gradual control driver, with driving switch pipe on or off step by step.
Wherein, n is the natural number more than or equal to 2.
In the present embodiment, time delay modules at different levels have an identical or different delay time, and time delay module at different levels prolongs
When the time be respectively less than drivers at different levels driving switching tubes at different levels control terminal voltage rise time or fall time.
In addition, switching tube M1~MnCan be any kind of switching tube for allowing hand over electric current, such as nmos pass transistor,
PMOS transistor or other transistors, and the size of each switching tube can be the same or different.In the present embodiment, switch
Pipe M1~MnIt is nmos pass transistor.
Please continue to refer to Fig. 4.Switch tube module 1 in the present embodiment, by switching tube of the prior art as shown in Figure 2
M is split as n small switching tube M1~Mn, and they are associated on current path, so as to form n level switching tubes.Accordingly, originally
Control terminal drive module 2 in embodiment, it is by the M of switching tube in the prior art as shown in Figure 2 DRV points of control terminal driver
With switching tube M1~MnCorresponding small driver DRV1~DRVn, so as to form n level drivers, for distinguishing driving switch pipe M1
~MnControl terminal G1~Gn.In addition, n-1 time delay module TD1~TDn-1A time delay chain 3 in series, so as to form n-1
Level time delay module；Control logic input signal IN had both accessed first order driver DRV1, first order time delay module TD is accessed again1；And
The delay control signal IN of time delay module outputs at different levels1~INn-1Both the input as next stage time delay module, is respectively coupled to again
Drive module DRV2~DRVnInputted as logic.
The operation principle of the present embodiment is as follows：
Referring to Fig. 5, when control logic input signal IN jumps to high level " 1 " from low level " 0 ", in time delay chain 3
Time delay module TD1~TDn-1The delay control signal IN of output1~INn-1, by its respective delay time td1~tdn-1Interval
Also high level " 1 " is jumped to from low level " 0 " step by step.Accordingly, drive module DRV1~DRVnAlso delay time td is pressed1~
tdn-1Interval allows its respective output voltage, namely switching tube M step by step1~MnControl terminal voltage VG1~VGnRisen to from 0V
Supply voltage VDD, so as to by switching tube M1~MnBy delay time td1~tdn-1Interval turns on one by one.Then tube module 1 is switched
In the overall electric current that passes through rise as the switching tube quantity increase of conducting is linear, until reaching fully on electric current ION.
Please continue to refer to Fig. 5, when control logic input signal IN jumps to low level " 0 " from high level " 1 ", time delay chain
Time delay module TD in 31~TDn-1The delay control signal IN of output1~INn-1, by its respective delay time td1~tdn-1
Interval also jumps to low level " 0 " from high level " 1 " step by step.Accordingly, drive module DRV1~DRVnAlso delay time td is pressed1
~tdn-1Interval allows its respective output voltage, namely switching tube M step by step1~MnControl terminal voltage VG1~VGnFrom supply voltage
VDD drops to 0V, so as to by switching tube M1~MnBy delay time td1~tdn-1Interval turns off one by one.Then tube module 1 is switched
The overall electric current passed through is linear as the switching tube quantity of conducting is reduced to be declined, and electric current 0 is complete switched off until reaching.
It is seen that, switch the overall electric current passed through in tube module 1 from the analysis of above turn-on and turn-off process and be proportional to
The switching tube quantity having been turned on, that is, it is proportional to the delay for the time delay chain 3 having already passed through.Enough, the time delay module in series n
TD1~TDn-1Delay time td1~tdn-1Respectively less than switching tube M1~MnControl terminal voltage VG1~VGnRise time or under
In the case of dropping the time, electric current ID waveforms are approximately increased straight line linearly over time, and current changing rate dI/dt approximations are smoothly
A lower value is maintained, has reached the purpose for effectively slowing down current changing rate.In addition, control terminal voltage VG1~VGnAll with
Electric current ID reaches ION (or 0) and the VDD that reaches home (or 0V), without there is extra prolong being delayed as RC in the prior art
When.So on the premise of equally current changing rate is reduced, the piece upper switch gradual control circuit of the present embodiment is with most short
On or off process, enables switching speed to maximize.
In addition, in the present embodiment, every grade of driver includes the CMOS inverter of two-stage series connection connection.As shown in fig. 6,
First order CMOS inverter is made up of the first PMOS transistor MP1 and the first nmos pass transistor MN1, second level CMOS inverter by
Second PMOS transistor MP2 and the second nmos pass transistor MN2 is formed, and the output of first order CMOS inverter is as second level CMOS
The input of phase inverter.Because the logic level for inputting first order CMOS is just the voltage VDD needed for switch controlled end, institute
Not need other logic level converting circuits.First PMOS transistor MP1, the first nmos pass transistor MN1, the 2nd PMOS crystal
When pipe MP2 and the second nmos pass transistor MN2 specific size need rise time or the decline according to switch controlled terminal voltage
Between requirement adjust.Certainly, in other examples, every grade of driver can also be adopted according to the difference of switching tube type
The equivalent drive circuit of driving function can be realized with other, rather than shall be limited only to the extent two-stage CMOS inverter.
In addition, in the present embodiment, every grade of time delay module includes the CMOS inverter of two-stage series connection connection, utilizes just
It is the gate delay of CMOS reversers.As shown in fig. 7, first order CMOS inverter is by the 3rd PMOS transistor MP3 and the 3rd
Nmos pass transistor MN3 is formed, and second level CMOS inverter is made up of the 4th PMOS transistor MP4 and the 4th nmos pass transistor MN4,
Input of the output of first order CMOS inverter as second level CMOS inverter.3rd PMOS transistor MP3, the 3rd NMOS are brilliant
Body pipe MN3, the 4th PMOS transistor MP4 and the 4th nmos pass transistor MN4 specific size are needed according to time delay module institutes at different levels
The delay time needed adjusts.Certainly, in other examples, every grade of time delay module can also be according to control terminal drive module
Logic level in 2 required for every grade of driver, and can provide the equivalent of low level " 0 " or high level " 1 " using other
Delay circuit, rather than shall be limited only to the extent two-stage CMOS inverter.
It is noted that each module involved in present embodiment is logic module, and in actual applications, one
Individual logic unit can be a part for a physical location or a physical location, can also be with multiple physics lists
The combination of member is realized.In addition, in order to protrude the innovative part of the present invention, will not be with solving institute of the present invention in present embodiment
The unit that the technical problem relation of proposition is less close introduces, but this is not intended that in present embodiment and other lists are not present
Member.
Referring to Fig. 8, second embodiment of the invention is related to signal pin drive circuit on a kind of piece, for driving load Z,
Wherein, signal pin drive circuit comprises at least on piece：Piece upper switch gradual control electricity involved by first embodiment of the invention
Road.It should be noted that the relevant technical details mentioned in first embodiment are still effective in the present embodiment, in order to reduce weight
It is multiple, repeat no more here.
In addition, signal pin drive circuit also includes on the piece of the present embodiment：Parasitic self-induction.One end of the parasitic self-induction with
Piece upper switch gradual control circuit involved by first embodiment is connected, the other end ground connection of the parasitic self-induction or power supply electricity
Pressure.Wherein, the other end of the parasitic self-induction is according to the type selecting of switching tube ground connection or supply voltage.
Specifically, if switching tube M1~MnIt is nmos pass transistor, the parasitic self-induction in the present embodiment is posted for GND pins
Sense LGND is born from, continuing with participation Fig. 8, on the piece involved by GND pin parasitism self-inductions LGND one end and first embodiment
Switch gradual control circuit is connected, GND pin parasitism self-inductions LGND other end ground connection GND.If switching tube M1~MnIt is
PMOS transistor, the parasitic self-induction in the present embodiment is VDD pin parasitism self-induction LVDD, VDD pin parasitism self-inductions LVDD's
One end is connected with the piece upper switch gradual control circuit involved by first embodiment, and VDD pin parasitism self-inductions LVDD's is another
Termination power voltage VDD.
Signal pin drive circuit on the piece of the present embodiment, using the piece upper switch gradual control involved by first embodiment
Circuit, current changing rate can be effectively reduced, while the speed for making electric current switch between signal pin and power line or ground wire
Degree is accelerated, so as to substantially reduce interference of the current switch to chip power supply line and ground wire.
Third embodiment of the invention is related to a kind of piece upper switch gradual control method, using involved by first embodiment of the invention
And piece upper switch gradual control circuit, idiographic flow is as shown in Figure 9.It should be noted that the phase mentioned in first embodiment
It is still effective in the present embodiment to close ins and outs, in order to reduce repetition, repeats no more here.
The piece upper switch gradual control method of the present embodiment comprises at least following steps：
Step S1, drivers at different levels are set, make the rising of the control terminal voltage of the switching tubes at different levels of driver drivings at different levels
Time or fall time meet demand.
Step S2, time delay modules at different levels are set, the delay time of time delay modules at different levels is respectively less than driver drivings at different levels
Switching tubes at different levels control terminal voltage rise time or fall time.
Step S3, according to control logic input signal and the delay time gradual control driver of time delay module at different levels, with
Driving switch pipe on or off step by step.
In the step S3 of the present embodiment, specific method is：
Step S301, control logic input signal from low transition be high level when, control logic input signal control
First order driver processed, to drive first order switching tube, the control terminal voltage of first order switching tube is set to be raised to power supply electricity from above freezing
Pressure, so that first order switching tube turns on.
Step S302, while control logic input signal controls first order driver, control logic input signal is also
Into first order time delay module, after the delay time of first order time delay module, the first order time delay module output first order is prolonged
When control signal, the first order delay control signal control second level driver, to drive second level switching tube, switch the second level
The control terminal voltage of pipe is raised to supply voltage from above freezing, so that second level switching tube turns on.
Step S303, with this gradual control, while the n-th -2 grades delay control signals control (n-1)th grade of driver, the
N-2 levels delay control signal is also into (n-1)th grade of time delay module, after the delay time of (n-1)th grade of time delay module, (n-1)th
Level time delay module exports (n-1)th grade of delay control signal, and (n-1)th grade of delay control signal controls n-th grade of driver, to drive the
N level switching tubes, the control terminal voltage of n-th grade of switching tube is set to be raised to supply voltage from above freezing, so that n-th grade of switching tube conducting,
Complete the conducting step by step of piece upper switch.
In the step S3 of the present embodiment, specific method can also be：
Step S303 ', control logic input signal from high level saltus step be low level when, control logic input signal control
First order driver processed, to drive first order switching tube, the control terminal voltage of first order switching tube is set to drop to from supply voltage
Zero, so that first order switching tube turns off.
Step S303 ', while control logic input signal controls first order driver, control logic input signal is also
Into first order time delay module, after the delay time of first order time delay module, the first order time delay module output first order is prolonged
When control signal, the first order delay control signal control second level driver, to drive second level switching tube, switch the second level
The control terminal voltage of pipe drops to zero from supply voltage, so that second level switching tube turns off.
Step S303 ', with this gradual control, while the n-th -2 grades delay control signals control (n-1)th grade of driver,
The n-th -2 grades delay control signals are also into (n-1)th grade of time delay module, after the delay time of (n-1)th grade of time delay module, n-th -
1 grade of time delay module exports (n-1)th grade of delay control signal, and (n-1)th grade of delay control signal controls n-th grade of driver, with driving
N-th grade of switching tube, the control terminal voltage of n-th grade of switching tube is set to drop to zero from supply voltage, so that n-th grade of switching tube closes
It is disconnected, complete the shut-off step by step of piece upper switch.
The piece upper switch control circuit of RC delays, and the present embodiment are utilized in the prior art to as shown in Figure 2 now
Used piece upper switch gradual control circuit, has carried out circuit simulation under the following conditions：N=20, supply voltage VDD=
2.5V, load Z=12.5 Ω, fully on electric current ION=100mA, GND pin parasitism self-inductions LGND=10nH.
Simulation result difference is as shown in Figure 10 and Figure 11.
Contrast both it is seen that, be equally the switching for completing 100mA electric currents, from control logic input signal IN in Figure 10
Level start saltus step, reach final stable state to control terminal G, required time is~15ns；And inputted in Figure 11 from control logic
Signal IN level starts saltus step, to control terminal G20Final stable state is reached, required time is~7.5ns, and the latter only has the former
50%.On the other hand, GND disturbance voltages peak value is~300mV on piece in Figure 10, and GND disturbance voltages peak value on piece in Figure 11
For~200mV, the latter also only has the former 66%.
As can be seen here, the piece upper switch gradual control method of the present embodiment, passes through on or off multiple-pole switch pipe step by step
Method so that switch tube module 1 in overall electric current linearly risen or fallen with the time, evenly effectively reduce electricity
Rheology rate；Relative to the method for existing RC delay control switch, the time of switching process shortens dramatically；In same switch speed
In the case of degree, the significantly more efficient interference reduced during high-current switch to chip power supply line and ground wire, improve
The overall performance of chip.
In summary, piece upper switch gradual control circuit of the invention, using the switch pipe die being made up of multiple-pole switch pipe
Block, and using these switching tubes of the delay effect gradual control of time delay chain, current changing rate can be effectively reduced, and equally subtracting
On the premise of low current rate of change, there is most short on or off process, switching speed is maximized.
Signal pin drive circuit on the piece of the present invention, using above-mentioned piece upper switch gradual control circuit, can make electricity
Rheology rate effectively reduces, while the speed for making electric current switch between signal pin and power line or ground wire is accelerated, so as to big
The big interference for reducing current switch to chip power supply line and ground wire.
The piece upper switch gradual control method of the present invention, passes through the method for on or off multiple-pole switch pipe step by step so that
The overall electric current passed through in switch tube module linearly rises or falls with the time, evenly effectively reduces curent change
Rate；Relative to the method for existing RC delay control switch, the time of switching process shortens dramatically；In the feelings of same switching speed
Under condition, the significantly more efficient interference reduced during high-current switch to chip power supply line and ground wire, chip is improved
Overall performance.So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (9)
1. a kind of piece upper switch gradual control circuit, it is characterised in that described upper switch gradual control circuit comprises at least：
Tube module is switched, the switch tube module comprises at least the switching tube that n levels are connected in parallel；
Control terminal drive module, the control terminal drive module comprise at least n level drivers, the output end difference of drivers at different levels
It is connected with the control terminal of switching tubes at different levels, for driving switching tubes at different levels；
Time delay chain, the time delay chain comprise at least the input of time delay module, wherein first order time delay module that n-1 levels are connected in series
The input of end and first order driver accesses a control logic input signal, and the output end of (n-1)th grade of time delay module jointly
It is connected with the input of n-th grade of driver, during for according to the delay of the control logic input signal and time delay module at different levels
Between driver described in gradual control, to drive the switching tube on or off step by step；
Wherein, n is the natural number more than or equal to 2；Time delay modules at different levels have identical or different delay time, and delay at different levels
When the delay time of module is respectively less than rise time or the decline of the control terminal voltage of the switching tubes at different levels of driver drivings at different levels
Between.
2. according to claim 1 upper switch gradual control circuit, it is characterised in that the switching tube is NMOS crystal
Pipe or PMOS transistor.
3. according to claim 1 upper switch gradual control circuit, it is characterised in that the driver comprises at least two
The CMOS inverter that level is connected in series.
4. according to claim 1 upper switch gradual control circuit, it is characterised in that the time delay module comprises at least
The CMOS inverter of two-stage series connection connection.
A kind of 5. signal pin drive circuit on piece, for driving load, it is characterised in that described upper signal pin driving electricity
Road comprises at least：
Piece upper switch gradual control circuit as described in claim any one of 1-4.
6. according to claim 5 upper signal pin drive circuit, it is characterised in that described upper signal pin driving
Circuit also includes：Parasitic self-induction；One end of the parasitic self-induction is connected with described upper switch gradual control circuit, the parasitism
The other end ground connection of self-induction or supply voltage.
A kind of 7. piece upper switch gradual control method, it is characterised in that described upper switch gradual control method uses such as right
It is required that the piece upper switch gradual control circuit described in any one of 1-4, it comprises at least following steps：
Drivers at different levels are set, when making rise time or the decline of the control terminal voltage of the switching tubes at different levels of driver drivings at different levels
Between meet demand；
Time delay modules at different levels are set, the delay time of time delay modules at different levels is respectively less than the switching tubes at different levels of driver drivings at different levels
Control terminal voltage rise time or fall time；
The driver according to the delay time gradual control of the control logic input signal and time delay module at different levels, with step by step
Drive the switching tube on or off.
8. according to claim 7 upper switch gradual control method, it is characterised in that inputted according to the control logic
Driver described in the delay time gradual control of signal and time delay module at different levels, to drive the switching tube to turn on step by step or close
Disconnected, specific method is：
The control logic input signal from low transition be high level when, control logic input signal control first
Level driver, to drive first order switching tube, makes the control terminal voltage of the first order switching tube be raised to supply voltage from above freezing,
So that the first order switching tube conducting；
While the control logic input signal controls first order driver, the control logic input signal is also into the
One-level time delay module, after the delay time of the first order time delay module, the first order time delay module exports the first order
Delay control signal, the first order delay control signal controls second level driver, to drive second level switching tube, makes described
The control terminal voltage of second level switching tube is raised to supply voltage from above freezing, so that the second level switching tube turns on；
With this gradual control, while the n-th -2 grades delay control signals control (n-1)th grade of driver, described the n-th -2 grades
Delay control signal is also into (n-1)th grade of time delay module, after the delay time of (n-1)th grade of time delay module, described
N-1 levels time delay module exports (n-1)th grade of delay control signal, and (n-1)th grade of delay control signal controls n-th grade of driver,
To drive n-th grade of switching tube, the control terminal voltage of n-th grade of switching tube is set to be raised to supply voltage from above freezing, so that described
N-th grade of switching tube conducting, completes the conducting step by step of piece upper switch.
9. according to claim 7 upper switch gradual control method, it is characterised in that inputted according to the control logic
Driver described in the delay time gradual control of signal and time delay module at different levels, to drive the switching tube to turn on step by step or close
Disconnected, specific method is：
The control logic input signal from high level saltus step be low level when, control logic input signal control first
Level driver, to drive first order switching tube, makes the control terminal voltage of the first order switching tube drop to zero from supply voltage,
So that the first order switching tube shut-off；
While the control logic input signal controls first order driver, the control logic input signal is also into the
One-level time delay module, after the delay time of the first order time delay module, the first order time delay module exports the first order
Delay control signal, the first order delay control signal controls second level driver, to drive second level switching tube, makes described
The control terminal voltage of second level switching tube drops to zero from supply voltage, so that the second level switching tube turns off；
With this gradual control, while the n-th -2 grades delay control signals control (n-1)th grade of driver, described the n-th -2 grades
Delay control signal is also into (n-1)th grade of time delay module, after the delay time of (n-1)th grade of time delay module, described
N-1 levels time delay module exports (n-1)th grade of delay control signal, and (n-1)th grade of delay control signal controls n-th grade of driver,
To drive n-th grade of switching tube, the control terminal voltage of n-th grade of switching tube is set to drop to zero from supply voltage, so that described
N-th grade of switching tube shut-off, completes the shut-off step by step of piece upper switch.
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| CN108880272A (en) * | 2018-08-24 | 2018-11-23 | 广州致远电子有限公司 | A kind of push-pull converter circuit and its control method |
| CN108880271A (en) * | 2018-08-24 | 2018-11-23 | 广州致远电子有限公司 | A kind of push-pull converter circuit and its control method |
| CN109067164A (en) * | 2018-08-24 | 2018-12-21 | 广州致远电子有限公司 | A kind of push-pull converter circuit and its control method |
| CN108923662A (en) * | 2018-08-24 | 2018-11-30 | 广州致远电子有限公司 | A kind of push-pull converter circuit and its control method |
| CN109613848B (en) * | 2018-10-26 | 2021-04-09 | 中国船舶重工集团公司第七0九研究所 | Multichannel high-speed signal switching system and control method |
| WO2020186471A1 (en) * | 2019-03-20 | 2020-09-24 | 华为技术有限公司 | Delay circuit and drive device |
| CN113037253A (en) * | 2021-02-25 | 2021-06-25 | 中国电子科技集团公司第五十八研究所 | Open drain output circuit |
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Address after: Zhangjiang Building 20A, 289 Chunxiao Road, China (Shanghai) Free Trade Pilot Area, Pudong New Area, Shanghai Co-patentee after: VeriSilicon Microelectronics (Beijing) Co., Ltd. Patentee after: Xinyuan Microelectronics (Shanghai) Co., Ltd. Co-patentee after: VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD. Co-patentee after: Core holdings limited company Address before: 201203 Zhangjiang Building 20A, 560 Songtao Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai Co-patentee before: VeriSilicon Microelectronics (Beijing) Co., Ltd. Patentee before: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Co-patentee before: VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD. Co-patentee before: VeriSilicon Holdings Co., Ltd. |
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