CN101142730A - Driver circuit and method with reduced di/dt and having delay compensation - Google Patents
Driver circuit and method with reduced di/dt and having delay compensation Download PDFInfo
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- CN101142730A CN101142730A CNA2005800435017A CN200580043501A CN101142730A CN 101142730 A CN101142730 A CN 101142730A CN A2005800435017 A CNA2005800435017 A CN A2005800435017A CN 200580043501 A CN200580043501 A CN 200580043501A CN 101142730 A CN101142730 A CN 101142730A
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Abstract
A method of driving a power transistor switch comprising: receiving a drive input signal; converting the drive input signal into a converted drive input signal; and providing the converted gate drive input signal to a control electrode of the switch to turn on the switch, the converted drive input signal having three regions with respect to time, each having a slope, a first region in time having a first slope up to a Miller Plateau of the switch; a second region in time having a second slope with a reduced slope compared with the first slope; and a third region having a third slope that is greater than the second slope, whereby the control electrode voltage rapidly reaches the Miller Plateau voltage, then more slowly reaches a threshold voltage of the switch and then, when the switch has substantially fully turned on, the control electrode voltage is rapidly increased. The switch delay time is also maintained substantially constant by adjusting the transistor control electrode precharge voltage.
Description
The cross reference of related application
The application requires application on November 5th, 2004, name is called the U.S. Provisional Patent Application 60/625 of " DRIVER CIRCUIT WITHREDUCED DI/DT AND HAVING DELAY COMPENSATION ", 214 rights and interests and priority, its whole disclosure is incorporated into this as quoting.
Background technology
The present invention relates to drive circuit, especially, relate to current changing rate (dI/dt) that reduces in the switching process and the drive circuit that therefore reduces EMI (electromagnetic interference).Simultaneously, the objective of the invention is to have big dv/dt, promptly big voltage change ratio is to reduce dissipation and switching loss.In addition, the object of the present invention is to provide a kind of passing through to adjust the grid pre-charge voltage, have the drive circuit of delay compensation.
Summary of the invention
According to the present invention, a kind of drive circuit is provided, this drive circuit is implemented the gate driving of three slopes to the power switch of for example power MOSFET.Especially, the present invention includes a kind of method of driving power transistor switch, this method comprises the reception drive input signal; This drive input signal is changed into the gate drive input signal of conversion; And provide the drive input signal of this conversion to the control electrode of described switch, so that make this switch conduction, the drive input signal of this conversion has three zones with time correlation, each zone has a slope, and the first area of time has first slope until this switch Miller plateau; Second region in time has second slope, and this second slope comprises the slope that reduces than first slope; And has the 3rd zone greater than the 3rd slope of second slope, thus, control electrode voltage promptly reaches Miller plateau voltage, reaches the threshold voltage of switch then more lentamente, when this switch basically fully during conducting, control electrode voltage promptly increases then.
According on the other hand, the pre-charge voltage of described switch is automatically adjusted, so that when this switch of conducting, and the control lag time, thus make to keep constant basically time of delay.
Description of drawings
The present invention will be described in more detail by following detailed description with reference to accompanying drawing, wherein:
Fig. 1 shows the power switch circuit that drives load;
Fig. 2 A, 2B show the waveform relevant with the circuit of Fig. 1 with 2C;
Fig. 3 shows a kind of execution mode of three slope gate driver circuit;
Fig. 4 shows the basic waveform of three slope gate driver circuit;
Fig. 5 shows the effect that changes threshold voltage with constant current load and constant voltage source;
Fig. 6 shows the influence of load current variation to time of delay;
Fig. 7 shows the waveform of being realized by embodiments of the invention, wherein comes the control lag time by closed-loop control;
Fig. 8 shows the circuit execution mode of the control lag time according to the present invention; And
Fig. 9 comprises Fig. 9 A and 9B, shows the waveform of circuit among Fig. 8;
Figure 10 shows the execution mode of circuit under single drive integrated circult among Fig. 8; And
Figure 11 comprises Figure 11 A and 11B, shows time of delay along with variations in threshold voltage.
Embodiment
According to the present invention, a kind of drive circuit is provided, this drive circuit is implemented the gate driving of three slopes to the power switch of for example power MOSFET.Fig. 1 shows the power switch circuit that drives load, and this loading liquifier is shown inductive load L.For example, this switching circuit can be transducer output circuit or motor driver.According to the present invention, power switch 10 is by the signal conducting with three zoness of different.In the initial gate drive process of power switch transistor shown in Figure 1 10, the grid of switching transistor 10 as shown in Figure 2, provides grid voltage (zone 1), and this grid voltage promptly rises, up to reaching Miller plateau M.Referring to Fig. 2 A.This is the necessary condition that prevents excessive deferral.In case reach Miller plateau M, this Miller plateau M is usually less than the threshold voltage vt h (Fig. 2 A) of switching transistor, applies the second milder grid voltage of rate of change in zone 2, to reduce dI/dt and EMI.At last, when free wheeling diode 20, as shown in Figure 1, during stop conducting, in zone 3, grid voltage increases sharply with high voltage conversion rate.Shown in Fig. 2 A.Grid voltage reaches its maximum grid voltage afterwards, for example, typically is 5 volts.Although show diode 20, this diode can be a synchronous transistor switch.
Three slope gate drive according to the present invention have the effect that reduces dI/dt, therefore reduce the EMI emission, improve dv/dt simultaneously, dissipate and power dissipation to reduce.
In the cutting-off process of this power switch, shown in the right hand portion of Fig. 2 A, this operation is reversed.Promptly at first going up at descent direction (zone 4) and carry out the quick voltage rate of change, then is milder rate of change (zone 5), until reaching Miller plateau, is rate of change (zone 6) faster afterwards.
Fig. 2 B shows electric current in the diode 20 (I diode) and the electric current (IMOS) in the switch 10.Fig. 2 C shows the source voltage Vout with respect to ground voltage, and expression is when diode 20 conductings, and this voltage is about-6 volts.Work as diode ceases conducting, during the complete conducting of switch 10, gate driving is in the 3rd zone 3.When grid voltage promptly increases, diode ceases conducting, and the voltage at source electrode or diode two ends reaches the VCC level, is shown schematically as 14 volts.In the right hand portion of Fig. 2 C, show in cutting-off process the waveform at diode two ends or source voltage.
Fig. 3 shows a kind of execution mode of three slope gate driver circuit.The output voltage V out at load two ends is fed to the grid of transistor 30.
In prime area 1, before reaching Miller plateau, switching transistor 10 is driven hastily, to obtain high dv/dt.These can be realized by utilizing grid voltage desired value Vgs driving transistors 10.
Voltage is when the source-6 volts the time, diode current flow.When diode 20 conductings, output transistor 10 not conductings.Therefore switch 30 disconnects, and high logical signal is provided for operational amplifier 40, makes its remain off, and thus, switch 10 can not driven hastily.During this period, operational amplifier 50 Be Controlled conductings, and the grid by resistor R 2 driving transistorss 10.After arriving Miller plateau, and at diode 20 still conduction period, these provide gate driving mild in the zone 2, low slope.
When the 10 complete conductings of beginning of diode ceases conducting and switch and when driving load, output voltage increases, shown in Fig. 2 C.This will make switch 30 complete conductings, reduce the voltage at resistor R two ends and make the drain electrode of transistor 30 be similar to ground connection.This will control operational amplifier 40, cause this output driving transistors 10 conducting sharp, realize the 3rd slope district 3 in the grid voltage thus.
In another embodiment of the present invention, utilize closed control circuit self-adjusting grid pre-charge voltage, in order to the compensation on-delay.Fig. 4 shows previously described basic waveform.In original area 1, grid is charged to the pre-charge voltage V Prech on the grid rapidly.In zone 2, grid is with constant current charge.In zone 3, Vgs reaches MOSFET threshold voltage vt h.To zone 4, grid is still with constant current charge from zone 3, and therefore the electric current I MOS by switch 10 increases.Referring to Fig. 4 C, in the stage 4, IMOS reaches load current value I load.Vds is detected and begins to reduce, and by the Vgs that increases sharply, makes grid current be increased to high value 5.
Fig. 5 illustrates and keeps I load and VCC constant, changes the effect of Vth.Grid in time quick charge to fixed voltage Vprech.Problem is if the threshold voltage vt h of switch 10 changes owing to processing variation or variations in temperature, and switch conduction point and IMOS begin rising point and will move to 2 to 3 from waveform 1 so, and as shown in Figure 5, Vth is depended in the position of moving.Because grid is with constant current charge, as shown in the figure, this causes very large Tdon (turn on delay time) to change.If Vth is higher, Vprech fixes as if this moment, will spend to reach Vth for more time, thereby cause longer time of delay.
Similarly, change, also will change significantly time of delay so if Fig. 6 illustrates load current.
Fig. 7 shows the waveform of being realized by embodiments of the invention, and wherein the closed-loop control by Vprech is to controlling time of delay.
In this embodiment, provide input control voltage IN to drive circuit.The output of drive circuit is Vgs, and three slope drive are (Fig. 7 (b)) as described previously.Draining to the voltage (Vds) and the time delay Tdon (Fig. 7 (d)) of source electrode of bridge switch 10 has been shown in Fig. 7 (c).Fig. 7 (d) is depicted as the tdon desired value of expectation.
Fig. 8 illustrates the circuit execution mode that is used to obtain the target delay time.In this embodiment, logical circuit 60 is used for monitoring output voltage.As mentioned above, square frame 50 is drive circuits of realizing three slope drive.Shown in Fig. 7 (d), in order to realize this control, for example, at the rising edge triggering monostable multivibrator MV (Fig. 8) of input voltage IN.Produce the logic signal image OUT of Vout by trigger equipment T (Fig. 8), and compare with the monostable output of grid 61 and 62.If the conducting of Vout is longer, Vprech increases so, and if the conducting of Vout shorter, Vprech reduces so.Described thus system is self-adjusting pre-charge voltage Vprech, so that no matter how other parameters of described process and described switch change, all can provide fixing tdon.
As shown in Figure 9, if time of delay is long, logical circuit 60 will be by gate 61 by delay input signal IN so
*Produce signal IN with the counter-rotating of output signal OUT
*AND OUTNOT.This will make the voltage Vprech at capacitor C two ends increase, and shown in Fig. 9 A, because can reach threshold voltage vt h quickly from higher pre-charge voltage, reduce time of delay thus.
On the contrary, shown in Fig. 9 B, should be very short time of delay, and Vprech reduces.In the case, comprise OUT AND IN
*The output of the logical circuit of the logical combination of NOT (by grid 62) causes Vprech to reduce, and increases time of delay thus to desired value.
Figure 10 shows the execution mode of circuit shown in Fig. 8 of single drive integrated circult.Closed loop is to identical among the charging of capacitor C and charging method and Fig. 8.
Figure 11 A shows and generally postpones the variation of tdon with Vth.Pass through to use this circuit according to the present invention, and adjust Vprech, it is constant that tdon can keep, shown in Figure 11 B.
Therefore, circuit of the present invention reduces dI/dt, so that reduce EMI, still has enough dv/dt, so that switching loss is minimized.This circuit is also by adjusting the on-delay of grid pre-charge voltage compensation threshold voltage variation.
Although the present invention is described by relative specific embodiment, for a person skilled in the art, many changes and improvements and other application will become apparent.Therefore, the present invention should not limited by concrete disclosing herein, but is only limited by accessory claim.
Claims (20)
1. the method for a driving power transistor switch, this method comprises:
Receive drive input signal;
Described drive input signal is changed into the drive input signal of conversion; And
The gate drive input signal of described conversion is offered the control electrode of described switch, so that this switch conduction, the drive input signal of described conversion has three zones with time correlation, each zone has a slope, and the first area of time has first slope until the Miller plateau of described switch; Second region in time has with described first slope compares second slope that reduces; And the 3rd the zone have the 3rd slope greater than described second slope, thus, control electrode voltage promptly reaches described Miller plateau voltage, reach the threshold voltage of described switch then more lentamente, then, when the basic conducting fully of described switch, described control electrode voltage promptly increases.
2. the method for claim 1, this method further comprises the pre-charge voltage on the control electrode of adjusting described switch, with from described drive input signal begin to described switch basic conducting fully during this period of time in keep time of delay of expecting.
3. the method for claim 1, this method further comprises provides first drive circuit, and this first drive circuit provides the drive signal of the control electrode with a slope;
Second drive circuit is provided, and this second drive circuit provides the control electrode drive signal with a slope that increases;
In described first area, drive described switch with described drive input signal;
Detection is from the output voltage of this switch; And when output voltage is in first level, drive this switch with described first drive circuit; And when described output voltage is in second level, drive this switch with described second drive circuit.
4. method as claimed in claim 2, this method further comprises:
Receive described drive input signal;
The beginning of this drive input signal and output signal from described switch are compared, and determine the beginning of this drive input signal and the time delay between the described output signal; And
Adjust the pre-charge voltage on the described switch, if so that should time of delay greater than time of delay of expectation, then increase this pre-charge voltage, if should time of delay less than time of delay of described expectation, then reduce this pre-charge voltage.
5. the method for claim 1, this method further comprises, when described switch is cut off in hope, the drive input signal of described conversion is provided, so that provide chronologically have the 4th slope, the shutoff signal of the 5th slope and the 6th slope, the 5th slope reduces with respect to described the 4th slope, and described the 6th slope increases with respect to described the 5th slope.
6. the method for claim 1, the drive input signal of wherein said conversion has reduced EMI.
7. the method for claim 1, the drive input signal of wherein said conversion has reduced switching loss.
8. method as claimed in claim 2, wherein said switch is MOSFET, and the step of the described pre-charge voltage of described adjustment comprises the voltage on the grid capacitance of adjusting described switch.
9. beginning and the basic method that obtains the time of delay of expectation fully between the conducting state of described switch in a drive input signal that drives semiconductor switch, this method comprises:
Adjust the pre-charge voltage on the control electrode of described switch, to keep the time of delay of described expectation.
10. method as claimed in claim 9, this method further comprises:
Receive described drive input signal;
When the basic conducting fully of described switch, the beginning of described drive input signal is compared with the output signal from described switch, and the beginning of definite described drive input signal and the time delay between the described output signal; And
Adjust the pre-charge voltage on the described switch, if so that greater than the time of delay of described expectation, then increase described pre-charge voltage described time of delay, and if described time of delay less than the time of delay of described expectation, then reduce described pre-charge voltage.
11. a circuit that is used for the driving power transistor switch, this circuit comprises:
Receive the circuit of drive input signal;
Described drive input signal is changed into the circuit of conversion driving input signal; And wherein
The gate drive input signal of this conversion is offered the control electrode of described switch, so that this switch conduction, the drive input signal of this conversion has three zones with time correlation, each zone has a slope, and the first area of time has first slope until the Miller plateau of this switch; Second region in time has with described first slope compares second slope that reduces; And the 3rd the zone have the 3rd slope greater than described second slope, thus, described control electrode voltage promptly reaches described Miller plateau voltage, reach the threshold voltage of this switch then more lentamente, when this switch basically fully during conducting, described control electrode voltage promptly increases then.
12. circuit as claimed in claim 11, this circuit further comprises the circuit of the pre-charge voltage on the control electrode that is used to adjust this switch, with from described drive input signal begin to described switch basic conducting fully during this period of time in, keep time of delay of expectation.
13. circuit as claimed in claim 11, this circuit further comprise first drive circuit that the control electrode drive signal with a slope is provided; Second drive circuit of the control electrode drive signal of the slope with increase is provided;
In described first area, come switch driven with described drive input signal; And
Detection is from the detector of the output voltage of this switch; And when this output voltage is in first level, drive this switch with described first drive circuit; And when this output voltage is in second level, drive this switch with described second drive circuit.
14. circuit as claimed in claim 12, this circuit further comprises:
Be used for the beginning of described drive input signal is compared with the output signal from this switch, and determine the beginning of described drive input signal and the circuit of the time delay between the described output signal; And
Be used to adjust the pre-charge voltage on the described switch, so that if described time of delay is greater than the time of delay of described expectation, then increase described pre-charge voltage, if less than the time of delay of described expectation, then reduce the circuit of described pre-charge voltage described time of delay.
15. circuit as claimed in claim 11, wherein this circuit is when operation, cut off described switch by the drive input signal that described conversion is provided, so that provide chronologically have the 4th slope, the shutoff signal of the 5th slope and the 6th slope, described the 5th slope reduces with respect to described the 4th slope, and described the 6th slope increases with respect to described the 5th slope.
16. circuit as claimed in claim 11, the drive input signal of wherein said conversion has reduced EMI.
17. circuit as claimed in claim 11, the drive input signal of wherein said conversion has reduced switching loss.
18. circuit as claimed in claim 12, wherein said switch is MOSFET, and the circuit that is used to adjust described pre-charge voltage comprises the circuit of the voltage on the grid capacitance that is used to adjust described switch.
19. a circuit that obtains time of delay of expecting the beginning of the drive input signal that drives semiconductor switch and described switch basic fully between the conducting state, this circuit comprises:
Be used to adjust the pre-charge voltage on the control electrode of described switch, with the circuit of time of delay of keeping expectation.
20. circuit as claimed in claim 19, this circuit further comprises:
Be used for when the basic conducting fully of described switch, the beginning of described drive input signal being compared with the output signal from this switch, and the beginning of definite described drive input signal and the circuit of the time delay between the described output signal; And
Be used to adjust the pre-charge voltage on the described switch, so that if described time of delay is greater than the time of delay of described expectation, then increase described pre-charge voltage, and if should time of delay less than time of delay of described expectation, then reduce the circuit of described pre-charge voltage.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US62521404P | 2004-11-05 | 2004-11-05 | |
| US60/625,214 | 2004-11-05 | ||
| US11/264,970 | 2005-11-02 |
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| Publication Number | Publication Date |
|---|---|
| CN101142730A true CN101142730A (en) | 2008-03-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005800435017A Pending CN101142730A (en) | 2004-11-05 | 2005-11-03 | Driver circuit and method with reduced di/dt and having delay compensation |
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| CN (1) | CN101142730A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104467769A (en) * | 2014-12-10 | 2015-03-25 | 芯原微电子(上海)有限公司 | On-chip switch step-by-step control circuit and method and on-chip signal pin drive circuit |
| WO2015067202A3 (en) * | 2013-11-07 | 2015-09-24 | Huawei Technologies Co., Ltd. | Startup method and system for resonant converters |
| CN105610304A (en) * | 2014-11-14 | 2016-05-25 | 基思利仪器公司 | Low noise power supply MOSFET gate drive scheme |
| CN105656311A (en) * | 2014-11-11 | 2016-06-08 | 产晶积体电路股份有限公司 | Power control device with dynamic driving ability regulation function |
| CN107947123A (en) * | 2017-10-24 | 2018-04-20 | 深圳市必易微电子有限公司 | ACDC protective circuit of switch power source and ACDC switching power units |
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2005
- 2005-11-03 CN CNA2005800435017A patent/CN101142730A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015067202A3 (en) * | 2013-11-07 | 2015-09-24 | Huawei Technologies Co., Ltd. | Startup method and system for resonant converters |
| US9350260B2 (en) | 2013-11-07 | 2016-05-24 | Futurewei Technologies, Inc. | Startup method and system for resonant converters |
| CN105656311A (en) * | 2014-11-11 | 2016-06-08 | 产晶积体电路股份有限公司 | Power control device with dynamic driving ability regulation function |
| CN105656311B (en) * | 2014-11-11 | 2018-11-13 | 产晶积体电路股份有限公司 | The power control of dynamic driving capacity adjustment |
| CN105610304A (en) * | 2014-11-14 | 2016-05-25 | 基思利仪器公司 | Low noise power supply MOSFET gate drive scheme |
| CN105610304B (en) * | 2014-11-14 | 2019-11-19 | 基思利仪器公司 | Low noise power supply MOSFET gate driving scheme |
| CN104467769A (en) * | 2014-12-10 | 2015-03-25 | 芯原微电子(上海)有限公司 | On-chip switch step-by-step control circuit and method and on-chip signal pin drive circuit |
| CN104467769B (en) * | 2014-12-10 | 2017-12-26 | 芯原微电子(上海)有限公司 | Signal pin drive circuit on piece upper switch gradual control circuit and method, piece |
| CN107947123A (en) * | 2017-10-24 | 2018-04-20 | 深圳市必易微电子有限公司 | ACDC protective circuit of switch power source and ACDC switching power units |
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