CN104465772A - High-efficiency radio frequency LDMOS device and manufacturing method thereof - Google Patents
High-efficiency radio frequency LDMOS device and manufacturing method thereof Download PDFInfo
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- CN104465772A CN104465772A CN201410628269.4A CN201410628269A CN104465772A CN 104465772 A CN104465772 A CN 104465772A CN 201410628269 A CN201410628269 A CN 201410628269A CN 104465772 A CN104465772 A CN 104465772A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 132
- 239000002184 metal Substances 0.000 claims abstract description 132
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 69
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 229920005591 polysilicon Polymers 0.000 claims description 43
- 238000002347 injection Methods 0.000 claims description 33
- 239000007924 injection Substances 0.000 claims description 33
- 238000005468 ion implantation Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 238000001259 photo etching Methods 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 15
- 238000005516 engineering process Methods 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000000605 extraction Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 19
- 238000013461 design Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H01L29/7816—
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- H01L29/41725—
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- H01L29/66681—
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a radio frequency LDMOS device. The radio frequency LDMOS device comprises a heavily-doped drain electrode. The heavily-doped drain electrode is provided with a drain electrode metal electrode. The bottom of the drain electrode metal electrode makes contact with the heavily-doped drain electrode, and the heavily-doped drain electrode is electrically led out. The invention further discloses a manufacturing method of the radio frequency LDMOS device. In the radio frequency LDMOS device, no drain electrode metal silicide is formed in the heavily-doped drain electrode any more, so that the upper surface of the heavily-doped drain electrode is lifted, and silicon in the heavily-doped drain electrode is not consumed basically. The thickness of grid electrode metal silicide can be increased as much as possible so as to reduce grid resistance, the function of a drain end region is not affected, leakage currents generated in the RFLDMOS reverse breakdown process are reduced, and stability of breakdown voltages is guaranteed. In the radio frequency LDMOS device, no drain electrode metal silicide is formed in the heavily-doped drain electrode any more, the width of the heavily-doped drain electrode can be reduced, source and drain capacitance Cds is reduced, and efficiency and non-linearity of the device are improved.
Description
Technical field
The application relates to a kind of semiconductor device, particularly relates to LDMOS (Lateral Diffused MetalOxide Semiconductor, Laterally Diffused Metal Oxide Semiconductor) device.
Background technology
RF power device is the Power semiconductor products of new generation that semiconductor microelectronic integrated circuit technique and microwave electron technological incorporation are got up, so that its linearity is good, gain is high, the advantage of the aspect such as withstand voltage height, power output are large, Heat stability is good, efficiency are high, Broadband Matching performance is good, become the power device of most competitiveness of communication base station, radar application.In order to meet the standard that the applications such as communication base station improve constantly, the requirement of radio frequency LDMOS device to efficiency and the linearity is also more and more higher,
Refer to Fig. 1, this is a kind of cross-sectional view of existing radio frequency LDMOS device.P-type silicon substrate 1 has p-type epitaxial layer 2.The p-type epitaxial layer 2 of part has gate oxide 3.Only come out in the position of source metal silicide 11b, drain metal silicide 11c, substrate metal electrode 15d by gate oxide 3.The gate oxide 3 of part has polysilicon gate 4.There is in the p-type epitaxial layer 2 of polysilicon gate 4 one side-lower N-shaped light dope injection region 6, in the epitaxial loayer 2 below polysilicon gate 4 opposite side, there is p-type channel region 7.There is N-shaped heavy doping drain electrode 8c in N-shaped light dope injection region 6.There is the adjacent N-shaped heavy doping source electrode 8b in side and p-type heavy doping injection region 9 in p-type channel region 7.The gate oxide 3 of part has silicide barrier layer 10.Silicide barrier layer 10 forms sidewall structure in the both sides of polysilicon gate 4, but exposes the position of metal silicide 11a, 11b, 11c and substrate metal electrode 15d.Polysilicon gate 4 has gate metal silicide 11a.The N-shaped heavy doping source electrode 8b of part and the p-type heavy doping injection region 9 of part has source metal silicide 11b.The N-shaped heavy-doped source drain electrode 8c of part has drain metal silicide 11c.Whole radio frequency LDMOS device all cover by before-metal medium layer 12.Source metal electrode 15b runs through before-metal medium layer 12, and bottom is in the upper surface of source metal silicide 11b or inside.Drain metal electrode 15c runs through before-metal medium layer 12, and bottom is in the upper surface of drain metal silicide 11c or inside.Substrate metal electrode 15d runs through before-metal medium layer 12, silicide barrier layer 10, gate oxide 3, p-type heavy doping injection region 9, p-type channel region 7, p-type epitaxial layer 2, and bottom is in the upper surface of p-type silicon substrate 1 or inside.
In radio frequency LDMOS device shown in Fig. 1, in order to obtain less resistance, need the thickness increasing gate metal silicide 11a.But source metal silicide 11b and drain metal silicide 11c and gate metal silicide 11a is deposit simultaneously and high annealing to be formed, as increased the thickness of gate metal silicide 11a, also will certainly will increase the thickness of source metal silicide 11b and drain metal silicide 11c simultaneously.Once the thickness of source metal silicide 11b and drain metal silicide 11c is excessive, the silicon (metal silicide is at high temperature reacted by metal and silicon and formed) of N-shaped heavy doping source electrode 8b and N-shaped heavy doping drain electrode 8c will be consumed in a large number.This has larger leakage current by causing during radio frequency LDMOS reverse breakdown, and puncture voltage is also stable not, thus causes the reduction of device reliability.
Refer to Fig. 2, this is the design layout of the part-structure of the radio frequency LDMOS device shown in Fig. 1.Just Fig. 1 is correspond to along the cross-section structure in A-A direction in Fig. 2.In Fig. 2, the design configuration of p-type channel region 7 can partly overlap with polysilicon gate 4, when forming the ion implantation of p-type channel region 7, lap is subject to the stop of polysilicon gate 4, and during annealing after ion implantation, the final graphics of p-type channel region 7 can partly overlap with polysilicon gate 4.Similarly, the design configuration of N-shaped heavy doping source electrode 8b can partly overlap with polysilicon gate 4 and with source metal electrode 15b zero lap, when forming the ion implantation of N-shaped heavy doping source electrode 8b, lap is subject to the stop of polysilicon gate 4, and during annealing after ion implantation, the final graphics of N-shaped heavy doping source electrode 8b can partly overlap with polysilicon gate 4 and partly overlap with source metal electrode 15b.In the drain-end region of the radio frequency LDMOS device shown in Fig. 1, the layout area of the layout area ﹤ N-shaped heavy doping drain electrode 8c of the layout area ﹤ drain metal silicide 11c of drain metal electrode 15c.Once the thickness of drain metal silicide 11c is excessive, owing to being subject to drain the restriction of alignment rule of 8c with the alignment of the drain metal electrode 15c of inner side rule and with the N-shaped heavy doping in outside, determining the drain width d of 8c of N-shaped heavy doping cannot reduce.This just makes source drain capacitance C
dscomparatively large, thus cause the efficiency of device and nonlinearity to reduce.
Summary of the invention
Technical problems to be solved in this application are to provide a kind of radio frequency LDMOS device, have higher efficiency.For this reason, the application also will provide the manufacture method of described radio frequency LDMOS device.
For solving the problems of the technologies described above, the application's high efficiency radio frequency LDMOS device comprises heavy doping drain electrode, and heavy doping drain electrode has drain metal electrode; Bottom and the heavy doping of described drain metal electrode drain to contact and heavy doping drained and electrically draw.
The manufacture method of the application's high efficiency radio frequency LDMOS device is included in heavy doping drain electrode and forms drain metal electrode, and directly heavy doping drain electrode is electrically drawn by drain metal electrode.
In the application's high efficiency radio frequency LDMOS device, in heavy doping drain electrode, no longer form drain metal silicide, therefore do not consume the silicon of heavy doping drain electrode, the upper surface of heavy doping drain electrode raised by relatively existing device.So just, can increase the thickness of gate metal silicide to reduce resistance as far as possible, and can not affect the function of drain-end region, leakage current when can reduce radio frequency LDMOS reverse breakdown also guarantees stable breakdown voltage.
In the application's high efficiency radio frequency LDMOS device, in heavy doping drain electrode, no longer form drain metal silicide, therefore change three of existing device layers of nested structure into two-layer nested structure.This can reduce the width of heavy doping drain electrode, thus reduces source drain capacitance C
ds, improve efficiency and the nonlinearity of device.
Accompanying drawing explanation
Fig. 1 is a kind of cross-sectional view of existing radio frequency LDMOS device;
Fig. 2 is the domain schematic diagram of part-structure in the radio frequency LDMOS device shown in Fig. 1;
Fig. 3 is the cross-sectional view of the high efficiency radio frequency LDMOS device of the application;
Fig. 4 is the domain schematic diagram of part-structure in the radio frequency LDMOS device shown in Fig. 3;
Fig. 5 is the peak efficiency of radio frequency LDMOS device and the relation curve (under different operating frequency) of operating voltage;
Fig. 6 is the simple equivalent circuit figure of radio frequency LDMOS device;
Fig. 7 a to Fig. 7 k is each step schematic diagram of the manufacture method of the high efficiency radio frequency LDMOS device of the application.
Description of reference numerals in figure:
1 is p-type heavily doped silicon substrate; 2 is p-type light dope epitaxial loayer; 3 is gate oxide; 4 is polysilicon gate; 5 is photoresist; 6 is N-shaped light dope injection region; 7 is p-type channel region; 8b is N-shaped heavy doping source electrode; 8c is N-shaped heavy doping drain electrode; 9 is p-type heavy doping injection region; 10 is silicide barrier layer; 11a is gate metal silicide; 11b is source metal silicide; 11c is drain metal silicide; 12 is before-metal medium layer; 13 is sunk type through hole; 14b is source contact openings; 14c is drain contact hole; 15b is source metal electrode; 15c is drain metal electrode; 15d is substrate metal electrode.
Embodiment
Refer to Fig. 3, this is the cross-sectional view of the radio frequency LDMOS device of the application.P-type silicon substrate 1 has p-type epitaxial layer 2.The p-type epitaxial layer 2 of part has gate oxide 3.Only come out in the position of source metal silicide 11b, drain metal electrode 15c, substrate metal electrode 15d by gate oxide 3.The gate oxide 3 of part has polysilicon gate 4.There is in the p-type epitaxial layer 2 of polysilicon gate 4 one side-lower N-shaped light dope injection region 6, in the epitaxial loayer 2 below polysilicon gate 4 opposite side, there is p-type channel region 7.There is N-shaped heavy doping drain electrode 8c in N-shaped light dope injection region 6.There is the adjacent N-shaped heavy doping source electrode 8b in side and p-type heavy doping injection region 9 in p-type channel region 7.The gate oxide 3 of part has silicide barrier layer 10.Silicide barrier layer 10 forms sidewall structure in the both sides of polysilicon gate 4, but exposes the position of source metal silicide 11b, drain metal electrode 15c and substrate metal electrode 15d.Polysilicon gate 4 has gate metal silicide 11a.The N-shaped heavy doping source electrode 8b of part and the p-type heavy doping injection region 9 of part has source metal silicide 11b.Whole radio frequency LDMOS device all cover by before-metal medium layer 12.Source metal electrode 15b runs through before-metal medium layer 12, and bottom is in the upper surface of source metal silicide 11b or inside.Drain metal electrode 15c runs through before-metal medium layer 12 and gate oxide 3, and bottom is in the N-shaped heavy doping drain electrode upper surface of 8c or inside.Substrate metal electrode 15d runs through before-metal medium layer 12, silicide barrier layer 10, gate oxide 3, p-type heavy doping injection region 9, p-type channel region 7, p-type epitaxial layer 2, and bottom is in the upper surface of p-type silicon substrate 1 or inside.
Below the structure of the high efficiency radio frequency LDMOS device of the application is only described with a specific embodiment.Can distortion be made based on same principle on this basis, such as, the doping type of each several part be become contrary etc.
Compared with the existing radio frequency LDMOS device shown in Fig. 1, the application eliminates drain metal silicide 11c, and is directly externally drawn by N-shaped heavy doping drain electrode 8c by drain metal electrode 15c.Refer to 4, this is the design layout of the part-structure of the radio frequency LDMOS device shown in Fig. 3.Just Fig. 3 is correspond to along the cross-section structure in A-A direction in Fig. 4.In Fig. 4, the design configuration of p-type channel region 7 can partly overlap with polysilicon gate 4, when forming the ion implantation of p-type channel region 7, lap is subject to the stop of polysilicon gate 4, and during annealing after ion implantation, the final graphics of p-type channel region 7 can partly overlap with polysilicon gate 4.Similarly, the design configuration of N-shaped heavy doping source electrode 8b can partly overlap with polysilicon gate 4 and with source metal electrode 15b zero lap, when forming the ion implantation of N-shaped heavy doping source electrode 8b, lap is subject to the stop of polysilicon gate 4, and during annealing after ion implantation, the final graphics of N-shaped heavy doping source electrode 8b can partly overlap with polysilicon gate 4 and partly overlap with source metal electrode 15b.In the drain-end region of the radio frequency LDMOS device of the application, only need meet the layout area of the layout area ﹤ N-shaped heavy doping drain electrode 8c of drain metal electrode 15c, thus breach the alignment rule restriction of original three layers of nested structure.So just, the width d of N-shaped heavy doping drain electrode 8c can be reduced, thus reduce source drain capacitance C
ds, improve efficiency and the nonlinearity of device.
Refer to Fig. 5, this is the operating voltage of radio frequency LDMOS device and the graph of a relation of peak efficiency under different operating frequency.Can find out after operating voltage is greater than 10V, the higher then peak efficiency of operating frequency is lower.
Refer to Fig. 6, this is the simple equivalent circuit figure of radio frequency LDMOS device.Radio frequency LDMOS device can simplify and is equivalent to three branch circuit parallel connections: the first branch road is source electrode and the drain electrode of a MOS transistor Q1; Second branch road is the source drain capacitance C of series connection
dswith resistance R
p; 3rd branch road is load resistance R
load.According to the empirical equation of the efficiency of calculating radio frequency LDMOS device
known, source drain capacitance C
dsless then device efficiency is higher.The radio frequency LDMOS device of the application is just because of reducing source drain capacitance C
dsthus improve device efficiency.
The manufacture method of the high efficiency LDMOS device of the application will be introduced below with a specific embodiment.
1st step, refers to Fig. 7 a and Fig. 7 b, p-type silicon substrate 1 adopts epitaxy technique grow p-type epitaxial layer 2.P-type epitaxial layer 2 adopt thermal oxidation technology grow gate oxide 3.Depositing polysilicon 4 on gate oxide 3.
2nd step, refers to Fig. 7 c, adopts photoetching and dry etch process that polysilicon 4 is etched polysilicon gate 4.Photoresist 5 covers on polysilicon gate 4.
3rd step, refer to Fig. 7 d and Fig. 7 e, adopt photoetching and N-shaped ion implantation technology in the p-type epitaxial layer 2 of polysilicon gate 4 one side-lower, form N-shaped light dope injection region 6, adopt in photoetching and the p-type epitaxial layer 2 of p-type ion implantation technology below polysilicon gate 4 opposite side and form p-type channel region 7, this two steps operating sequence can be exchanged.The ion implantation energy forming p-type channel region 7 is such as 50keV, and p-type ion implantation dosage is such as 1 × 10
12~ 1 × 10
13ions per cubic centimeter.Then annealing, can be high temperature furnace annealing or rapid thermal annealing (RTA).
4th step, refer to Fig. 7 f and Fig. 7 g, adopt photoetching and N-shaped ion implantation technology in N-shaped light dope injection region 6, form N-shaped heavy doping drain electrode 8c, in p-type channel region 7, form N-shaped heavy doping source electrode 8b simultaneously, adopt photoetching and p-type ion implantation technology in p-type channel region 7, form p-type heavy doping injection region 9.P-type heavy doping injection region 9 contains the region that part is N-shaped heavy doping source electrode 8b originally, and therefore in p-type channel region 7, p-type heavy doping injection region 9 and N-shaped heavy doping source electrode 8b side contact.Then annealing, can be high temperature furnace annealing or rapid thermal annealing (RTA).
5th step, refers to Fig. 7 h and Fig. 7 i, adopts self-registered technology to form gate metal silicide 11a on polysilicon gate 4, forms source metal silicide 11b simultaneously at partially n-type heavy doping source electrode 8b and part of p-type heavy doping injection region 9.The thickness of metal silicide 11a and 11b is such as
this step mainly comprises: depositing silicide barrier layer 10, and this is the dielectric materials such as such as silica; Adopt dry plasma etching process to anti-carve silicide barrier layer 10, thus form sidewall structure (now polysilicon gate 4 upper surface comes out) in the both sides of polysilicon gate 4; Photoetching and etching technics is adopted the silicide barrier layer 10 and gate oxide 3 that prepare to be formed source metal silicide regions to be removed (now the upper surface of the N-shaped heavy doping source electrode 8b of part and the p-type heavy doping injection region 9 of part comes out); Deposit for the formation of the metal of metal silicide, such as, is titanium; Carry out high annealing, make metal and silicon form metal silicide 11a and 11b; Wet chemical etch process is adopted to remove remaining metal.
6th step, refers to Fig. 7 j, and before depositing metal, medium 12 covers all structures, the upper surface of medium 12 before employing flatening process flat metal.Flatening process can be cmp (CMP), dry plasma etching process anti-carves.
7th step, refers to Fig. 7 k and Fig. 3, adopts photoetching and etching technics in the region of p-type heavy doping injection region 9, form at least one sunk type through hole 13.Sunk type through hole 13 runs through pre-metal dielectric 12, silicide barrier layer 10, p-type heavy doping injection region 9, p-type channel region 7, p-type epitaxial layer 2, and bottom is in the upper surface of p-type silicon substrate 1 or inside.Adopt photoetching and etching technics to form at least one source contact openings 14b on source metal silicide 11b, on N-shaped heavy doping drain electrode 8c, form at least one drain contact hole 14c simultaneously.The bottom of source contact openings 14b is in the upper surface of source metal silicide 11b or inside.The bottom of drain contact hole 14c is in the upper surface of N-shaped heavy-doped source drain electrode 8a or inside.The two step operating sequences forming sunk type through hole 13 and contact hole 14b and 14c can be exchanged.Deposit for the formation of the metal of metal electrode, such as, is tungsten; Adopt the upper surface of flatening process flat metal again until with the upper surface flush of before-metal medium layer 12, thus in sunk type through hole 13, form substrate metal electrode 15d, in source contact openings 14b, form source metal electrode 15b simultaneously, in drain contact hole 14c, form drain metal electrode 15c simultaneously.Flatening process can be cmp (CMP), dry plasma etching process anti-carves.Alternatively, before deposit is for the formation of the metal of metal electrode, first can carry out N-shaped ion implantation to reduce contact resistance in sunk type through hole 13 and contact hole 14b and 14c.
In order to the existing radio frequency LDMOS device shown in shop drawings 1, need first on N-shaped heavy doping drain electrode 8c, to form drain metal silicide 11c, then form drain metal electrode 15c drain metal silicide 11c is electrically drawn.The manufacture method of the high efficiency radio frequency LDMOS device of the application by comparison, only needs to form drain metal electrode 15c on N-shaped heavy doping drain electrode 8c, is directly electrically drawn by N-shaped heavy doping drain electrode 8c by drain metal electrode 15c.
These are only the preferred embodiment of the application, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (8)
1. a high efficiency radio frequency LDMOS device, comprises heavy doping drain electrode, it is characterized in that, heavy doping drain electrode has drain metal electrode; Bottom and the heavy doping of described drain metal electrode drain to contact and heavy doping drained and electrically draw.
2. high efficiency radio frequency LDMOS device according to claim 1, is characterized in that having epitaxial loayer on a silicon substrate; Portion of epi layer has gate oxide; Part gate oxide has polysilicon gate; In the epitaxial loayer of polysilicon gate one side-lower, there is light dope injection region, in the epitaxial loayer below polysilicon gate opposite side, there is channel region; There is heavy doping drain electrode in light dope injection region; There is heavy doping source electrode and the heavy doping injection region of contacts side surfaces in channel region; Part gate oxide has silicide barrier layer; Polysilicon gate has gate metal silicide; Part heavy doping source electrode and heavy doping injection region has source metal silicide; Whole device all cover by before-metal medium layer; It also electrically draws by source metal electrode contact source metal silicide; It also electrically draws by the heavy doping drain electrode of drain metal electrode contact N-shaped; It also electrically draws by substrate metal electrode contact silicon substrate;
Described silicon substrate, epitaxial loayer, channel region, heavy doping injection region are the first doping type;
Described light dope injection region, heavy doping drain electrode, heavy-doped source very the second doping type.
3. high efficiency radio frequency LDMOS device according to claim 1, is characterized in that, the layout area of the layout area ﹤ heavy doping drain electrode of described drain metal electrode.
4. a manufacture method for high efficiency radio frequency LDMOS device, is characterized in that, is included in heavy doping drain electrode and forms drain metal electrode, and the step of the electrically extraction that directly heavy doping drained by drain metal electrode.
5. the manufacture method of high efficiency radio frequency LDMOS device according to claim 4, is characterized in that, comprise the steps:
1st step, adopts epitaxy technique grown epitaxial layer on a silicon substrate, epitaxial loayer adopts thermal oxidation technology grow gate oxide, depositing polysilicon on gate oxide;
2nd step, adopts photoetching and dry etch process that etching polysilicon is gone out polysilicon gate;
3rd step, adopts photoetching and ion implantation technology in the epitaxial loayer of polysilicon gate one side-lower, form light dope injection region, adopts in photoetching and the epitaxial loayer of ion implantation technology below polysilicon gate opposite side and form channel region;
4th step, adopt photoetching and ion implantation technology in light dope injection region, form heavy doping drain electrode, in channel region, form heavy doping source electrode simultaneously, adopt photoetching and ion implantation technology in channel region, to form heavy doping injection region, heavy doping injection region and heavy doping source electrode contacts side surfaces;
5th step, adopts self-registered technology to form gate metal silicide on polysilicon gate, forms source metal silicide simultaneously on part heavy doping source electrode and heavy doping injection region;
6th step, before depositing metal, there is structure in dielectric overlay residence, the upper surface of medium before employing flatening process flat metal;
7th step, adopts photoetching and etching technics in the region of heavy doping injection region, form sunk type through hole, and the bottom of sunk type through hole is in the upper surface of silicon substrate or inside; Adopt photoetching and etching technics to form source contact openings on source metal silicide, in heavy doping drain electrode, form at least drain contact hole simultaneously; Depositing metal fills sunk type through hole, source contact openings and drain contact hole; Adopt the upper surface of flatening process flat metal again until with the upper surface flush of before-metal medium layer, thus substrate metal electrode is formed in sunk type through hole, in source contact openings, form source metal electrode simultaneously, in drain contact hole, form drain metal electrode simultaneously.
6. the manufacture method of high efficiency radio frequency LDMOS device according to claim 5, is characterized in that, in described method the 3rd step, the ion implantation energy forming channel region is 50keV, and ion implantation dosage is 1 × 10
12~ 1 × 10
13ions per cubic centimeter.
7. the manufacture method of high efficiency radio frequency LDMOS device according to claim 5, is characterized in that, described method the 5th step specifically comprises: depositing silicide barrier layer; Adopt dry plasma etching process to anti-carve silicide barrier layer, thus form sidewall structure in the both sides of polysilicon gate; Photoetching and etching technics is adopted the silicide barrier layer and gate oxide that prepare to be formed source metal silicide regions to be removed; Deposit for the formation of metal silicide metal and carry out high annealing, make metal and silicon form metal silicide; Wet chemical etch process is adopted to remove remaining metal.
8. the manufacture method of high efficiency radio frequency LDMOS device according to claim 5, is characterized in that, in described method the 7th step, before depositing metal, first in sunk type through hole and contact hole, carries out ion implantation to reduce contact resistance.
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| CN112558354A (en) * | 2020-12-09 | 2021-03-26 | 华南理工大学 | Backlight substrate and display panel |
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| CN103390645A (en) * | 2012-05-08 | 2013-11-13 | 上海韦尔半导体股份有限公司 | LDMOS transistor and manufacturing method thereof |
| CN103035727A (en) * | 2012-11-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) component and manufacture method |
| CN103871881A (en) * | 2012-12-14 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Groove of P type LDMOS device and manufacture method of groove |
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| CN112558354A (en) * | 2020-12-09 | 2021-03-26 | 华南理工大学 | Backlight substrate and display panel |
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