CN104465325A - Method for improving evenness of critical size of active area - Google Patents
Method for improving evenness of critical size of active area Download PDFInfo
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- CN104465325A CN104465325A CN201410714895.5A CN201410714895A CN104465325A CN 104465325 A CN104465325 A CN 104465325A CN 201410714895 A CN201410714895 A CN 201410714895A CN 104465325 A CN104465325 A CN 104465325A
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- active area
- wafer
- critical size
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Weting (AREA)
Abstract
The invention relates to the technology of semiconductor devices, in particular to a method for improving evenness of the critical size of an active area. The method is suitable for a wafer with the critical size of the active area of a marginal area of the wafer larger than that of the active area of a central area of the wafer. The wet cleaning and etching technology is adopted. A hydrofluoric acid solution of 0.15% -2% is used in a single-chip microcomputer table for carrying out cleaning and etching to remove oxidation films formed on the side wall of a groove of the marginal area of the wafer under natural conditions, oxidising chemicals are then used to remove silicon dioxide of a silicon oxidation layer of the side wall of the groove of the marginal area of the wafer, and the mentioned steps are repeated until the critical size of the marginal active area of the wafer is identical to that of the active area of the central area of the wafer. The method is simple, operation is easy, and the evenness of the critical size of the active area of the wafer is improved effectively.
Description
Technical field
The present invention relates to semiconductor device technology, particularly relate to a kind of method improving active area critical dimension uniformity.
Background technology
The critical size of active area is the important parameter in semiconductor device, along with semiconductor technology is towards accurate future development, the uniformity (namely wafer edge region active area critical size is identical with wafer central region active area critical size) of active area critical size more and more comes into one's own, the uniformity of current those skilled in the art by adopting the method for photoetching and dry etching to effectively improve the critical size of active area is to a great extent a much progress of this area technique.
But for this kind of technology, the improvement of this active area critical dimension uniformity realizes by photoetching and dry etching, due to the restriction of photoetching itself, active area critical size is less, photoetching difficulty is higher, therefore some the active area dimensions uniformity finally obtained all do not meet user to active area critical dimension uniformity demand, some is the critical size that cannot improve active area critical dimension uniformity further and obtain under the condition of process technology limit, people adopt various method to solve this problem, what become to make the critical size of active area is even with the demand meeting user, such as adopt new light source (UV), double exposure techniques etc., but due to the reason of each side, these technology are all difficult to the demand meeting user, therefore, how to implement to improve active area critical size and become a great problem that those skilled in the art face.
Summary of the invention
For the problems referred to above, the present invention proposes a kind of method improving active area critical dimension uniformity, on wafer, wafer edge region is had chance with the critical size in the district region larger than wafer central region active area critical size, the natural oxidizing layer being positioned at wafer edge region trenched side-wall is removed by adopting wet-cleaned and etching technics, make the oxide removal of the silicon of wafer edge region trenched side-wall self-assembling formation, then oxidizing chemical is adopted to process wafer edge region, the silica of fringe region trenched side-wall is made to change into silicon dioxide, repeat above-mentioned steps afterwards, until the critical size of full wafer wafer active area becomes even, (namely active area, wafer edge region critical size is identical with wafer central region active area critical size) concrete grammar is:
Improve a method for active area critical dimension uniformity, wherein, said method comprising the steps of:
The wafer that one has central area and a fringe region is provided, described central area is provided with wafer central region active area, described marginal zone is provided with wafer edge region active area, and the active area critical size of described wafer edge region is larger than described wafer central region active area critical size, separates between described active area with groove:
Step S1: the natural oxidizing layer removing described wafer edge region trenched side-wall by wet clean process;
Step S2: with wafer edge region trenched side-wall described in oxidizing chemical process, to regenerate an oxide layer at trenched side-wall;
Repeat step S1, step S2 several times, until wafer edge region active area critical size is identical with wafer central region active area critical size, namely wafer active area critical dimension uniformity is improved.
Preferably, the cleaning fluid that described wet clean process uses is hydrofluoric acid.
Preferably, in described hydrofluoric acid solution, the content of hydrofluoric acid is 0.15%-2%.
Preferably, described oxidizing chemical is the mixed liquor of sulfuric acid and hydrogen peroxide or the deionized water containing ozone.
Preferably, the concentration of described deionization ozone in water is 2ppm-20ppm.
Said method, wherein, the critical size that described method reduces described wafer edge region active area is 1nm-10nm.
Said method, wherein, implements described wet-cleaned and oxidation technology at single chip washer platform.Foregoing invention tool has the following advantages or beneficial effect:
The method of the invention simply, is easily implemented, and effectively can improve Waffer edge active area critical dimension uniformity, makes wafer edge region active area critical size identical with wafer central region active area critical size.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the embodiment of the present invention;
Fig. 2 is that the embodiment of the present invention provides chip architecture schematic diagram;
Fig. 3 is the wafer edge region active area structure schematic diagram that the embodiment of the present invention provides;
Fig. 4 is the structural representation of wafer edge region trenched side-wall after wet-cleaned that the embodiment of the present invention provides;
Fig. 5 is the structural representation of wafer edge region trenched side-wall after peroxidating that the embodiment of the present invention provides.
Execution mode
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
For above-mentioned Problems existing, the present invention discloses a kind of effective method improving Waffer edge active area critical dimension uniformity, by the natural oxidizing layer adopting wet clean process and etch process to remove wafer edge region active area trenched side-wall, then a new oxide layer is formed with the trenched side-wall of oxidizing chemical after removing oxide layer, overcome the defect that conventional method dry etching is just difficult to carry out to certain size, effectively reduce the critical size of wafer edge region active area, repeat above-mentioned steps, until wafer edge region active area critical size is identical with wafer central region active area critical size, effectively improve wafer active area critical dimension uniformity, this method is simple, easy enforcement, the requirement of user to wafer active area critical dimension uniformity can be met.The specific embodiment of the present invention is:
Structure shown in Figure 2, what provide for the embodiment of the present invention has the wafer edge region including wafer central region He be surrounded on center wafer, wherein, wafer central region is provided with wafer central region active area, Waffer edge is provided with wafer edge region active area, and wafer edge region active area critical size is greater than wafer central region active area critical size, therefore user needs to reduce active area, wafer edge region critical size to improve the uniformity of active area critical size.
With reference to structural representation shown in Fig. 3, for the wafer edge region active area structure that the present embodiment provides, , wherein 1 is the first groove that the present embodiment provides wafer edge region, 2 is second grooves that the present embodiment provides wafer edge region, be wherein Waffer edge active area between wafer edge region first groove 1 and wafer edge region second groove 2, first oxide-film 3 represents the oxide-film of wafer edge region first groove 1 sidewall oxidized formation under field conditions (factors), second oxide-film 4 refers to the oxide-film of wafer edge region second groove 2 sidewall oxidized formation under field conditions (factors).
With reference to structure shown in Fig. 4, in monolithic board, use wet clean process to remove the first oxide-film 3 and the second oxide-film 4, wet-cleaned uses concentration to be the hydrofluoric acid solution of 0.15%-2%, with the second oxide-film 4 of the first oxide-film 3 and wafer edge region second trenched side-wall of removing wafer edge region first trenched side-wall, deionized water is then used to remove the hydrofluoric acid of the first groove 1 surface and the second groove 2 remained on surface.Emphasis of the present invention is the sidewall of wafer edge region first groove and wafer edge region second groove, and in specific implementation process, wafer edge region first channel bottom and wafer edge region second channel bottom also have cleaning.Etching removes the process of oxide layer and the oxidation of this oxidizing chemical, owing to not being key problems-solving of the present invention, repeats no more in the drawings and in the present embodiment.It will be understood by those skilled in the art that and only have the minor variations of bottom not affect novelty of the present invention.
With reference to structure shown in Fig. 5, with the sidewall of wafer edge region first groove 1 of oxidizing chemical process first oxide-film 3 and the sidewall of wafer edge region second groove 2 of removal the second oxide-film 4, the oxidizing chemical wherein used can be the mixed acid of deionized water ozoniferous or sulfuric acid and hydrogen peroxide, wherein the concentration of deionization ozone in water ozoniferous is 2ppm-20ppm, the silica of the Waffer edge active area groove after oxide layer removal can be changed into silicon dioxide by oxidizing chemical, through process, the silicon of wafer edge region first groove 1 sidewall and wafer edge region second groove 2 sidewall is oxidized to silicon dioxide, because the oxide-film of formation oxidized under natural conditions is washed, therefore the critical size of wafer edge region active area and the size between wafer edge region first groove and wafer edge region second groove reduce, through this process, Waffer edge active area critical dimension reduction 1nm-2nm.
Wherein, defining wet-cleaned, etching and forming oxide-film with oxidizing chemical process wafer edge region first groove and the second groove is an operation cycle, each end cycle, the critical dimension reduction 1nm-2nm of wafer edge region active area, user determines the periodicity that the needs of oneself repeat, until the critical size of wafer edge region active area is identical with wafer central region active region critical size according to the difference of wafer edge region active area critical size and wafer central region active area critical size.Finally, dry described wafer, the improved wafer of active area critical dimension uniformity.In sum, by the oxide-film using the hydrofluoric acid solution wet-cleaned of 0.15%-2% concentration in monolithic board, etching removal wafer edge region trenched side-wall is formed under field conditions (factors), then use oxidizing chemical that the silica of wafer fringe region trenched side-wall is changed into silicon dioxide, repeatedly carry out above step, until the critical size of wafer edge region active area is identical with wafer central region active area critical size, wafer key size critical dimension uniformity is improved.Make simply, easily to implement in this way, and effectively improve active area critical dimension uniformity.It should be appreciated by those skilled in the art that those skilled in the art are realizing described change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs to the scope of technical solution of the present invention protection.
Claims (7)
1. improve a method for active area critical dimension uniformity, it is characterized in that, said method comprising the steps of:
There is provided one have central area and fringe region wafer, described central area is provided with active area, central area, described fringe region is provided with fringe region active area, and the active area critical size of described wafer edge region is larger than wafer central region active area critical size, separates between described active area with groove:
Step S1: the natural oxidizing layer removing described wafer edge region trenched side-wall by wet clean process;
Step S2: with wafer edge region trenched side-wall described in oxidizing chemical process, to regenerate an oxide layer at trenched side-wall;
Repeat step S1, step S2 several times, until wafer edge region active area critical size is identical with wafer central region active area critical size, namely wafer active area critical dimension uniformity is improved.
2. method as claimed in claim 1, is characterized in that, the cleaning fluid that described wet clean process uses is hydrofluoric acid solution.
3. method as claimed in claim 2, it is characterized in that, in described hydrofluoric acid solution, the content of hydrofluoric acid is 0.15%-2%.
4. method as claimed in claim 1, is characterized in that, described oxidizing chemical is the mixed liquor of sulfuric acid and hydrogen peroxide or the deionized water containing ozone.
5. method as claimed in claim 4, it is characterized in that, the concentration of described deionization ozone in water is 2ppm-20ppm.
6. method as claimed in claim 1, is characterized in that, utilize described method by wafer edge region active area critical dimension reduction 1nm-10nm.
7. method as claimed in claim 1, is characterized in that, implement described wet-cleaned and oxidation technology at single chip washer platform.
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| CN201410714895.5A CN104465325A (en) | 2014-11-28 | 2014-11-28 | Method for improving evenness of critical size of active area |
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| CN201410714895.5A CN104465325A (en) | 2014-11-28 | 2014-11-28 | Method for improving evenness of critical size of active area |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104992928A (en) * | 2015-05-15 | 2015-10-21 | 上海华力微电子有限公司 | Method for improving difference between critical dimensions of active areas of different wafers |
| CN110729293A (en) * | 2019-11-19 | 2020-01-24 | 上海华力集成电路制造有限公司 | Method for increasing effective area of active region |
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| CN1711211A (en) * | 2002-11-18 | 2005-12-21 | 皇家飞利浦电子股份有限公司 | Dispersion of nanowires of semiconductor material |
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| CN102792426A (en) * | 2010-03-10 | 2012-11-21 | 应用材料公司 | Apparatus and methods for cyclical oxidation and etching |
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| CN104124194A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Groove forming method |
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| KR100255665B1 (en) * | 1998-01-08 | 2000-05-01 | 윤종용 | Method for fabricating semiconductor device which havig a different thickness gate oxide structure in a semiconductor substrate |
| CN1711211A (en) * | 2002-11-18 | 2005-12-21 | 皇家飞利浦电子股份有限公司 | Dispersion of nanowires of semiconductor material |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104992928A (en) * | 2015-05-15 | 2015-10-21 | 上海华力微电子有限公司 | Method for improving difference between critical dimensions of active areas of different wafers |
| CN104992928B (en) * | 2015-05-15 | 2018-02-27 | 上海华力微电子有限公司 | A kind of method of active area critical size difference between improvement different chips |
| CN110729293A (en) * | 2019-11-19 | 2020-01-24 | 上海华力集成电路制造有限公司 | Method for increasing effective area of active region |
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