CN100565839C - The manufacture method of the gate oxide of different-thickness - Google Patents
The manufacture method of the gate oxide of different-thickness Download PDFInfo
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- CN100565839C CN100565839C CNB2007101087125A CN200710108712A CN100565839C CN 100565839 C CN100565839 C CN 100565839C CN B2007101087125 A CNB2007101087125 A CN B2007101087125A CN 200710108712 A CN200710108712 A CN 200710108712A CN 100565839 C CN100565839 C CN 100565839C
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Abstract
The invention discloses a kind of manufacture method of gate oxide of different-thickness.The method is, substrate is provided, and substrate has high voltage devices district and lower voltage components district.Then, in substrate, form the high voltage gate oxide.Afterwards, carry out first wet etch process, remove the part high voltage gate oxide in lower voltage components district.Subsequently, carry out second wet etch process, remove the residual high voltage gate oxide in lower voltage components district.Wherein, the rate of etch of second wet etch process is less than the rate of etch of first wet etch process.Then, in the substrate in lower voltage components district, form the low voltage gate oxide layer.
Description
Technical field
The present invention relates to a kind of manufacture method of integrated circuit, and be particularly related to a kind of manufacture method of gate oxide of different-thickness.
Background technology
In recent years, flourish along with electronic industry makes integrated circuit (IC) chip be subjected to extensive utilization, is the demand of making rapid progress in response to electronic industry, many about semi-conductive technology also with develop rapidly.
In integrated circuit component, different circuit need have the different circuit element close fit of different fundamental operation characteristics.And be competitiveness and diversity in response to circuit element, the element that must have different gate oxide thickness on some circuit simultaneously exists, to satisfy the demand of different operating voltage, therefore just need multiple gate oxide thickness (multiple gate oxide thickness).Generally speaking, on same chip, can have high voltage (high voltage simultaneously, be called for short HV) and low-voltage (low voltage, be called for short LV) element of different voltages such as element, and the high voltage devices thicker gate oxide of need growing up just can bear high-tension operational environment, and the lower voltage components thin gate oxide of then growing up can bear the operational environment of low-voltage.
With present technology, when gate oxide thickness difference is very big, some difficult problems that in follow-up technology, can face.Therefore, how to make the gate oxide of multiple thickness, and can keep film layer quality, just become an important topic that needs to be resolved hurrily to avoid influencing element efficiency.
Summary of the invention
In view of this, purpose of the present invention is exactly the manufacture method at the gate oxide that a kind of different-thickness is provided, and can solve a known difficult problem that causes greatly because of gate oxide thickness difference, and can promote the film layer quality of gate oxide.
The present invention proposes a kind of manufacture method of gate oxide of different-thickness.The method is, substrate is provided, and substrate has first element region and second element region.Then, in substrate, form first grid oxide layer.Then, carry out first wet etch process, remove the part first grid oxide layer of second element region.Continue it, carry out second wet etch process, remove the residual first grid oxide layer of second element region.Wherein, the rate of etch of second wet etch process is less than the rate of etch of first wet etch process.Subsequently, in the substrate of second element region, form second gate oxide.Above-mentioned, the thickness of second gate oxide is less than first grid thickness of oxide layer.
Described according to embodiments of the invention, above-mentioned substrate also comprises the three element district.In one embodiment, also comprise: carrying out first wet etch process, when removing the part first grid oxide layer of second element region, removing the part first grid oxide layer in three element district simultaneously.Then, carry out second wet etch process, when removing the residual first grid oxide layer of second element region, removing the residual first grid oxide layer in three element district simultaneously.Then, in the substrate in three element district, form the 3rd gate oxide.Wherein, the thickness of the 3rd gate oxide is between the thickness of the first grid oxide layer and second gate oxide.The formation method of the 3rd gate oxide for example is thermal oxidation method, chemical vapour deposition technique or other suitable methods.Hold above-mentionedly, first element region, second element region are to be used for different voltage-operated element regions with the three element district.
Described according to embodiments of the invention, the first above-mentioned wet etch process for example is to use the buffer oxide etch agent, and second wet etch process for example is to use dilute hydrofluoric acid.Wherein, the buffer oxide etch agent is HF/NH
4The solution that F mixes with 20: 1 ratio and water.Dilute hydrofluoric acid is HF/H
2The solution that O forms with 1: 10 mixed.
Described according to embodiments of the invention, have component isolation structure in first above-mentioned element region and the substrate between second element region.Component isolation structure for example is fleet plough groove isolation structure or field oxide.
Described according to embodiments of the invention, the formation method of above-mentioned first grid oxide layer for example is thermal oxidation method or chemical vapour deposition technique.
Described according to embodiments of the invention, the formation method of the second above-mentioned gate oxide for example is thermal oxidation method or chemical vapour deposition technique.
The present invention proposes a kind of manufacture method of gate oxide of different-thickness in addition.The method is, substrate is provided, and substrate has high voltage devices district and lower voltage components district.Then, in substrate, form the high voltage gate oxide.Afterwards, carry out first wet etch process, remove the part high voltage gate oxide in lower voltage components district.Subsequently, carry out second wet etch process, remove the residual high voltage gate oxide in lower voltage components district.Wherein, the rate of etch of second wet etch process is less than the rate of etch of first wet etch process.Then, in the substrate in lower voltage components district, form the low voltage gate oxide layer.
Described according to embodiments of the invention, the first above-mentioned wet etch process for example is to use the buffer oxide etch agent, and second wet etch process for example is to use dilute hydrofluoric acid.Wherein, the buffer oxide etch agent is HF/NH
4The solution that F mixes with 20: 1 ratio and water.Dilute hydrofluoric acid is HF/H
2The solution that O forms with 1: 10 mixed.
Described according to embodiments of the invention, have component isolation structure in first above-mentioned element region and the substrate between second element region.Component isolation structure for example is fleet plough groove isolation structure or field oxide.
Described according to embodiments of the invention, the formation method of above-mentioned first grid oxide layer for example is thermal oxidation method or chemical vapour deposition technique.
Described according to embodiments of the invention, the formation method of the second above-mentioned gate oxide for example is thermal oxidation method or chemical vapour deposition technique.
Because method of the present invention is, utilize the wet etch process of high etch rates to remove the part high voltage gate oxide in lower voltage components district earlier, utilize the wet etch process of low etch-rate to remove residual high voltage gate oxide afterwards again.Therefore, method of the present invention can not produce coarse or uneven problem because of over etching causes the side wall profile of high voltage gate oxide, and can improve the problem of the substrate surface damage in lower voltage components district, and can form the good gate oxide of quality.In addition, method of the present invention also can avoid causing component isolation structure and substrate adjoiner to produce depression, and causes the generation of problems such as neck knot effect and gate oxide thinning.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below.
Description of drawings
Figure 1A to Fig. 1 D is the schematic flow sheet according to the manufacture method of the gate oxide of the different-thickness that one embodiment of the invention illustrated.
Fig. 2 A to Fig. 2 D is the schematic flow sheet according to the manufacture method of the gate oxide of the different-thickness that another embodiment of the present invention illustrated.
Fig. 3 A to Fig. 3 D is the schematic flow sheet according to the manufacture method of the gate oxide of the different-thickness that another embodiment of the present invention illustrated.
Description of reference numerals
100,200,300: substrate
102,202,302: the high voltage devices district
104,204,304: the lower voltage components district
106,106a, 206,206a, 306,306a: high voltage gate oxide
108,208,308: the first wet etch process
110,210,310: the second wet etch process
112,212,312: the low voltage gate oxide layer
205: field oxide
220,320: depression
305: fleet plough groove isolation structure
Embodiment
Figure 1A to Fig. 1 D is the schematic flow sheet according to the manufacture method of the gate oxide of the different-thickness that one embodiment of the invention illustrated.
At first, please refer to Figure 1A, substrate 100 is provided, have high voltage devices district 102 and lower voltage components district 104 in this substrate 100.In the present embodiment, high voltage devices district 102 for example is the element region that is used under the 40 voltaism press operations, and lower voltage components district 104 for example is the element region that is used under the 3.3 voltaism press operations.
Then, please continue, in substrate 100, form one deck high voltage gate oxide 106 with reference to Figure 1A.The material of high voltage gate oxide 106 for example is a silica, and its formation method for example is thermal oxidation method, chemical vapour deposition technique or other suitable methods.The thickness of high voltage gate oxide 106 is about 850 dusts.
Then, utilize the wet etch process of different etch-rates to remove the high voltage gate oxide in lower voltage components district.Please refer to Figure 1B, carry out first wet etch process 108, removing the part high voltage gate oxide 106 in lower voltage components district 104, and stay high voltage gate oxide 106a.Above-mentioned, the thickness of the high voltage gate oxide 106a that does not remove is between 100 dust to 150 dusts.In the present embodiment, first wet etch process 108 for example is to use the buffer oxide etch agent (buffered oxide etchant, BOE), it is HF/NH
4The solution that F mixes with 20: 1 ratio (volume ratio) and water.The etch-rate of this BOE is about between per minute 400 dust to 450 dusts.
Afterwards, please refer to Fig. 1 C, carry out second wet etch process 110, remove the residual high voltage gate oxide 106a in lower voltage components district 104.In the present embodiment, second wet etch process 110 for example is to use dilute hydrofluoric acid (diluted HF, DHF), it is HF/H
2The solution that O mixes with 1: 10 ratio (volume ratio).The etch-rate of this DHF is about between per minute 50 dust to 70 dusts.
Be noted that especially known is to utilize the etchant of high etch rates directly to remove the high voltage gate oxide in lower voltage components district to exposing substrate surface, to save time and the technology cost.Yet, the method easily is removed over etching fully because of the high voltage gate oxide of guaranteeing the lower voltage components district, and the side wall profile that causes the high voltage gate oxide in high voltage devices district produces coarse or uneven problem, and can make the substrate surface in lower voltage components district sustain damage.Above-mentioned problem all can influence subsequent technique, the gate oxide bad that makes follow-up formation, and reduce element efficiency.
In addition, the known method that removes the high voltage gate oxide in lower voltage components district also comprises and utilizes the dry-etching method to carry out.The method need additionally use photomask and then improve the technology cost, and its employed plasma also can cause the substrate surface damage.
Continue it, please refer to Fig. 1 D, after removing the high voltage gate oxide 106 in lower voltage components district 104, then in the substrate 100 in lower voltage components district 104, form low voltage gate oxide layer 112.The material of low voltage gate oxide layer 112 for example is a silica, and its formation method for example is thermal oxidation method, chemical vapour deposition technique or other suitable methods.The thickness of low voltage gate oxide layer 112 is about 65 dusts.
In one embodiment, be used in the middle voltage component district (do not illustrate) of operating voltage between 40 volts to 3.3 volts also comprising in the substrate 100 having.Hold above-mentionedly, the formation method of the middle voltage grid oxide layer in the middle voltage component district for example is when carrying out first wet etch process 108, the part high voltage gate oxide in voltage component district in also removing simultaneously.Then, when carrying out second wet etch process 110, the residual high voltage gate oxide in voltage component district in also removing simultaneously.Subsequently, in the substrate 100 in middle voltage component district, form in the voltage grid oxide layer.In the voltage grid thickness of oxide layer between high voltage gate oxide and low voltage gate thickness of oxide layer, that is be between 65 dust to 850 dusts.
It should be noted that because present embodiment is to utilize the wet etch process of high etch rates to remove the part high voltage gate oxide in lower voltage components district earlier, utilize the wet etch process of low etch-rate to remove residual high voltage gate oxide afterwards again.Therefore, the method for present embodiment can not produce coarse or uneven problem because of over etching causes the side wall profile of high voltage gate oxide, and can improve the problem of the substrate surface damage in lower voltage components district, and can form the good gate oxide of quality.And the method for present embodiment does not need additionally to use photomask, and can save the technology cost.
Next, enumerate other embodiment so that method of the present invention more clearly to be described.
Fig. 2 A to Fig. 2 D is the schematic flow sheet according to the manufacture method of the gate oxide of the different-thickness that another embodiment of the present invention illustrated.Illustrated field oxide in this embodiment with as component isolation structure, and among Fig. 2 A to Fig. 2 D, the member identical with Figure 1A to Fig. 1 D then omits its explanation.
At first, please refer to Fig. 2 A, substrate 200 is provided, have high voltage devices district 202 and lower voltage components district 204 in this substrate 200.And, between high voltage devices district 202 and lower voltage components district 204, have field oxide 205, with as component isolation structure.Then, in substrate 200, form high voltage gate oxide 206.
Then, please refer to Fig. 2 B, carry out first wet etch process 208, removing the part high voltage gate oxide 206 in lower voltage components district 204, and stay high voltage gate oxide 206a.
Afterwards, please refer to Fig. 2 C, carry out second wet etch process 210, remove the residual high voltage gate oxide 206a in lower voltage components district 204.
Be noted that, the known etchant that utilizes high etch rates is directly removed the method for the high voltage gate oxide in lower voltage components district, tend to cause the field oxide of part etched, and form depression (shown in the label 220 of Fig. 2 C) in substrate and field oxide adjoiner.This depression problem can cause the generation of neck knot effect (kink effect), and influences element efficiency.
And, when follow-up formation gate oxide, because of the depression at substrate and field oxide adjoiner can influence oxidation rate, so the thickness at field oxide and the formed gate oxide of substrate adjoiner can be thinner than the thickness of the formed gate oxide of substrate, it causes the problem of uneven thickness, that is so-called gate oxide thinning (gate oxide thinning), it can cause the electrical problem of element, and influences element efficiency.
Continue, please refer to Fig. 2 D, after removing the high voltage gate oxide 206 in lower voltage components district 204, then in the substrate 200 in lower voltage components district 204, form low voltage gate oxide layer 212.
Because the method for present embodiment is to utilize the wet etch process of high etch rates to remove the part high voltage gate oxide in lower voltage components district earlier, utilizes the wet etch process of low etch-rate to remove residual high voltage gate oxide afterwards again.Therefore, can not form depression, can avoid the generation of problems such as neck knot effect and gate oxide thinning thus because of over etching causes substrate and field oxide adjoiner, but and lift elements usefulness.
Fig. 3 A to Fig. 3 D is the schematic flow sheet according to the manufacture method of the gate oxide of the different-thickness that another embodiment of the present invention illustrated.Illustrated fleet plough groove isolation structure in this embodiment with as component isolation structure, and among Fig. 3 A to Fig. 3 D, the member identical with Figure 1A to Fig. 1 D then omits its explanation.
At first, please refer to Fig. 3 A, substrate 300 is provided, have high voltage devices district 302 and lower voltage components district 304 in this substrate 300.And, between high voltage devices district 302 and lower voltage components district 304, have fleet plough groove isolation structure 305, with as component isolation structure.Then, in substrate 300, form high voltage gate oxide 306.
Then, please refer to Fig. 3 B, carry out first wet etch process 308, removing the part high voltage gate oxide 306 in lower voltage components district 304, and stay high voltage gate oxide 306a.
Afterwards, please refer to Fig. 3 C, carry out second wet etch process 310, remove the residual high voltage gate oxide 306a in lower voltage components district 304.
Be noted that, the known etchant that utilizes high etch rates is directly removed the method for the high voltage gate oxide in lower voltage components district, also can cause the fleet plough groove isolation structure of part etched, and form depression (shown in the label 320 of Fig. 3 C) at drift angle (top edge comer) peripheral part of fleet plough groove isolation structure.This depression problem can cause the generation of neck knot effect, and influences element efficiency.And when follow-up formation gate oxide, this depression problem also can cause so-called gate oxide thinning, and it can influence the electrical problem of element, and reduces element efficiency.。
Continue it, please refer to Fig. 3 D, after removing the high voltage gate oxide 306 in lower voltage components district 304, then in the substrate 300 in lower voltage components district 304, form low voltage gate oxide layer 312.
Because the method for present embodiment is to utilize the different wet etch process of etch-rate to remove the high voltage gate oxide in lower voltage components district.Therefore, can not form depression, so can avoid the generation of problems such as neck knot effect and gate oxide thinning because of over etching causes drift angle peripheral part of fleet plough groove isolation structure, but and lift elements usefulness.
In sum, method of the present invention has following advantage at least:
1. method of the present invention can avoid the side wall profile of known gate oxide to produce coarse or uneven problem, and the problem that can improve the substrate surface damage in lower voltage components district.And, also can promote the quality of the gate oxide of follow-up formation;
2. method of the present invention need not need the extra photomask that uses as dry-etching, therefore can comparatively save cost;
3. method of the present invention can not cause component isolation structure and substrate adjoiner to produce depression, does not therefore have the generation of problems such as neck knot effect and gate oxide thinning.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (20)
1. the manufacture method of the gate oxide of a different-thickness comprises:
Substrate is provided, and this substrate has first element region and second element region;
In this substrate, form first grid oxide layer;
Carry out first wet etch process, remove this first grid oxide layer of part of this second element region;
Carry out second wet etch process, remove this residual first grid oxide layer of this second element region,
Wherein the rate of etch of this second wet etch process is less than the rate of etch of this first wet etch process; And
In this substrate of this second element region, form second gate oxide,
Wherein the thickness of this second gate oxide is less than this first grid thickness of oxide layer.
2. the manufacture method of the gate oxide of different-thickness as claimed in claim 1, wherein this substrate also comprises the three element district.
3. the manufacture method of the gate oxide of different-thickness as claimed in claim 2 also comprises:
Carry out this first wet etch process, when removing this first grid oxide layer of part of this second element region, removing this first grid oxide layer of part in this three element district simultaneously;
Carry out this second wet etch process, when removing residual this first grid oxide layer of this second element region, removing this residual first grid oxide layer in this three element district simultaneously; And
In this substrate in this three element district, form the 3rd gate oxide,
Wherein the thickness of the 3rd gate oxide is between the thickness of this first grid oxide layer and this second gate oxide.
4. the manufacture method of the gate oxide of different-thickness as claimed in claim 3, wherein the formation method of the 3rd gate oxide comprises thermal oxidation method or chemical vapour deposition technique.
5. the manufacture method of the gate oxide of different-thickness as claimed in claim 2, wherein this first element region, this second element region are to be used for different voltage-operated element regions with this three element district.
6. the manufacture method of the gate oxide of different-thickness as claimed in claim 1, wherein this first wet etch process comprises and uses the buffer oxide etch agent, and this second wet etch process comprises the use dilute hydrofluoric acid.
7. the manufacture method of the gate oxide of different-thickness as claimed in claim 6, wherein this buffer oxide etch agent is HF/NH
4The solution that F mixes with 20: 1 volume ratio and water.
8. the manufacture method of the gate oxide of different-thickness as claimed in claim 6, wherein this dilute hydrofluoric acid is HF/H
2The solution that O mixes with 1: 10 volume ratio.
9. the manufacture method of the gate oxide of different-thickness as claimed in claim 1 wherein has component isolation structure in this substrate between this first element region and this second element region.
10. the manufacture method of the gate oxide of different-thickness as claimed in claim 9, wherein this component isolation structure comprises fleet plough groove isolation structure or field oxide.
11. the manufacture method of the gate oxide of different-thickness as claimed in claim 1, wherein the formation method of this first grid oxide layer comprises thermal oxidation method or chemical vapour deposition technique.
12. the manufacture method of the gate oxide of different-thickness as claimed in claim 1, wherein the formation method of this second gate oxide comprises thermal oxidation method or chemical vapour deposition technique.
13. the manufacture method of the gate oxide of a different-thickness comprises:
Substrate is provided, and this substrate has high voltage devices district and lower voltage components district;
In this substrate, form the high voltage gate oxide;
Carry out first wet etch process, remove this high voltage gate oxide of part in this lower voltage components district;
Carry out second wet etch process, remove this residual high voltage gate oxide in this lower voltage components district,
Wherein the rate of etch of this second wet etch process is less than the rate of etch of this first wet etch process; And
In this substrate in this lower voltage components district, form the low voltage gate oxide layer.
14. the manufacture method of the gate oxide of different-thickness as claimed in claim 13, wherein this first wet etch process comprises the agent of use buffer oxide etch, and this second wet etch process comprises the use dilute hydrofluoric acid.
15. the manufacture method of the gate oxide of different-thickness as claimed in claim 14, wherein this buffer oxide etch agent is HF/NH
4The solution that F mixes with 20: 1 volume ratio and water.
16. the manufacture method of the gate oxide of different-thickness as claimed in claim 14, wherein this dilute hydrofluoric acid is HF/H
2The solution that O mixes with 1: 10 volume ratio.
17. the manufacture method of the gate oxide of different-thickness as claimed in claim 13 wherein has component isolation structure in this substrate between this high voltage devices district and this lower voltage components district.
18. the manufacture method of the gate oxide of different-thickness as claimed in claim 17, wherein this component isolation structure comprises fleet plough groove isolation structure or field oxide.
19. the manufacture method of the gate oxide of different-thickness as claimed in claim 13, wherein the formation method of this high voltage gate oxide comprises thermal oxidation method or chemical vapour deposition technique.
20. the manufacture method of the gate oxide of different-thickness as claimed in claim 13, wherein the formation method of this low voltage gate oxide layer comprises thermal oxidation method or chemical vapour deposition technique.
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| CNB2007101087125A CN100565839C (en) | 2007-05-31 | 2007-05-31 | The manufacture method of the gate oxide of different-thickness |
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| CNB2007101087125A CN100565839C (en) | 2007-05-31 | 2007-05-31 | The manufacture method of the gate oxide of different-thickness |
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| CN102194679B (en) * | 2010-03-15 | 2013-08-14 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN105990110A (en) * | 2015-01-27 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Method of forming gate oxide layer |
| CN108257860A (en) * | 2018-01-19 | 2018-07-06 | 武汉新芯集成电路制造有限公司 | A kind of production method of grid oxic horizon |
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