CN104461962A - Loading ground test interface adapter - Google Patents
Loading ground test interface adapter Download PDFInfo
- Publication number
- CN104461962A CN104461962A CN201410704615.2A CN201410704615A CN104461962A CN 104461962 A CN104461962 A CN 104461962A CN 201410704615 A CN201410704615 A CN 201410704615A CN 104461962 A CN104461962 A CN 104461962A
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- lvds
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3808—Network interface controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Optical Communication System (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a loading ground test interface adapter which comprises a power module, a data transmitting and receiving module and a high-speed storage module. The current input of the power module is connected with the current output of an external power adapter body, and the current input of the data transmitting and receiving module and the current input of the high-speed storage module are connected with the current output of the power module respectively. The data transmitting and receiving module performs data exchange with the high-speed storage module through a GTP interface, a data transmission module performs data exchange with a load to be tested, and the high-speed storage module performs data exchange with an external master control computer through a network. The loading ground test interface adapter is used for simulating data transmission equipment, receiving and storing loading data in real time, receiving pulses per second and OC commands required for generating loads.
Description
Technical field
The present invention relates to a kind of load ground test interface adapter.
Background technology
Artificial satellite launches quantity at most, and spacecraft with fastest developing speed, is widely used in the fields such as telecommunications, meteorology, resource investigation and military surveillance.Present artificial satellite to be unified multiple part compositions such as useful load primarily of structural system, propulsion system, heat control system, power supply-distribution system, star system system, telemetering and remote control system, attitude control system, data transmission system.Wherein useful load is that in satellite, the direct subsystem performing particular task is the core of satellite, and it is the primary sub-system determining satellite performance level.And data transmission system is the crucial subsystem realizing payload information real-time Transmission between space and ground.Along with the lifting of satellite performance and index, higher requirement be there has also been to useful load and data transmission system.
Due to the singularity of satellite operation on orbit, after lift-off, very difficulty is safeguarded to it.Therefore, the ground test work before transmitting seems particularly important.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of load ground test interface adapter is provided, for simulating data transmission equipment, receiving load data and real-time storage, receive pulse per second (PPS) and produce the OC instruction of load needs.
The object of the invention is to be achieved through the following technical solutions: a kind of load ground test interface adapter, it comprises power module, number transmitting/receiving module and high speed memory modules, the electric current input of power module exports with the electric current of external power adapter and is connected, the electric current of power module exports and is connected with the electric current input of several transmitting/receiving module and high speed memory modules respectively, number transmitting/receiving module to be connected with high speed memory modules by GTP interface and to carry out exchanges data, digital transmission module is connected with tested load and carries out exchanges data, high speed memory modules to be connected with external piloting control computing machine by network and to carry out exchanges data.
The front panel of described cabinet is provided with pulse per second (PPS) input interface, pulse per second (PPS) output interface, trigger pulse output interface, 1LVDS-A interface, 1LVDS-B interface, 2LVDS-A interface, 1LVDS-B interface, OC pulse per second (PPS) interface, LAN interface, light mouth and LED state display.
The rear panel of described cabinet is provided with 24V power interface and ground interface.
Described digital transmission module comprises Transistor-Transistor Logic level imput output circuit, Transistor-Transistor Logic level driving circuit, pulse per second (PPS) input circuit, level shifting circuit, LVDS data input circuit, LVDS driving circuit, OC instruction output circuit, OC driving circuit, first processor and the second processor, first processor is connected with LAN interface by PHY chip, first processor to be connected with the second processor by EMIF interface and to carry out exchanges data, Transistor-Transistor Logic level imput output circuit to be connected with the second processor by Transistor-Transistor Logic level driving circuit and to carry out exchanges data, the output of pulse per second (PPS) input circuit is connected with the input of level shifting circuit, the output of level shifting circuit is connected with the input of the second processor, the output of LVDS data input circuit is connected with the input of LVDS driving circuit, the output of LVDS driving circuit is connected with the input of the second processor, the output of the second processor is connected with the input of OC driving circuit, the output of OC driving circuit is connected with OC instruction output circuit, second processor to be connected with high speed memory modules by GTP interface and to carry out exchanges data.
Described high speed memory modules comprises fiber optical transceiver, storer, the 3rd processor and four-processor, 3rd processor is connected with LAN interface by PHY chip, 3rd processor to be connected with four-processor by EMIF interface and to carry out exchanges data, four-processor is connected with light mouth by fiber optical transceiver, the display translation of four-processor is connected with the input of LED state display, four-processor is connected with storer carries out exchanges data, and four-processor is connected by GTP interface carries out exchanges data with number transmitting/receiving module.
Described LVDS data input circuit comprises two-way LVDS data path, and every road LVDS data path possesses two mutually redundant A channels and channel B.
Described A channel and channel B all support 1/4/8 pair of LVDS data transmission, and often pair of LVDS message transmission rate is less than or equal to 125MHz, and the speed of the highest reception data of single channel LVDS is 1.0Gbps.
Described OC instruction output circuit exports 16 tunnel load OC instructions.
The OC instruction that described OC instruction output circuit exports shows as impulse form.
Described storer is made up of 32 MLC Nand Flash.
Described first processor and the 3rd processor include the main process chip of C6455.
The second described processor and four-processor form by FPGA.
Described several transmitting/receiving modules also comprise level cache and L2 cache, and described level cache and L2 cache are all connected with the second processor and carry out exchanges data.
The invention has the beneficial effects as follows: (1) number transmitting/receiving module and high speed memory modules receive tested load data and real-time storage; (2) pulse per second (PPS) transmission circuit can receive pulse per second (PPS); (3) the OC instruction of the exportable tested load needs of OC instruction output circuit.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the front panel of cabinet in the present invention;
Fig. 2 is the schematic diagram of the rear panel of cabinet in the present invention;
Fig. 3 is the theory diagram of load ground test interface adapter of the present invention;
Fig. 4 is the theory diagram of number transmitting/receiving module in the present invention;
Fig. 5 is the theory diagram of high speed memory module of the present invention;
In figure, 1-pulse per second (PPS) input interface, 2-pulse per second (PPS) output interface, 3-trigger pulse output interface, 4-1LVDS-A interface, 5-1LVDS-B interface, 6-2LVDS-A interface, 7-1LVDS-B interface, 8-OC pulse per second (PPS) interface, 9-LAN interface, 10-light mouth, 11-LED display, 12-24V power interface, 13-ground interface.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail, but protection scope of the present invention is not limited to the following stated.
As shown in Figure 1, the front panel of described cabinet is provided with pulse per second (PPS) input interface 1, pulse per second (PPS) output interface 2, trigger pulse output interface 3,1LVDS-A interface 4,1LVDS-B interface 5,2LVDS-A interface 6,1LVDS-B interface 7, OC pulse per second (PPS) interface 8, LAN interface 9, light mouth 10 and LED state display 11.
As shown in Figure 2, the rear panel of described cabinet is provided with 24V power interface 12 and ground interface 13.
As shown in Figure 3, a kind of load ground test interface adapter, it comprises power module, number transmitting/receiving module and high speed memory modules, the electric current input of power module exports with the electric current of external power adapter and is connected, the electric current of power module exports and is connected with the electric current input of several transmitting/receiving module and high speed memory modules respectively, number transmitting/receiving module to be connected with high speed memory modules by GTP interface and to carry out exchanges data, digital transmission module is connected with tested load and carries out exchanges data, and high speed memory modules to be connected with external piloting control computing machine by network and to carry out exchanges data.
The binary channels LVDS data of reception can be carried out separate storage by described high speed memory modules simultaneously.
Described high speed memory modules can real-time error.
Described high speed memory modules can carry out unloading to the binary channels LVDS data stored simultaneously.
Data between described several transmitting/receiving module and memory module transmit the highest effective transmission speed realizing 7.2Gbps, completed the transmission of order and parameter between two modules by control signal simultaneously, memory module realizes data dump function by gigabit Ethernet, and main control computer realizes data storage, dump and system monitoring function by gigabit Ethernet.
As shown in Figure 4, described digital transmission module comprises Transistor-Transistor Logic level imput output circuit, Transistor-Transistor Logic level driving circuit, pulse per second (PPS) input circuit, level shifting circuit, LVDS data input circuit, LVDS driving circuit, OC instruction output circuit, OC driving circuit, first processor and the second processor, first processor is connected with LAN interface 9 by PHY chip, first processor to be connected with the second processor by EMIF interface and to carry out exchanges data, Transistor-Transistor Logic level imput output circuit to be connected with the second processor by Transistor-Transistor Logic level driving circuit and to carry out exchanges data, the output of pulse per second (PPS) input circuit is connected with the input of level shifting circuit, the output of level shifting circuit is connected with the input of the second processor, the output of LVDS data input circuit is connected with the input of LVDS driving circuit, the output of LVDS driving circuit is connected with the input of the second processor, the output of the second processor is connected with the input of OC driving circuit, the output of OC driving circuit is connected with OC instruction output circuit, second processor to be connected with high speed memory modules by GTP interface and to carry out exchanges data.
Described LVDS data input circuit comprises two-way LVDS data path, and every road LVDS data path possesses two mutually redundant A channels and channel B, and A channel and channel B work simultaneously.
Described A channel and channel B all support 1/4/8 pair of LVDS data transmission, and often pair of LVDS message transmission rate is less than or equal to 125MHz, and the speed of the highest reception data of single channel LVDS is 1.0Gbps.
Described OC instruction output circuit exports 16 tunnel load OC instructions.
The OC instruction that described OC instruction output circuit exports shows as impulse form, and low level conducting is effective, and ON time 160ms ± 10ms, conduction level is less than or equal to 0.4V.
Described storer is made up of 32 MLC Nand Flash.
Described first processor comprises the main process chip of C6455.
The second described processor is made up of FPGA.
Described several transmitting/receiving modules also comprise level cache and L2 cache, and described level cache and L2 cache are all connected with the second processor and carry out exchanges data.
Described several transmitting/receiving modules mainly complete reception, framing, shunting, the buffer memory of LVDS data and transmit storage, and the function such as RS422 level conversion and OC instruction output; First second processor completes the parsing of control command and the configuration of VDS receiving cable, then the LVDS data inputted from LVDS data input circuit is passed through GTP interface by LVDS real-time data transmission to high speed memory modules after a L2 cache; The effect of level cache is the data transmission channel in order to mate LVDS, realizes the conversion of clock zone and the reliable reception of data, and the effect of L2 cache is interface in order to realize Primary Transmit module and the mating of GTP transmission interface; LVDS data input circuit relates to the conversion of multi-clock zone, adopts the structure of two-level cache, realizes reliable reception and the unofficial biography of data.
As shown in Figure 5, described high speed memory modules comprises fiber optical transceiver, storer, the 3rd processor and four-processor, 3rd processor is connected with LAN interface 9 by PHY chip, 3rd processor to be connected with four-processor by EMIF interface and to carry out exchanges data, four-processor is connected with light mouth 10 by fiber optical transceiver, the display translation of four-processor is connected with the input of LED state display 11, four-processor is connected with storer carries out exchanges data, and four-processor is connected by GTP interface carries out exchanges data with number transmitting/receiving module.
Described storer is made up of 32 MLC Nand Flash.
The 3rd described processor comprises the main process chip of C6455.
Described four-processor is made up of FPGA.
Described storer comprises LASH multi-level buffer submodule, multi-stage pipeline controller and streamline top controller; FLASH multi-level buffer submodule is made up of multiple buffer unit, accept the control from streamline top controller, multi-stage pipeline controller is one group and independently controls submodule, comprise two levels: one is logical layer, complete the functions such as the interactive interfacing of this streamline and top controller, feedback of status, two is Physical layers, completes the sequential control of FLASH chip; Streamline top controller realizes top layer and controls, and realizes the functions such as streamline management.
Described high speed memory modules, according to the control command of main control computer, completes the functions such as self-test, data storage, data dump, file management; First high speed memory modules completes the parsing of main control computer control command word, and carries out the preparation receiving GTP data; Data from several transmitting/receiving module are delivered to storer by four-processor, the multistage submodule of FLASH is according to control command, data be put in corresponding buffer area, streamline top controller controls 8 level production lines and completes and store operation accordingly, and provides corresponding status information.
Described high speed memory modules also can also complete data dump operation according to the control command of main control computer, and completes framing transmission according to frame structure.
Connector of the present invention, resistance, electric capacity etc. at least take II level derate, for the withstand voltage of electric capacity, then take 50% design of Reducing Rating, for connector by electric current, at least take 70% design of Reducing Rating.
The present invention adopts and is connected on bus-bar by the method for 4 core power connectors by 24V power supply (24V), 24V ground (24V_GND); digital operation ground and analog operation ground then tandem on veneer; digitally be connected at backboard external application copper billet with protecting field and be connected in frame, ground plane limit should be greater than the border at least 3mm of cabling and components and parts.
Power connector of the present invention selects 4 core supply sockets of inverse plugging function.
Claims (9)
1. a load ground test interface adapter, it is characterized in that: it comprises power module, number transmitting/receiving module, high speed memory modules and cabinet, the electric current input of power module exports with the electric current of external power adapter and is connected, the electric current of power module exports and is connected with the electric current input of several transmitting/receiving module and high speed memory modules respectively, number transmitting/receiving module to be connected with high speed memory modules by GTP interface and to carry out exchanges data, digital transmission module is connected with tested load and carries out exchanges data, high speed memory modules to be connected with external piloting control computing machine by network and to carry out exchanges data,
The front panel of described cabinet is provided with pulse per second (PPS) input interface (1), pulse per second (PPS) output interface (2), trigger pulse output interface (3), 1LVDS-A interface (4), 1LVDS-B interface (5), 2LVDS-A interface (6), 1LVDS-B interface (7), OC pulse per second (PPS) interface (8), LAN interface (9), light mouth (10) and LED state display (11);
The rear panel of described cabinet is provided with 24V power interface (12) and ground interface (13);
Described digital transmission module comprises Transistor-Transistor Logic level imput output circuit, Transistor-Transistor Logic level driving circuit, pulse per second (PPS) input circuit, level shifting circuit, LVDS data input circuit, LVDS driving circuit, OC instruction output circuit, OC driving circuit, first processor and the second processor, first processor is connected with LAN interface (9) by PHY chip, first processor to be connected with the second processor by EMIF interface and to carry out exchanges data, Transistor-Transistor Logic level imput output circuit to be connected with the second processor by Transistor-Transistor Logic level driving circuit and to carry out exchanges data, the output of pulse per second (PPS) input circuit is connected with the input of level shifting circuit, the output of level shifting circuit is connected with the input of the second processor, the output of LVDS data input circuit is connected with the input of LVDS driving circuit, the output of LVDS driving circuit is connected with the input of the second processor, the output of the second processor is connected with the input of OC driving circuit, the output of OC driving circuit is connected with OC instruction output circuit, second processor to be connected with high speed memory modules by GTP interface and to carry out exchanges data,
Described high speed memory modules comprises fiber optical transceiver, storer, the 3rd processor and four-processor, 3rd processor is connected with LAN interface (9) by PHY chip, 3rd processor to be connected with four-processor by EMIF interface and to carry out exchanges data, four-processor is connected with Guang Kou (10) by fiber optical transceiver, the display translation of four-processor is connected with the input of LED state display (11), four-processor is connected with storer carries out exchanges data, and four-processor is connected by GTP interface carries out exchanges data with number transmitting/receiving module.
2. a kind of load ground test interface adapter according to claim 1, is characterized in that: described LVDS data input circuit comprises two-way LVDS data path, and every road LVDS data path possesses two mutually redundant A channels and channel B.
3. a kind of load ground test interface adapter according to claim 2, it is characterized in that: described A channel and channel B all support 1/4/8 pair of LVDS data transmission, often pair of LVDS message transmission rate is less than or equal to 125MHz, and the speed of the highest reception data of single channel LVDS is 1.0Gbps.
4. a kind of load ground test interface adapter according to claim 1, is characterized in that: described OC instruction output circuit exports 16 tunnel load OC instructions.
5. a kind of load ground test interface adapter according to claim 1, is characterized in that: the OC instruction that described OC instruction output circuit exports shows as impulse form.
6. a kind of load ground test interface adapter according to claim 1, is characterized in that: described storer is made up of 32 MLC Nand Flash.
7. a kind of load ground test interface adapter according to claim 1, is characterized in that: described first processor and the 3rd processor include the main process chip of C6455.
8. a kind of load ground test interface adapter according to claim 1, is characterized in that: the second described processor and four-processor form by FPGA.
9. a kind of load ground test interface adapter according to claim 1, is characterized in that: described several transmitting/receiving modules also comprise level cache and L2 cache, and described level cache and L2 cache are all connected with the second processor and carry out exchanges data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410704615.2A CN104461962B (en) | 2014-11-28 | 2014-11-28 | Loading ground test interface adapter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410704615.2A CN104461962B (en) | 2014-11-28 | 2014-11-28 | Loading ground test interface adapter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104461962A true CN104461962A (en) | 2015-03-25 |
| CN104461962B CN104461962B (en) | 2017-05-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410704615.2A Expired - Fee Related CN104461962B (en) | 2014-11-28 | 2014-11-28 | Loading ground test interface adapter |
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| Country | Link |
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| CN (1) | CN104461962B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050149645A1 (en) * | 2004-01-06 | 2005-07-07 | Hitachi, Ltd. | Storage control device |
| CN203278857U (en) * | 2013-07-17 | 2013-11-06 | 国家电网公司 | Dual-path IEC61850 message receiving and transmitting device based on CRIO (Core-Router Integrated Overlay) platform |
| CN204203955U (en) * | 2014-11-28 | 2015-03-11 | 成都龙腾中远信息技术有限公司 | A kind of load ground test interface adapter |
-
2014
- 2014-11-28 CN CN201410704615.2A patent/CN104461962B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050149645A1 (en) * | 2004-01-06 | 2005-07-07 | Hitachi, Ltd. | Storage control device |
| CN203278857U (en) * | 2013-07-17 | 2013-11-06 | 国家电网公司 | Dual-path IEC61850 message receiving and transmitting device based on CRIO (Core-Router Integrated Overlay) platform |
| CN204203955U (en) * | 2014-11-28 | 2015-03-11 | 成都龙腾中远信息技术有限公司 | A kind of load ground test interface adapter |
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| Publication number | Publication date |
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| CN104461962B (en) | 2017-05-17 |
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