CN104360960A - High-speed storage module based on load ground test interface adapter and storage method thereof - Google Patents
High-speed storage module based on load ground test interface adapter and storage method thereof Download PDFInfo
- Publication number
- CN104360960A CN104360960A CN201410708462.9A CN201410708462A CN104360960A CN 104360960 A CN104360960 A CN 104360960A CN 201410708462 A CN201410708462 A CN 201410708462A CN 104360960 A CN104360960 A CN 104360960A
- Authority
- CN
- China
- Prior art keywords
- processor
- ground test
- load ground
- interface adapter
- test interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses a high-speed storage module based on a load ground test interface adapter and a storage method thereof. The high-speed storage module based on the load ground test interface adapter comprises a PHY (Physical Layer) chip, a fiber optical transceiver, an LED (Light Emitting Diode) status display, a memory, a first processor and a second processor, wherein the first processor is connected to the PHY chip, the PHY chip is connected to an external main control computer through a network interface, the first processor is connected to the second processor through an EMIF (External Memory Interface) for data exchange, the second processor is connected to an optical port through the fiber optical transceiver, the display output of the second processor is connected to the LED status display, the second processor is connected to the memory for data exchange, and the second processor is connected to an external data transmission receiving module through an interface J3 for data exchange. The high-speed storage module based on the load ground test interface adapter and the storage method thereof have the characteristics of high-speed storage, large capacity and high reliability.
Description
Technical field
The present invention relates to a kind of high speed memory modules based on load ground test interface adapter and storage means thereof.
Background technology
Artificial satellite launches quantity at most, and spacecraft with fastest developing speed, is widely used in the fields such as telecommunications, meteorology, resource investigation and military surveillance.Present artificial satellite to be unified multiple part compositions such as useful load primarily of structural system, propulsion system, heat control system, power supply-distribution system, star system system, telemetering and remote control system, attitude control system, data transmission system.Wherein useful load is that in satellite, the direct subsystem performing particular task is the core of satellite, and it is the primary sub-system determining satellite performance level.And data transmission system is the crucial subsystem realizing payload information real-time Transmission between space and ground.Along with the lifting of satellite performance and index, higher requirement be there has also been to useful load and data transmission system.Due to the singularity of satellite operation on orbit, safeguard very difficulty to it after lift-off, therefore, the ground test work before transmitting seems particularly important.For load ground test interface adapter, the performance impact of self high speed memory modules is to the performance of whole interface adapter.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of high speed memory modules based on load ground test interface adapter and storage means thereof are provided, there is high speed storing, the feature that capacity is large and reliability is high.
The object of the invention is to be achieved through the following technical solutions: a kind of high speed memory modules based on load ground test interface adapter, it comprises PHY chip, fiber optical transceiver, LED state display, storer, first processor and the second processor, first processor is connected with PHY chip, PHY chip is connected with external piloting control computing machine by network interface, first processor to be connected with the second processor by EMIF interface and to carry out exchanges data, second processor is connected with light mouth by fiber optical transceiver, the display translation of the second processor is connected with LED state display, second processor is connected with storer and carries out exchanges data, second processor to be connected with external number transmitting/receiving module by interface J3 and to carry out exchanges data.
Described storer is the storer be made up of 32 MLC Nand Flash.
Described first processor comprises the main process chip of C6455.
The second described processor is FPGA integrated circuit.
Described storer is made up of FLASH multi-level buffer submodule, multi-stage pipeline controller and streamline top controller.
Based on a storage means for the high speed memory modules of load ground test interface adapter, it comprises the following steps:
S1. PHY chip is by the control command of network interface reception from main control computer, and sends control command to first processor;
S2. first processor is resolved described control command, and the control command after resolving is sent to the second processor, and the second processor controls its GTP and receives the preparation that submodule carries out reception data;
S3. this GTP receives submodule and receives data from several transmitting/receiving module by GTP interface and interface J3;
S4. the second processor forwards storage instruction according to the control command after parsing to corresponding streamline top controller, and streamline top controller controls the multistage submodule of corresponding FLASH according to this storage instruction and GTP is received the data temporary storage received by submodule in the buffer area of correspondence;
S5. streamline top controller controls multi-stage pipeline controller by the deposit data in buffer area to corresponding storage unit according to storing instruction, complete and store operation accordingly, meanwhile, multi-stage pipeline controller also sends corresponding storaging state information by streamline top controller to the second processor;
S6. storaging state information is fed back to main control computer by first processor by the second processor.
The invention has the beneficial effects as follows: (1) adopts MLC Nand Flash as storage medium, has high speed storing, the feature that capacity is large and reliability is high; (2) adopt GTP interface to be connected with external number transmitting/receiving module, the effective transmission speed of 7.2Gbps can be realized; (3) adopt FPGA, high speed storing can be realized and control; (4) adopt C6455 chip, storage administration practical flexibly can be realized.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the high speed memory modules that the present invention is based on load ground test interface adapter;
Fig. 2 is the process flow diagram of the storage means of the high speed memory modules that the present invention is based on load ground test interface adapter.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail, but protection scope of the present invention is not limited to the following stated.
As shown in Figure 1, a kind of high speed memory modules based on load ground test interface adapter, it comprises PHY chip, fiber optical transceiver, LED state display, storer, first processor and the second processor, first processor is connected with PHY chip, PHY chip is connected with external piloting control computing machine by network interface, first processor to be connected with the second processor by EMIF interface and to carry out exchanges data, second processor is connected with light mouth by fiber optical transceiver, the display translation of the second processor is connected with LED state display, second processor is connected with storer and carries out exchanges data, second processor to be connected with external number transmitting/receiving module by interface J3 and to carry out exchanges data.
Described storer is the storer be made up of 32 MLC Nand Flash.
Described first processor comprises the main process chip of C6455.
The second described processor is FPGA integrated circuit.
Described storer is made up of FLASH multi-level buffer submodule, multi-stage pipeline controller and streamline top controller.
Described FLASH multi-level buffer submodule is made up of multiple buffer unit, accepts the control from streamline top controller; Multi-stage pipeline controller is one group and independently controls submodule, comprises two levels: one is logical layer, completes the functions such as the interactive interfacing of this streamline and top controller, feedback of status; Two is Physical layers, completes the sequential control of FLASH chip.Streamline top controller realizes top layer and controls, and realizes the functions such as streamline management.
As shown in Figure 2, a kind of storage means of the high speed memory modules based on load ground test interface adapter, it comprises the following steps:
S1. PHY chip is by the control command of network interface reception from main control computer, and sends control command to first processor;
S2. first processor is resolved described control command, and the control command after resolving is sent to the second processor, and the second processor controls its GTP and receives the preparation that submodule carries out reception data;
S3. this GTP receives submodule and receives data from several transmitting/receiving module by GTP interface and interface J3;
S4. the second processor forwards storage instruction according to the control command after parsing to corresponding streamline top controller, and streamline top controller controls the multistage submodule of corresponding FLASH according to this storage instruction and GTP is received the data temporary storage received by submodule in the buffer area of correspondence;
S5. streamline top controller controls multi-stage pipeline controller by the deposit data in buffer area to corresponding storage unit according to storing instruction, complete and store operation accordingly, meanwhile, multi-stage pipeline controller also sends corresponding storaging state information by streamline top controller to the second processor;
S6. storaging state information is fed back to main control computer by first processor by the second processor.
In Fig. 2, the complete separate, stored of data of GTP0 and GTP1, ensures that number passes the reliable and stable of storage system; In addition, the multi-stage pipeline of FLASH array controls to ensure that the real-time reliable memory of high-speed data.
Claims (6)
1. the high speed memory modules based on load ground test interface adapter, it is characterized in that: it comprises PHY chip, fiber optical transceiver, LED state display, storer, first processor and the second processor, first processor is connected with PHY chip, PHY chip is connected with external piloting control computing machine by network interface, first processor to be connected with the second processor by EMIF interface and to carry out exchanges data, second processor is connected with light mouth by fiber optical transceiver, the display translation of the second processor is connected with LED state display, second processor is connected with storer and carries out exchanges data, second processor to be connected with external number transmitting/receiving module by interface J3 and to carry out exchanges data.
2. a kind of high speed memory modules based on load ground test interface adapter according to claim 1, is characterized in that: described storer is the storer be made up of 32 MLC Nand Flash.
3. a kind of high speed memory modules based on load ground test interface adapter according to claim 1, is characterized in that: described first processor comprises the main process chip of C6455.
4. a kind of high speed memory modules based on load ground test interface adapter according to claim 1, is characterized in that: the second described processor is FPGA integrated circuit.
5. a kind of high speed memory modules based on load ground test interface adapter according to claim 1, is characterized in that: described storer is made up of FLASH multi-level buffer submodule, multi-stage pipeline controller and streamline top controller.
6., based on a storage means for the high speed memory modules of load ground test interface adapter, it is characterized in that: it comprises the following steps:
S1. PHY chip is by the control command of network interface reception from main control computer, and sends control command to first processor;
S2. first processor is resolved described control command, and the control command after resolving is sent to the second processor, and the second processor controls its GTP and receives the preparation that submodule carries out reception data;
S3. this GTP receives submodule and receives data from several transmitting/receiving module by GTP interface and interface J3;
S4. the second processor forwards storage instruction according to the control command after parsing to corresponding streamline top controller, and streamline top controller controls the multistage submodule of corresponding FLASH according to this storage instruction and GTP is received the data temporary storage received by submodule in the buffer area of correspondence;
S5. streamline top controller controls multi-stage pipeline controller by the deposit data in buffer area to corresponding storage unit according to storing instruction, complete and store operation accordingly, meanwhile, multi-stage pipeline controller also sends corresponding storaging state information by streamline top controller to the second processor;
S6. storaging state information is fed back to main control computer by first processor by the second processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410708462.9A CN104360960A (en) | 2014-11-28 | 2014-11-28 | High-speed storage module based on load ground test interface adapter and storage method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410708462.9A CN104360960A (en) | 2014-11-28 | 2014-11-28 | High-speed storage module based on load ground test interface adapter and storage method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104360960A true CN104360960A (en) | 2015-02-18 |
Family
ID=52528224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410708462.9A Pending CN104360960A (en) | 2014-11-28 | 2014-11-28 | High-speed storage module based on load ground test interface adapter and storage method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104360960A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104598163A (en) * | 2014-11-28 | 2015-05-06 | 成都龙腾中远信息技术有限公司 | High-speed storage module storage method based on load ground test interface adapter |
| CN106649142A (en) * | 2016-12-02 | 2017-05-10 | 北京航天长征飞行器研究所 | High-speed memorizer with outage renew function |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080147985A1 (en) * | 2006-12-13 | 2008-06-19 | International Business Machines Corporation | Method and System for Purging Data from a Controller Cache |
| CN101980139A (en) * | 2010-11-12 | 2011-02-23 | 北京理工大学 | NAND-based memory plate |
| CN203950033U (en) * | 2014-05-26 | 2014-11-19 | 中国电子科技集团公司第三十八研究所 | The equipment of high-speed record radar return data |
| CN104598163A (en) * | 2014-11-28 | 2015-05-06 | 成都龙腾中远信息技术有限公司 | High-speed storage module storage method based on load ground test interface adapter |
-
2014
- 2014-11-28 CN CN201410708462.9A patent/CN104360960A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080147985A1 (en) * | 2006-12-13 | 2008-06-19 | International Business Machines Corporation | Method and System for Purging Data from a Controller Cache |
| CN101980139A (en) * | 2010-11-12 | 2011-02-23 | 北京理工大学 | NAND-based memory plate |
| CN203950033U (en) * | 2014-05-26 | 2014-11-19 | 中国电子科技集团公司第三十八研究所 | The equipment of high-speed record radar return data |
| CN104598163A (en) * | 2014-11-28 | 2015-05-06 | 成都龙腾中远信息技术有限公司 | High-speed storage module storage method based on load ground test interface adapter |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104598163A (en) * | 2014-11-28 | 2015-05-06 | 成都龙腾中远信息技术有限公司 | High-speed storage module storage method based on load ground test interface adapter |
| CN104598163B (en) * | 2014-11-28 | 2017-10-17 | 成都龙腾中远信息技术有限公司 | A kind of storage method of the high speed memory modules based on load ground test interface adapter |
| CN106649142A (en) * | 2016-12-02 | 2017-05-10 | 北京航天长征飞行器研究所 | High-speed memorizer with outage renew function |
| CN106649142B (en) * | 2016-12-02 | 2019-09-06 | 北京航天长征飞行器研究所 | A kind of high-speed memory renewing function with power-off |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110751280A (en) | Configurable convolution accelerator applied to convolutional neural network | |
| US8521929B2 (en) | Virtual serial port management system and method | |
| CN108804376B (en) | Small heterogeneous processing system based on GPU and FPGA | |
| CN104731569B (en) | A kind of data processing method and relevant device | |
| CN106301859A (en) | A kind of manage the method for network interface card, Apparatus and system | |
| CN102833237B (en) | InfiniBand protocol conversion method and system based on bridging | |
| CN102891813A (en) | Ethernet port architecture supporting multiple transmission modes | |
| CN110837093B (en) | Remote sensing micro-nano satellite integrated information processing platform | |
| CN102122256A (en) | Pipe-type communication method and system for interprocess communication | |
| CN106648817A (en) | Cross-platform data object transmission method | |
| CN104360960A (en) | High-speed storage module based on load ground test interface adapter and storage method thereof | |
| CN104192300B (en) | A kind of flight control system and method | |
| CN114742000B (en) | SoC chip verification system, method and device based on FPGA cluster | |
| CN104598163A (en) | High-speed storage module storage method based on load ground test interface adapter | |
| CN104598194A (en) | Initializing method and circuit of head and tail pointer chain table storage | |
| CN109919826B (en) | Graph data compression method for graph computation accelerator and graph computation accelerator | |
| CN103970714B (en) | For the device and method and its reconfigurable processor of sharing functionality logic | |
| CN103901881A (en) | Device compatible with multiple test states for carrier rocket equivalent device system | |
| CN105204581A (en) | Satellite-borne beam controlling computer | |
| US9449714B2 (en) | Flexible interrupt generation mechanism | |
| CN104898775A (en) | Calculation apparatus, storage device, network switching device and computer system architecture | |
| CN107391044A (en) | A kind of creation method and creating device of cloud hard disk | |
| CN109949202B (en) | Parallel graph computation accelerator structure | |
| CN103746941A (en) | Board-level interconnected big data all-in-one machine | |
| CN104239084A (en) | Implementing method for automatically loading DSP (digital signal processor) procedures |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150218 |