CN104461962B - Loading ground test interface adapter - Google Patents
Loading ground test interface adapter Download PDFInfo
- Publication number
- CN104461962B CN104461962B CN201410704615.2A CN201410704615A CN104461962B CN 104461962 B CN104461962 B CN 104461962B CN 201410704615 A CN201410704615 A CN 201410704615A CN 104461962 B CN104461962 B CN 104461962B
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- China
- Prior art keywords
- output
- processor
- input
- lvds
- interfaces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3808—Network interface controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
Abstract
The invention discloses a loading ground test interface adapter which comprises a power module, a data transmitting and receiving module and a high-speed storage module. The current input of the power module is connected with the current output of an external power adapter body, and the current input of the data transmitting and receiving module and the current input of the high-speed storage module are connected with the current output of the power module respectively. The data transmitting and receiving module performs data exchange with the high-speed storage module through a GTP interface, the data transmitting and receiving module performs data exchange with a load to be tested, and the high-speed storage module performs data exchange with an external master control computer through a network. The loading ground test interface adapter is used for simulating data transmission equipment, receiving and storing loading data in real time, receiving pulses per second and OC commands required for generating loads.
Description
Technical field
The present invention relates to a kind of load ground test interface adapter.
Background technology
Artificial satellite be transmitting quantity at most, spacecraft with fastest developing speed, be widely used in telecommunications, meteorology, resource investigation and
The fields such as military surveillance.Present artificial satellite is main by structural system, propulsion system, heat control system, power supply-distribution system, star thing system
The some such as system, telemetering and remote control system, attitude control system, data transmission system and payload are constituted.Wherein have
The core that the subsystem that load is direct execution particular task in satellite is satellite is imitated, it is to determine satellite performance level
Primary sub-system.And data transmission system is to realize that the key of payload information real-time Transmission between space and ground is divided to be
System.With the lifting of satellite performance and index, requirement higher there has also been to payload and data transmission system.
Due to the particularity of satellite operation on orbit, extremely difficult is safeguarded to it after lift-off.Therefore, the ground test before transmitting
Work is particularly important.
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art, there is provided a kind of load ground test interface adapter, use
In simulation data transmission equipment, load data and real-time storage are received, receive the OC instructions that pulse per second (PPS) and generation load need.
The purpose of the present invention is achieved through the following technical solutions：A kind of load ground test interface adapter, it
Including power module, number transmitting/receiving module and high speed memory modules, electric current input and the external power adapter of power module
Electric current output connection, the electric current output of power module is input into the electric current of several transmitting/receiving modules and high speed memory modules connects respectively
Connect, number transmitting/receiving module is connected with high speed memory modules by GTP interfaces and carries out data exchange, counts transmitting/receiving module and tested load
Lotus connection carries out data exchange, and high speed memory modules are connected with external piloting control computer by network and carry out data exchange.
Pulse per second (PPS) input interface, pulse per second (PPS) output interface, trigger pulse output are provided with the front panel of described cabinet
Interface, 1LVDS-A interfaces, 1LVDS-B interfaces, 2LVDS-A interfaces, 1LVDS-B interfaces, OC pulse per second (PPS)s interface, LAN interface, light
Mouth and LED state display.
24V power interfaces and ground interface are provided with the rear board of described cabinet.
Described several transmitting/receiving modules include Transistor-Transistor Logic level imput output circuit, Transistor-Transistor Logic level drive circuit, pulse per second (PPS) input
Circuit, level shifting circuit, LVDS data input circuits, LVDS drive circuits, OC instructions output circuit, OC drive circuits, the
One processor and second processing device, first processor are connected by PHY chip with LAN interface, and first processor is connect by EMIF
Mouth is connected with second processing device and carries out data exchange, and Transistor-Transistor Logic level imput output circuit is by Transistor-Transistor Logic level drive circuit and second
Reason device connection carries out data exchange, and the output of pulse per second (PPS) input circuit is connected with the input of level shifting circuit, level conversion electricity
The output on road is connected with the input of second processing device, and the output of LVDS data input circuits connects with the input of LVDS drive circuits
Connect, the output of LVDS drive circuits is connected with the input of second processing device, the output of second processing device is defeated with OC drive circuits
Enter connection, the output of OC drive circuits is connected with OC instruction output circuits, and second processing device is by GTP interfaces and high speed storing mould
Block connection carries out data exchange.
Described high speed memory modules include fiber optical transceiver, memory, the 3rd processor and fourth processor, at the 3rd
Reason device is connected by PHY chip with LAN interface, and the 3rd processor is connected with fourth processor by EMIF interfaces and carries out data friendship
Change, fourth processor is connected by fiber optical transceiver with optical port, the display output of fourth processor is defeated with LED state display
Enter connection, fourth processor is connected with memory carries out data exchange, fourth processor is by GTP interfaces and number transmitting/receiving module
Connection carries out data exchange.
Described LVDS data input circuits include two-way LVDS data paths, possess two per road LVDS data paths mutually
It is the A channel and channel B of backup.
Described A channel and channel B support that 1/4/8 pair of LVDS data transfer, each pair LVDS message transmission rates are less than
Equal to 125MHz, the speed that single channel LVDS highests receive data is 1.0Gbps.
The described road-load lotus OC instructions of OC instruction output circuits output 16.
The OC instructions of described OC instruction output circuit outputs show as impulse form.
Described memory is made up of 32 MLC Nand Flash.
Described first processor and the 3rd processor include C6455 main process task chips.
Described second processing device and fourth processor is constituted by FPGA.
Described several transmitting/receiving modules also include level cache and L2 cache, and described level cache and L2 cache is equal
Being connected with second processing device carries out data exchange.
The beneficial effects of the invention are as follows：（1）It is simultaneously real that number transmitting/receiving module and high speed memory modules receive tested load data
When store；（2）Pulse per second (PPS) transmission circuit can receive pulse per second (PPS)；（3）The OC that the exportable tested load of OC instruction output circuits needs
Instruction.
Brief description of the drawings
Fig. 1 is the schematic diagram of the front panel of cabinet in the present invention；
Fig. 2 is the schematic diagram of the rear board of cabinet in the present invention；
Fig. 3 is the theory diagram of load ground test interface adapter of the present invention；
Fig. 4 is the theory diagram of number transmitting/receiving module in the present invention；
Fig. 5 is the theory diagram of high speed memory module of the present invention；
In figure, 1- pulse per second (PPS) input interfaces, 2- pulse per second (PPS) output interfaces, 3- trigger pulse output interfaces, 4-1LVDS-A connects
Mouthful, 5-1LVDS-B interfaces, 6-2LVDS-A interfaces, 7-1LVDS-B interfaces, 8-OC pulse per second (PPS) interfaces, 9-LAN interfaces, 10- light
Mouthful, 11-LED displays, 12-24V power interfaces, 13- ground interfaces.
Specific embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
It is as described below.
As shown in figure 1, be provided with the front panel of described cabinet pulse per second (PPS) input interface 1, pulse per second (PPS) output interface 2,
Trigger pulse output interface 3,1LVDS-A interfaces 4,1LVDS-B interfaces 5,2LVDS-A interfaces 6,1LVDS-B interfaces 7, OC second arteries and veins
Rush interface 8, LAN interface 9, optical port 10 and LED state display 11.
As shown in Fig. 2 being provided with 24V power interfaces 12 and ground interface 13 on the rear board of described cabinet.
As shown in figure 3, a kind of load ground test interface adapter, it includes power module, number transmitting/receiving module and height
Fast memory module, the electric current input of power module is connected with the electric current output of external power adapter, and the electric current of power module is defeated
Go out and be connected with the electric current input of several transmitting/receiving modules and high speed memory modules respectively, number transmitting/receiving module is by GTP interfaces and height
Fast memory module connection carries out data exchange, and number transmitting/receiving module is connected with tested load and carries out data exchange, high speed storing mould
Block is connected with external piloting control computer by network and carries out data exchange.
The binary channels LVDS data of reception can be carried out separate storage by described high speed memory modules simultaneously.
Described high speed memory modules can real-time error.
Described high speed memory modules can be while the binary channels LVDS data to storing carry out unloading.
Data transfer highest between described several transmitting/receiving modules and memory module can realize effective transmission of 7.2Gbps
Speed, while completing order and the transmission of parameter by control signal between two modules, memory module passes through gigabit Ethernet
Data dump function is realized, main control computer realizes data storage, dump and system monitoring function by gigabit Ethernet.
As shown in figure 4, described several transmitting/receiving modules include Transistor-Transistor Logic level imput output circuit, Transistor-Transistor Logic level drive circuit,
Pulse per second (PPS) input circuit, level shifting circuit, LVDS data input circuits, LVDS drive circuits, OC instructions output circuit, OC drive
Dynamic circuit, first processor and second processing device, first processor are connected by PHY chip with LAN interface 9, first processor
Being connected with second processing device by EMIF interfaces carries out data exchange, and Transistor-Transistor Logic level imput output circuit drives electricity by Transistor-Transistor Logic level
Road is connected with second processing device carries out data exchange, and the output of pulse per second (PPS) input circuit is connected with the input of level shifting circuit,
The output of level shifting circuit is connected with the input of second processing device, output and the LVDS drive circuits of LVDS data input circuits
Input connection, the output of LVDS drive circuits be connected with the input of second processing device, the output of second processing device and OC drivings
The input connection of circuit, the output of OC drive circuits is connected with OC instruction output circuits, and second processing device is by GTP interfaces and height
Fast memory module connection carries out data exchange.
Described LVDS data input circuits include two-way LVDS data paths, possess two per road LVDS data paths mutually
For the A channel and channel B of backup, A channel and channel B work simultaneously.
Described A channel and channel B support that 1/4/8 pair of LVDS data transfer, each pair LVDS message transmission rates are less than
Equal to 125MHz, the speed that single channel LVDS highests receive data is 1.0Gbps.
The described road-load lotus OC instructions of OC instruction output circuits output 16.
The OC instructions of described OC instruction output circuit outputs show as impulse form, and low level conducting is effective, during conducting
Between 160ms ± 10ms, conduction level be less than or equal to 0.4V.
Described memory is made up of 32 MLC Nand Flash.
Described first processor includes C6455 main process task chips.
Described second processing device is made up of FPGA.
Described several transmitting/receiving modules also include level cache and L2 cache, and described level cache and L2 cache is equal
Being connected with second processing device carries out data exchange.
Described several transmitting/receiving modules mainly complete reception, framing, shunting, caching and the transmission storage of LVDS data, with
And the function such as RS422 level conversions and OC instruction outputs；Second processing device completes the parsing of control command first and VDS receives logical
The configuration in road, the LVDS data that then will be input into from LVDS data input circuits by GTP interfaces after a L2 cache by being incited somebody to action
LVDS real-time data transmissions are to high speed memory modules；The effect of level cache is in order to match the data transmission channel of LVDS, in fact
The conversion of existing clock zone and the reliable reception of data, the effect of L2 cache be in order to realize the interface of Primary Transmit module with
The matching of GTP coffrets；LVDS data input circuits are related to the conversion of multi-clock zone, real using the structure of two-level cache
The reliable reception and unofficial biography of existing data.
As shown in figure 5, described high speed memory modules include fiber optical transceiver, memory, the 3rd processor and the everywhere
Reason device, the 3rd processor is connected by PHY chip with LAN interface 9, and the 3rd processor is connected by EMIF interfaces with fourth processor
Row data exchange is tapped into, fourth processor is connected by fiber optical transceiver with optical port 10, the display output and LED of fourth processor
The input connection of status displays 11, fourth processor is connected with memory carries out data exchange, and fourth processor is connect by GTP
Mouth is connected with number transmitting/receiving module and carries out data exchange.
Described memory is made up of 32 MLC Nand Flash.
The 3rd described processor includes C6455 main process task chips.
Described fourth processor is made up of FPGA.
Described memory includes the control of LASH multi-level buffers submodule, multi-stage pipeline controller and streamline top layer
Device；FLASH multi-level buffers submodule is made up of multiple buffer units, receives the control from streamline top controller, many
Level production line controller is one group of control submodule of independence, comprising two levels：One is logical layer, completes the streamline with top
The functions such as interactive interfacing, the feedback of status of layer controller, two is physical layer, completes the SECO of FLASH chip；Streamline top
Layer controller realizes top layer control, realizes the functions such as flowing water wire management.
Described high speed memory modules complete self-test, data storage, data turn according to the control command of main control computer
The functions such as storage, file management；High speed memory modules complete the parsing of main control computer control command word first, and carry out reception
The preparation of GTP data；Fourth processor by the data transfer from several transmitting/receiving modules to memory, FLASH multistage submodules
According to control command, place data into corresponding buffer area, it is corresponding that streamline top controller controls 8 level production lines to complete
Storage operation, and provide corresponding status information.
Described high speed memory modules can also can also complete data dump operation according to the control command of main control computer,
And complete framing transmission according to frame structure.
Connector of the invention, resistance, electric capacity etc. at least take II grades of drop volume, for the pressure voltage of electric capacity, then take 50%
Design of Reducing Rating, for connector by electric current, at least takes 70% design of Reducing Rating.
The present invention using by the method for 4 core power connectors by 24V power supplys（24V）, 24V ground (24V_GND) be connected to
On busbar, digital operation ground with simulation the place of working then tandem on veneer, digitally with protecting field in backboard external application copper billet
Connect and be connected in frame, ground plane side should be greater than the border at least 3mm of cabling and component.
Power connector of the invention is from the 4 core power outlets for having counnter attack plugging function.
Claims (5)
1. a kind of load ground test interface adapter, it is characterised in that：It includes power module, number transmitting/receiving module, high speed
Memory module and cabinet, the electric current input of power module are connected with the electric current output of external power adapter, the electricity of power module
Stream output is connected with the electric current input of several transmitting/receiving modules and high speed memory modules respectively, and number transmitting/receiving module passes through GTP interfaces
Being connected with high speed memory modules carries out data exchange, and number transmitting/receiving module is connected with tested load and carries out data exchange, deposits at a high speed
Storage module is connected with external piloting control computer by network and carries out data exchange；
Pulse per second (PPS) input interface is provided with the front panel of described cabinet（1）, pulse per second (PPS) output interface（2）, trigger pulse it is defeated
Outgoing interface（3）, 1LVDS-A interfaces（4）, 1LVDS-B interfaces（5）, 2LVDS-A interfaces（6）, 1LVDS-B interfaces（7）, OC seconds arteries and veins
Rush interface（8）, LAN interface（9）, optical port（10）With LED state display（11）；
24V power interfaces are provided with the rear board of described cabinet（12）And ground interface（13）；
Described several transmitting/receiving modules include Transistor-Transistor Logic level imput output circuit, Transistor-Transistor Logic level drive circuit, pulse per second (PPS) input circuit,
Level shifting circuit, LVDS data input circuits, LVDS drive circuits, OC instructions output circuit, OC drive circuits, the first treatment
Device and second processing device, first processor pass through PHY chip and LAN interface（9）Connection, first processor by EMIF interfaces with
The connection of second processing device carries out data exchange, and Transistor-Transistor Logic level imput output circuit is by Transistor-Transistor Logic level drive circuit and second processing device
Connection carries out data exchange, and the output of pulse per second (PPS) input circuit is connected with the input of level shifting circuit, level shifting circuit
Output is connected with the input of second processing device, and the output of LVDS data input circuits is connected with the input of LVDS drive circuits,
The output of LVDS drive circuits is connected with the input of second processing device, and the output of second processing device connects with the input of OC drive circuits
Connect, the output of OC drive circuits is connected with OC instruction output circuits, and second processing device is connected by GTP interfaces with high speed memory modules
Tap into row data exchange；
Described high speed memory modules include fiber optical transceiver, memory, the 3rd processor and fourth processor, the 3rd processor
By PHY chip and LAN interface（9）Connection, the 3rd processor is connected with fourth processor by EMIF interfaces and carries out data friendship
Change, fourth processor passes through fiber optical transceiver and optical port（10）Connection, display output and the LED state display of fourth processor
（11）Input connection, fourth processor be connected with memory carries out data exchange, fourth processor by GTP interfaces with count biography
Receiver module connection carries out data exchange；Described LVDS data input circuits include two-way LVDS data paths, per road LVDS
Data path possesses two mutually redundant A channels and channel B；Described A channel and channel B support 1/4/8 pair of LVDS number
According to transmission, each pair LVDS message transmission rates are less than or equal to 125MHz, and the speed that single channel LVDS highests receive data is
1.0Gbps；
The OC instructions of described OC instruction output circuit outputs show as impulse form；
Described several transmitting/receiving modules also include level cache and L2 cache, and described level cache and L2 cache are with the
The connection of two processors carries out data exchange.
2. a kind of load ground test interface adapter according to claim 1, it is characterised in that：Described OC instructions are defeated
Go out the road-load lotus OC instructions of circuit output 16.
3. a kind of load ground test interface adapter according to claim 1, it is characterised in that：Described memory by
32 MLC Nand Flash compositions.
4. a kind of load ground test interface adapter according to claim 1, it is characterised in that：The first described treatment
Device and the 3rd processor include C6455 main process task chips.
5. a kind of load ground test interface adapter according to claim 1, it is characterised in that：Described second processing
Device and fourth processor are constituted by FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410704615.2A CN104461962B (en) | 2014-11-28 | 2014-11-28 | Loading ground test interface adapter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410704615.2A CN104461962B (en) | 2014-11-28 | 2014-11-28 | Loading ground test interface adapter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104461962A CN104461962A (en) | 2015-03-25 |
| CN104461962B true CN104461962B (en) | 2017-05-17 |
Family
ID=52908044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410704615.2A Expired - Fee Related CN104461962B (en) | 2014-11-28 | 2014-11-28 | Loading ground test interface adapter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104461962B (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4401788B2 (en) * | 2004-01-06 | 2010-01-20 | 株式会社日立製作所 | Storage controller |
| CN203278857U (en) * | 2013-07-17 | 2013-11-06 | 国家电网公司 | Dual-path IEC61850 message receiving and transmitting device based on CRIO (Core-Router Integrated Overlay) platform |
| CN204203955U (en) * | 2014-11-28 | 2015-03-11 | 成都龙腾中远信息技术有限公司 | A kind of load ground test interface adapter |
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2014
- 2014-11-28 CN CN201410704615.2A patent/CN104461962B/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CN104461962A (en) | 2015-03-25 |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
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Granted publication date: 20170517 Termination date: 20171128 |