CN104426493A

CN104426493A - Apparatus and methods for chopper amplifiers

Info

Publication number: CN104426493A
Application number: CN201410418603.3A
Authority: CN
Inventors: 周捷; A·J·卡尔布; M·D·莱西格
Original assignee: Analog Devices Inc
Current assignee: Analog Devices Inc
Priority date: 2013-08-23
Filing date: 2014-08-22
Publication date: 2015-03-18
Anticipated expiration: 2034-08-22
Also published as: CN104426493B

Abstract

Apparatus and methods for chopper amplifiers are provided herein. In certain configurations, a chopper amplifier includes at least one differential transistor bank including a selection circuit and a plurality of transistors. The selection circuit can select a first portion of the transistors for operation in a first transistor group and a second portion of the transistors for operation in a second transistor group. During calibration, the chopper amplifier's input offset can be observed for different transistor configurations of the differential transistor banks. Although the transistors of a particular bank can be designed to have about the same drive-strength and/or geometry, the chopper amplifier can have a different input offset in different transistor configurations due to manufacturing mismatch between transistors, such as process variation. The chopper amplifier can be programmed to operate with the selected transistor configurations of the differential transistor banks to provide the amplifier with low input offset.

Description

The apparatus and method of chopper amplifier

Technical field

Embodiments of the invention relate to electronic equipment, and more specifically, relate to chopper amplifier.

Background technology

Amplifier (such as, operational amplifier or instrument amplifier) can comprise chopper circuit, for reducing the input offset voltage of amplifier.Such as, in the chopper amplifier of routine, input chopping switch can be used to cut during chopping operation and chops or the input signal of resonance-amplifier, thus the frequency of the input signal of up-conversion amplifier.In addition, amplifier can comprise filter, and for filtering the input deviation of described amplifier, it can independent of chopped input signal in frequency.Amplifier can also comprise output chopping switch, for the frequency of demodulation or down-conversion chopped input signal during exporting chopping operation.

Although comprise the input offset voltage that chopper circuit can reduce amplifier in the amplifier, copped wave also can generate ripple (ripple) in chopping frequency and the output signal of its harmonic wave at this amplifier.

There are the needs for having the amplifier improving performance.In addition, the chopper amplifier to having the output voltage ripple reducing input offset voltage and reduction is also needed.

Summary of the invention

In one embodiment, a kind of device comprises: programmable storage, is configured to generation first control signal, and a chopper amplifier, is configured to amplify differential input voltage signal to produce output signal.Chopper amplifier comprises: the first difference transistor pond comprising selection circuit and multiple transistor.Selection circuit is configured to the multiple transistors selecting Part I based on the first control signal, for the operation in the first transistor group, and selects multiple transistors of Part II based on the first control signal, for the operation in transistor seconds group.The input offset voltage of chopper amplifier is different according to the transistor selection in the first and second transistor groups.

In another embodiment, a kind of method of calibrating chopper amplifier is provided.The method comprises: observe each the input offset voltage of chopper amplifier for the multiple selected transistor arrangement in the first difference transistor pond of Chopper amplifiers.First difference transistor pond comprises multiple transistor, and selected transistor arrangement comprises: the various combination of multiple transistor in the first transistor group and the second group transistor group.The method comprises further: based on described input offset voltage observation and select transistor arrangement, and store in programmable storage and correspond to the data of selected transistor arrangement.

Accompanying drawing explanation

Figure 1A is the schematic block diagram of the embodiment that integrated circuit (IC) is shown.

Figure 1B and 1C is the schematic block diagram in the difference transistor pond according to an embodiment.

Fig. 2-7 is circuit diagrams of the chopper amplifier according to various embodiment.

Fig. 8 A-8D is the circuit diagram in the difference transistor pond according to various embodiment.

Fig. 9 is the circuit diagram of an execution mode of chopper circuit.

Figure 10 is the circuit diagram of the chopper amplifier according to another embodiment.

Figure 11 is the circuit diagram of the chopper amplifier according to another embodiment.

Figure 12 A is the circuit diagram in the copped wave difference transistor pond according to an embodiment.

Figure 12 B is the circuit diagram in the copped wave difference transistor pond according to another embodiment.

Figure 13 is the flow chart of the method according to an embodiment calibration chopper amplifier.

Figure 14 is the flow chart of the method according to another embodiment calibration chopper amplifier.

Embodiment

The various descriptions of specific embodiment of the present invention are proposed in the following detailed description of some embodiment.But the present invention can be embodied in multiple different mode, as claim define and contain.In this manual, with reference to accompanying drawing, wherein similar Reference numeral can indicate identical or functionally similar element.

For some application of such as high-precision amplification, wish that there is the biased amplifier of low input.Be biased to help to realize low input, some amplifier can use auto zero and/or copped wave plan.

Although it is biased to use auto zero and/or copped wave can reduce input in the amplifier, this technology can have shortcoming.Such as, because broadband noise aliasing enters auto zero frequency range, auto zero can produce relatively high low-frequency noise power spectral density (PSD).

In addition, the input that copped wave can reduce amplifier is biased, but owing to inputting biased modulation, also can introduce pulsation in the output signal of amplifier.Such as, the input chopping switch of Chopper amplifiers can operate to be regulated by chopping frequency or the frequency spectrum of up-conversion input signal, and the output chopping switch of Chopper amplifiers can operate with by chopping frequency demodulation or the frequency spectrum to down-conversion amplification input signal.But the input amplifying stage of amplifier can be positioned in the signal path of the chopper amplifier after input chopping switch, and input is biased and can not be modulated by input chopping switch thus.But input is biased will be output chopping switch modulation or upconvert, it can cause the ripple in output signal at chopping frequency and its harmonic wave.

Although low pass filter may be provided in the signal path of chopper amplifier, with decay and the biased frequency component be associated of input, low pass filter can filtering input be biased and/or can reduce the bandwidth of the chopper amplifier lower than chopping frequency by halves.In addition, even if when chopping frequency is selected as relatively high to provide relatively wide bandwidth, high chopping frequency can increase the relevant distortion (artifact) of charge injection, and can cause the stabilization time and the increase of the power consumption thing followed that reduce amplifier.In other configurations, bandwidth can be expanded to comprise multiple amplification path by configuration chopper amplifier.But such configuration can comprise the limit of additional transfer function and/or can comprise the high bandwidth path having high power consumption, occupy a large amount of chip area, and adds the complexity of design.In addition, such configuration can suffer the unmatched distortion in path.

Be provided for the apparatus and method of chopper amplifier in this article.In some configuration, chopper amplifier comprises at least one difference transistor pond, the pond be such as associated with the difference cascode transistor of differential input transistor to, differential load transistor or amplifier.Each difference transistor pond can comprise selection circuit and multiple transistor, and selection circuit can select the Part I of the transistor for operating in the first transistor group and the Part II of transistor for operating in transistor seconds group.Between alignment epoch, the input of Chopper amplifiers is biased can be carried out observing or measuring for the different crystal pipe configuration in difference transistor pond.Although the transistor of particular pool can be designed as have approximately identical driver intensity and/or geometry, chopper amplifier can have different inputs and be biased in different transistor arrangement.Such as, before copped wave, chopper amplifier can have different input offset voltage amounts in different transistor arrangement.The amount of bias of input chopper amplifier can change along with different transistor arrangement, due to the manufacture mismatch between transistor, and the manufacture mismatch be such as associated with change in process.

Although the input that chopper amplifier can show relatively small amount when amplifier copped wave is biased, the input offset voltage of the amplifier before copped wave can convert output voltage ripple to by chopping operation.Therefore, before copped wave, it is desirable that chopper amplifier has low input offset voltage.Therefore, Chopper amplifiers herein can be programmed to the selected transistor arrangement operating difference transistor pond, has the biased amplifier of low input to provide.

Chopper amplifier herein can realize low input and be biased, and relative to some, other input is biased Reduced measure, can produce relatively little impact to the size of amplifier, power consumption and/or amplification characteristic.In addition, some chopper amplifier of this paper can have little output ripple, little input bias current, low input offset drift and/or low flash noise.

There is the general introduction of the chopper amplifier that low input is biased

Figure 1A is the schematic block diagram of the embodiment that integrated circuit (IC) 20 is shown.Integrated circuit 20 comprises programmable storage 9 and chopper amplifier 10.

Programmable storage 9 can receive programming signal PGRM, and it may be used for the state of programming programmable storage 9.Although Figure 1A illustrates that programmable storage 9 is as reception programming signal, programmable storage 9 can receive extra programming signal and/or programming signal PGRM can comprise multiple position.Programmable storage 9 can generate control signal CTL based on the state of described programmable storage.Although Figure 1A illustrates that programmable storage 9 is for generation control signal, programmable storage 9 can produce additional control signal.In some embodiments, programmable storage 9 can generate multiple control signal and/or control signal CTL can comprise multiple position.

Shown chopper amplifier 10 comprises input chopper circuit 1, exports chopper circuit 2 and difference transistor pond 4.Chopper amplifier 10 can reception control signal CTL and input signal, is just corresponding to or non-inverting input voltage V _iN+with negative or reverse inter-input-ing voltage V _iN-between difference.In addition, this chopper amplifier 10 can amplification input signal, to produce output voltage V _oUT.

Although Figure 1A shows wherein chopper amplifier 10 and produces the configuration of single ended output voltage signal, described Chopper amplifiers 10 can be used for producing other output signals, comprise such as, differential output voltage signal, Single-end output current signal, differential output current signal, or their combination.In addition, although Figure 1A illustrates the Chopper amplifiers 10 in open-loop configuration, Chopper amplifiers 10 can be used for closed loop.

Input and output chopper circuit 1,2 can be used for performing input and output chopping operation, to reduce the output voltage V be associated with the input offset voltage of Chopper amplifiers to input signal respectively _oUTin error.Before the input amplifying stage by chopper amplifier 10 amplifies, input chopper circuit 1 can be used for cutting and chops or modulating input signal, export chopper circuit 2 to can be used to cut and chop or differential input signal that demodulation is amplified, thus can amplify further and/or otherwise process to produce output voltage V _oUT.

Difference transistor pond 4 can comprise at least the first terminal, the second terminal, selection circuit and multiple transistor.Described multiple transistor can be selected individually for operating in the first transistor group or the electronic circuit relevant to the first terminal, or for operating in transistor seconds group or the electronic circuit relevant to the second terminal.Difference transistor pond 4 can be placed in the amplification path along Chopper amplifiers 10.Such as, in some embodiments, difference transistor pond 4 can as the differential input transistor of chopper amplifier 10, differential load transistor or differential cascade transistor.In some implementation, this transistor has about identical geometry for the manufacture of on the mask of IC20.

As shown in Figure 1A, difference transistor pond 4 can from programmable storage 9 reception control signal CTL.Control signal CTL can be used to configuration difference transistor pond 4 and has the customized configuration with the transistor of the coupling terminals in pond.Such as, the selection circuit in pond can use control signal CTL to select the Part II for the Part I of transistor operated in the first transistor group and the transistor operated in transistor seconds group.

In device fabrication, each transistor in difference transistor pond 4 can produce random bias voltage, and it can change along with working point, such as temperature, supply voltage, bias current and/or input common mode voltage.For given transistor arrangement, all biased sum of the integral biased transistor approximated in the first transistor group in pond in the difference transistor pond of the transistor that selectivity connects deducts all biased sum of the transistor in the transistor seconds group in pond.

In some configuration, the input of chopper amplifier 10 is biased can be observed in the calibration process of the various transistor arrangement in difference transistor pond 4.In addition, the special transistor that data can be used for selecting to have the difference transistor pond 4 that low input is biased configures.In addition, this programmable storage 9 can use the data corresponding to selected transistor arrangement to programme, and chopper amplifier 10 is operated in operation together with the difference transistor pond 4 of selected transistor arrangement.The example of the chopper amplifier (such as, Chopper amplifiers 10) of calibration process will be further described below with reference to Figure 13 and 14.

Therefore, the difference transistor pond 4 of Chopper amplifiers 10 can be programmed, to comprise the transistor arrangement having and be biased relative to reduction or the minimum input of other possible transistor arrangement in difference transistor pond 4.Low input is biased and also can causes little output ripple and/or the low input bias current relevant with charging and discharging input capacitance between charge period.

In some configuration, programmable storage 9 can be nonvolatile memory, comprises such as, flash memory, read-only memory (ROM), the memory using fuse and/or anti-fuse to realize and/or magnetic storage apparatus.But other configurations are also possible, such as wherein during calibrating sequence power on or open and/or usage data programming during programmable storage 9 are the execution modes being programmed the volatile memory comprised corresponding to selected transistor arrangement data.

Although the chopper amplifier 10 shown in Figure 1A is the pond comprising a difference transistor, instruction is here applicable to the configuration that wherein chopper amplifier comprises extra difference transistor pond.In such an arrangement, programmable storage (9) can be configured to provide additional control signal, for additional difference transistor pond.

Figure 1B and 1C is the schematic block diagram in the difference transistor pond 8 according to an embodiment.Difference transistor pond 8 shows an execution mode in the difference transistor pond 4 of Figure 1A.Difference transistor pond 8 before Figure 1B shows and to be configured by control signal CTL, and Fig. 1 C shows the example in difference transistor pond 8 after being configured by control signal CTL.

Difference transistor pond 8 comprises the first terminal A, the second terminal B, and the first to the tenth transistor 5a-5j and selection circuit 7, it is configured to reception control signal CTL.

This selection circuit 7 can use control signal CTL to select the Part I of transistor 5a-5j for operating in the first transistor group 6a, and the Part II of transistor 5a-5j for operating in the second electronic circuit 6b.

In some embodiments, transistor 5a-5j is designed to have substantially identical driver intensity and/or severally why not there is manufacture deviation, and selection circuit 7 is configured to the transistor comprising equal number at described first and second electronic circuit 6a, 6b.

During the manufacture of IC comprising difference transistor pond 8, each transistor 5a-5j can cause random bias voltage.For the given configuration of the transistor in first and second electronic circuit 6a, 6b, the integral biased amount of bias sum that can approximate transistor in described first electronic circuit 6a in difference transistor pond 8 deducts the amount of bias sum of transistor in described second electronic circuit 6b.

Between the alignment epoch of chopper amplifier comprising difference transistor pond 8, the combination of the different choice of transistor can be included in first and second electronic circuit 6a, 6b, and the input of amplifier is biased and can observes for each selected transistor arrangement.In some configuration, observe the biased of input amplifier when amplifier is not in copped wave.In other configurations, the residue input observing amplifier is biased, and simultaneously amplifier in copped wave.

In addition, usage data can select specific transistor arrangement, such as has the transistor combination that the input of minimum amplifier is biased.In addition, programmable memory (such as, the programmable storage 9 of Figure 1A) can use and programme corresponding to selected transistor arrangement.Programmable storage can produce control signal CTL, and this selection circuit 7 can be used for the transistor selecting to operate in first and second electronic circuit 6a, 6b.

In the example in the figures, selection circuit 7 use control signal CTL with select second, third, the 5th and the 9th transistor 5b, 5c, 5e, 5i, for operating in described the first transistor group 6a.In addition, selection circuit 7 have employed control signal CTL to select the 4th, the 6th, the 7th and the tenth transistor 5d, 5f, 5g, 5j, for operating in the 2nd crystal nest of tubes 6b.In addition, in the example in the figures, first and the 8th transistor 5a, 5h do not selected to operate in first or second group transistor 6a, 6b.

Fig. 1 C illustrates the example that may distribute of the transistor 5a-5j between the first and second transistor group 6a, 6b.But the distribution shown in Fig. 1 C is illustrative, and can programme by other modes in difference transistor pond 8.

Although comprise 10 transistors in illustrated difference transistor pond 8, difference transistor pond can be suitable for comprising more or less transistor.In one embodiment, difference transistor pond comprises between about 4 to about 24 transistors.But other configurations are also possible.

As mentioned above, selection circuit 7 can use control signal CTL to select the Part I of transistor 5a-5j to be included in the first transistor group 6a and to select the Part II of transistor 5a-5j to be included in the 22 transistor group 6b.In illustrated configuration, be less than whole transistor 5a-5j and be selected for and operate in the first and second transistor group 6a, 6b.But other configurations are also possible, and such as wherein each transistor 5a-5j is included in the execution mode in the first transistor group 6a or transistor seconds group 6b.

In some embodiments, selection circuit 7 can comprise circuit, for selectively comprising any specific transistor at the first transistor group 6a or at transistor seconds group 6b.But in other configuration, some transistor can selectively only be included in a specific transistor group.Such as, in one embodiment, selection circuit 7 is selected the first transistor group 6a from the first transistor group or pond and is selected transistor seconds group 6b from the second group transistor, and at least part of transistor wherein in described Part I group and the second group transistor is different.

Transistor 5a-5h can correspond to polytype transistor.In one embodiment, transistor 5a-5h comprises field-effect transistor (FET), such as metal-oxide semiconductor (MOS) (MOS) transistor or junction field effect transistor (JFET).But other configurations are also possible, and such as wherein transistor 5a-5h comprises the execution mode of bipolar transistor.

In some configuration, in the coupled in parallel electrical connection that specific transistor group comprises.Such as, in the configuration using FET, the drain electrode be connected with each other, the source electrode be connected with each other and/or the grid be connected with each other can be had for the transistor operating selection in the first electronic circuit 6a.Similarly, the transistor for operating selection in the second electronic circuit 6b can have the drain electrode be connected with each other, the source electrode be connected with each other and/or the grid be connected with each other.

Although Figure 1B and Fig. 1 C illustrates that difference transistor pond 8 is for comprising two terminals, difference transistor pond 8 can be suitable for comprising additional terminal.Such as, in the configuration using FET, the terminal that difference transistor pond 8 can comprise and the drain electrode of transistor in first and second electronic circuit 6a, 6b, source electrode and/or grid are connected.The various embodiments in difference transistor pond will further describe below.

Fig. 2 is the circuit diagram of the chopper amplifier 50 according to an embodiment.Chopper amplifiers 50 comprises first or non-inverting input V _iN+, second or reversed input terminal V _iN-, output V _oUT, input chopper circuit 11, first exports the load transistor 21 that chopper circuit 12a, second exports chopper circuit 12b, current source 13, first difference transistor pond 14, first and second p-type metal-oxide semiconductor (MOS) (PMOS), 22, the first and second PMOS cascode transistors 23,24, the load transistor 31 of the first and second n-type metal oxide semiconductor (NMOS), 32, the first and second NMOS cascode transistors 33,34, output amplifier 41, integrating condenser 42 and feedback condenser 43.

As used herein and those of ordinary skill in the art will be understood that, MOS transistor can have by nonmetallic material (such as, polysilicon) grid made, and the dielectric area implemented without silica can be had, but by other dielectric (such as, high-k dielectric).

Input chopper circuit 11 comprises: be electrically connected to described non-inverting input V _iN+first input, be electrically connected to reversed input terminal V _iN-the second input, be configured to receive chopper clock signal CLK _cHOPclock input, be electrically connected to described first difference transistor pond 14 first export and be electrically connected to described first difference transistor pond 14 second grid terminal second export.Current source 13 is connected electrically between the common source terminal in the first transistor pond 14 and the first service voltage V1, and it can be such as low-power or ground power supply.Current source 13 can be used to the common source terminal providing bias current to the first difference transistor pond 14.First difference transistor pond 14 comprises control end further, is configured as receiving the first control signal CTL1 from programmable storage, the programmable storage 9 of such as Figure 1A.First difference transistor pond 14 also comprises the first drain terminal of the source electrode of drain electrode and the PMOS cascode transistors 23 being electrically connected to a PMOS load transistor 21, and the first difference transistor pond 14 also comprises the second drain terminal of the source electrode of drain electrode and the described 2nd PMOS cascode transistors 24 being electrically connected to described 2nd PMOS load transistor 22.

One PMOS load transistor 21 also comprises and is electrically connected to the first reference voltage V _rEF1with the grid of the grid of described 2nd PMOS load transistor 22, a PMOS load transistor 21 also comprises and is electrically connected to second source voltage source V ₂, the source electrode of (it can be such as high power power).2nd PMOS load transistor 22 also comprises the source electrode being electrically connected to second source voltage V2.One PMOS cascode transistors 23 also comprises and is electrically connected to the second reference voltage V _rEF2with the grid of the grid of the 2nd PMOS cascode transistors 24.One PMOS cascode transistors 23 also comprises the drain electrode of the first input being electrically connected to described first output chopper circuit 12a.2nd PMOS cascode transistors 24 also comprises the drain electrode of the second input being electrically connected to the first output chopper circuit 12a.First exports chopper circuit 12a comprises further and is configured to receive chopper clock signal CLK _cHOPclock input.First exports chopper circuit 12a also comprises the first end of inverting input to feedback condenser 43 and first first output inputted of the second output chopper circuit 12b that are electrically connected to output amplifier 41.First output chopper circuit 12a also comprises electrical connection second and exports the second output that second of chopper circuit 12b is input to the non-inverting input of output amplifier 41 and the first end of integrating condenser 42.Integrating condenser 42 also comprises the second end being electrically connected to the first supply voltage V1.Feedback condenser 43 also comprises the output and output V that are electrically connected to described output amplifier 41 _oUTthe second end.

Second output chopper circuit 12b also comprises the clock being configured to receive chopper clock signal CLKCHOP and inputs, is electrically connected to the second output that first of the drain electrode of a described NMOS cascode transistors 33 exported and be electrically connected to the drain electrode of the 2nd NMOS cascode transistors 34.One NMOS cascode transistors 33 also comprises and is electrically connected to the 3rd reference voltage V _rEF3with the grid of the grid of the 2nd NMOS cascode transistors 34, a NMOS cascode transistors 33 also comprises the source electrode of the drain electrode being electrically connected to a NMOS load transistor 31.2nd NMOS cascode transistors 34 also comprises the source electrode of the drain electrode being electrically connected to described 2nd NMOS load transistor 32.One NMOS load transistor 31 also comprises the grid of the source electrode being electrically connected to described first supply voltage V1 and the grid being electrically connected to the 4th reference voltage V REF4 and the 2nd NMOS load transistor 32, and the 2nd NMOS load transistor 32 also comprises and is electrically connected to described first supply voltage V ₁source electrode.

In illustrated configuration, the first difference transistor pond 14 is for being operating as the differential input transistor pair of Chopper amplifiers 50.First difference transistor pond 14 comprises multiple transistor.The Part I of transistor can operate in the first transistor group be associated with first drain terminal in pond, first grid terminal and public source terminal, and the Part II of transistor can operate in the transistor seconds group be associated with second drain terminal in pond, second grid terminal and public source terminal.Such as, the Part I of transistor can have the drain electrode being electrically connected to the first drain terminal, the grid being electrically connected to first grid terminal, be electrically connected to the source electrode of public source terminal.In addition, the Part II of transistor can have the drain electrode being electrically connected to the second drain terminal, the grid being electrically connected to second grid terminal, be electrically connected to the source electrode of public source terminal.Two example embodiment in the first difference transistor pond 14 will be further described below with reference to Fig. 8 A-8B.

Fig. 2 illustrates the example of the Chopper amplifiers that can comprise difference transistor pond.First difference transistor pond 14 can use the first control signal CTL1 to programme, and has the biased special transistor configuration of low input to operate.Although the chopper amplifier 50 in Fig. 2 shows an example of the chopper amplifier that can comprise difference transistor pond, instruction herein can be applicable to various chopper amplifier, comprises such as, the chopper amplifier using other circuit topology to realize.

In addition, although Fig. 2 illustrates the configuration that wherein the first difference transistor pond 14 is associated with N-shaped input transistors, instruction herein can be applicable to the configuration using p-type input transistors, and/or the combination of N-shaped and p-type input transistors.

Fig. 3 is the circuit diagram of the chopper amplifier 60 according to another embodiment.The Chopper amplifiers 60 of Fig. 3 is similar to the Chopper amplifiers 50 in Fig. 2, a kind of configuration is shown except using Chopper amplifiers 60, the first and second PMOS load transistors 21,22 wherein in Fig. 2 are omitted, to comprise the second difference transistor group 15, and the first and second NMOS load transistors 31,32 in Fig. 2 are omitted, to comprise the 3rd difference transistor group 16.

As shown in Figure 3, second difference transistor group 15 comprises the control terminal being configured to reception second control signal CTL2, the common source terminal being electrically connected to second source voltage V2, is electrically connected to the first drain terminal of the source electrode of a PMOS cascode transistors 23, is electrically connected to the second drain terminal of the source electrode of described 2nd PMOS cascode transistors 24, and is electrically connected to described first reference voltage V _rEF1public grid terminal.In addition, the 3rd difference transistor group 16 comprise be configured to reception the 3rd control signal CTL3 control terminal, be electrically connected to the first supply voltage V ₁public source terminal, be electrically connected to the first drain terminal of the source electrode of a described NMOS cascode transistors 33, be electrically connected to the second drain terminal of the source electrode of described 2nd NMOS cascode transistors 34, and be electrically connected to described 4th reference voltage V _rEF4public grid terminal.

Second control signal CTL2 can be used for the configuration of transistor of control second difference transistor group 15.In addition, the 3rd control signal CTL3 can be used for the configuration of transistor of control the 3rd difference transistor group 16.And second and the 3rd control signal CTL2, CTL3 can pass through programmable storage (such as, the programmable storage 9 of Figure 1A) and generate.

Relative to the configuration in single pond, comprise multiple difference transistor pond can contribute to reducing further chopper amplifier input be biased.In shown structure, the first, the second and the three difference transistor pond 1416 can use first, second, and third control signal CTL1-CTL3 to configure respectively, has the biased amplifier of low input to calibrate.

Fig. 4 A is the circuit diagram of the chopper amplifier 70 according to another embodiment.The Chopper amplifiers 70 of Fig. 4 A is similar to the Chopper amplifiers 60 in Fig. 3, except chopper amplifier 70 shows a kind of configuration, the first difference transistor pond 14 wherein in Fig. 3 is omitted, to comprise the first and second nmos input transistors 61,62, its differential input transistor as Chopper amplifiers is to operating.

As shown in Figure 4 A, the source electrode of the first and second nmos input transistors 61,62 is connected to each other, and can receive described bias current from current source 13.In addition, the grid of the first and second nmos input transistors 61,62 is electrically connected to the first and second outputs of input chopper circuit 11 respectively.In addition, the drain electrode of the first and second nmos input transistors 61,62 is electrically connected to the first and second drain terminals of the second difference transistor group 15 respectively.

Difference transistor pond described herein can be included in the various configurations of chopper amplifier.Such as, in shown configuration, difference transistor pond operates, as the load transistor of Chopper amplifiers.But instruction herein is also applicable to various structure, comprises such as, wherein the operation of difference transistor pond is as the configuration of differential input transistor to the difference cascode transistor of, differential load transistor and/or chopper amplifier.

Fig. 4 B is the circuit diagram of the chopper amplifier 75 according to another embodiment.The Chopper amplifiers 75 of Fig. 4 B is similar to the chopper amplifier 70 of Fig. 4 A, difference is that chopper amplifier 75 shows a kind of configuration, wherein the 3rd difference transistor pond 16 of Fig. 4 A is omitted, to comprise the first and second NMOS load transistors 31,32.

In some embodiments, difference transistor pond may be used for PMOS load transistor, but can not be used for NMOS load transistor, or vice versa.It is described such before the additional detail of Chopper amplifiers 75 can be similar to.

Fig. 5 A is chopper amplifier 80 circuit diagram according to another embodiment.The chopper amplifier 80 of Fig. 5 A is similar to the Chopper amplifiers 50 in Fig. 2, and except chopper amplifier 80 shows a kind of configuration, the first difference transistor pond 14 wherein in Fig. 2 is omitted, to comprise the first and second nmos input transistors 61,62.In addition, chopper amplifier 80 shows a kind of configuration, the first and second PMOS cascode transistors 23,24 wherein in Fig. 2 are omitted, to comprise the 4th difference transistor pond 17, and the first and second NMOS cascode transistors 33,34 in Fig. 2 are omitted, to comprise the 5th difference transistor pond 18.

As shown in Figure 5A, the 4th difference transistor pond 17 comprises: be configured to the control terminal of reception the 4th control signal CTL4, be electrically connected to the first source terminal of the drain electrode of a described PMOS load transistor 21, be electrically connected to the second source terminal of the drain electrode of the 2nd PMOS load transistor 22, be electrically connected to the described first the first source terminal exporting first input of chopper circuit 12a, be electrically connected to described first and export the second source terminal of second input of chopper circuit 12a and be electrically connected to described second reference voltage V _rEF2public grid terminal.In addition, the 5th difference transistor group 18 comprises: be configured to the control terminal of reception the 5th control signal CTL5, be electrically connected to the first source terminal of the drain electrode of a described NMOS load transistor 31, be electrically connected to the second source terminal of the drain electrode of the 2nd NMOS load transistor 32, be electrically connected to the described second the first the first drain terminal exported exporting chopper circuit 12b, be electrically connected to described second and export second second drain terminal exported of chopper circuit 12b and be electrically connected to described 3rd reference voltage V _rEF3common gate terminal.

4th control signal CTL4 can be used for the configuration of transistor in control the 4th difference transistor pond 17.In addition, the 5th control signal CTL5 can be used for the configuration of the transistor of control the 5th difference transistor group 18.4th and the 5th control signal CTL4, CTL5 can pass through programmable storage (such as, the programmable storage 9 of Figure 1A) and generate.Eliminate the first, second, and third difference transistor pond 14-16 of Fig. 3 in the construction illustrated.But instruction is herein applicable to various configuration, comprises such as, comprise first, second, third, fourth and/or the 5th configuration of combination in any of difference triode pond 14-18.Described those before the additional detail of chopper amplifier 80 can be similar to.

Fig. 5 B is the circuit diagram of the chopper amplifier 85 according to another embodiment.The chopper amplifier 85 of Fig. 5 B is similar to the chopper amplifier 80 of Fig. 5 A, difference is that chopper amplifier 85 shows a kind of configuration, wherein the 5th difference transistor pond 18 of Fig. 5 A is omitted, to comprise the first and second NMOS cascode transistors 33,34.

In some embodiments, difference transistor pond may be used for PMOS cascode transistors, but is not used in NMOS cascode transistors, or vice versa.Described those before the additional detail of Chopper amplifiers 85 can be similar to.

Fig. 5 C is the circuit diagram of the chopper amplifier 84 according to another embodiment.Chopper amplifiers 84 comprises input chopper circuit 11, first and exports chopper circuit 12a, the second output chopper circuit 12b, current source 13, output amplifier 41, integrating condenser 42, feedback condenser 43, and first and second nmos input transistors 61,62, it can be as previously described.Chopper amplifiers 84 also comprises the first difference transistor pond 86 and the second difference transistor pond 87.

In some embodiments, difference transistor group can comprise the combination of the input transistors of cascode transistors, load transistor and/or grouping or pairing.

Such as, in shown configuration, the first difference transistor pond 86 comprises multiple PMOS load transistor of grouping and multiple PMOS cascode transistors.Especially, described multiple PMOS load transistor and described multiple PMOS cascode transistors are implemented, and make the drain electrode of specific PMOS load transistor be connected to the source electrode of corresponding PMOS cascode transistors.Equally, the second difference transistor pond 87 comprises multiple NMOS load transistor of grouping and multiple NMOS cascode transistors.Especially, described multiple NMOS load transistor and described multiple NMOS cascode transistors are implemented, and make the drain electrode of specific NMOS load transistor be connected to the source electrode of corresponding NMOS cascode transistors.

In illustrated configuration, control signal CTL4 can be used for transistor in selection first difference triode group 86, and right Part I exports with the drain electrode and first that are connected electrically in the first nmos input transistor 61 between first input of chopper circuit 12a, and selects the right Part II of the transistor in the first difference transistor group 86 to export between second input of chopper circuit 12a with the drain electrode and first that are connected electrically in the second nmos input transistor 62.In addition, control signal CTL5 can be used to the right Part I of transistor in selection second difference triode group 87, to be connected electrically in first input and the first supply voltage V of the second output chopper circuit 12b ₁between, and the Part II selecting the transistor in the second difference transistor pond 87 right, to be connected electrically in the second input and the first supply voltage V of the second output chopper circuit 12b ₁between.

Although comprising shown in each environment comprising the difference transistor pond of the transistor group of cascode transistors and load transistor, other configurations are being possible.Such as, difference transistor group can comprise the input transistors of cascode transistors, load transistor and/or grouping or pairing.In addition, in some configuration, negative feedback resistor is grouped or matches the transistor of difference transistor group.

Before other details of this chopper amplifier 84 can be similar to described those.

Fig. 5 D is the circuit diagram of the chopper amplifier 88 according to another embodiment.Chopper amplifiers 88 comprises input chopper circuit 11, first and exports chopper circuit 12a, the second output chopper circuit 12b, current source 13, difference transistor group 16, first and second PMOS cascode transistors 23,24, the first and second NMOS cascode transistors 33,34, output amplifier 41, integrating condenser 42 and feedback condenser 43, it can be as previously described.Chopper amplifiers 88 also comprises difference transistor pond 89.

In illustrated configuration, difference transistor pond 89 comprises multiple nmos input transistor and the PMOS load transistor of pairing mutually.Especially, multiple nmos input transistor and multiple PMOS load transistor are implemented, and make the drain electrode of specific nmos input transistor be connected to the drain electrode of corresponding PMOS load transistor.In addition, the Part I that the transistor that control signal CTL1 can be used in selection difference transistor pond 89 is right, with between the first output being connected electrically in input chopper circuit 12 and the source electrode of a PMOS cascode transistors 23, and select the Part II that in difference transistor pond 89, transistor is right, with between the second output being connected electrically in input chopper circuit 12 and the source electrode of described 2nd PMOS cascode transistors 24.

Although when comprise each comprise the difference transistor pond of the transistor group of input transistors and load transistor illustrate, other configurations are possible.Such as, in one embodiment, difference transistor pond comprises multiple each transistor group comprising input transistors and load transistor.In another embodiment, difference transistor pond comprises multiple each transistor group comprising load transistor and cascode transistors.In another embodiment, difference transistor pond comprises multiple transistor group, and often group comprises input transistors, cascode transistors and load transistor.

Before other details of this chopper amplifier 88 can be similar to described those.

Fig. 6 is chopper amplifier 90 circuit diagram according to another embodiment.The chopper amplifier 90 of Fig. 6 is similar to the Chopper amplifiers 60 of Fig. 3, and difference is that chopper amplifier 90 shows the difference configuration exporting chopper circuit.Such as, relative to the Chopper amplifiers 60 of Fig. 3 comprising first and second output chopper circuit 12a, 12b, Chopper amplifiers 90 comprises and exports chopper circuit 12.

As shown in Figure 6, export chopper circuit 12 comprise drain electrode and the NMOS cascode transistors 33 being electrically connected to a PMOS cascode transistors 23 first input end, be electrically connected to described drain electrode drain electrode the 2nd PMOS cascode transistors 24 and to the 2nd NMOS cascode transistors 34 the second input, be configured to receive chopper clock signal CLK _cHOPclock input, be electrically connected to first of the inverting input of output amplifier 41 and the drain electrode of described first input end of clock and feedback condenser 43 and export and be electrically connected to second of the non-inverting input of output amplifier 41 and the first end of integrating condenser 42 and export.

As those of ordinary skill in the art will be understood that, instruction is herein applicable to various input, exports copped wave configuration.Such as, Chopper amplifiers can comprise multiple input herein and/or export chopper circuit.In addition, in some configuration, one or more input and/or export chopper circuit and can receive different clock signals, such as have different to postpone, the clock signal of overlapping, non-overlapped and/or phase place.

In addition, as described in detail with further reference to Figure 10 Figure 12 below, in some embodiments, chopper circuit can integrated difference transistor pond.Comprise independent input chopper circuit and the scheme in difference transistor pond relative to wherein this chopper amplifier, integrate chopper circuit and difference transistor pond and can reduce number of switches in signal path.

Fig. 7 is the circuit diagram of the Chopper amplifiers 100 according to another embodiment.The chopper amplifier 100 of Fig. 7 is similar to the chopper amplifier 50 of Fig. 2, and difference is that Chopper amplifiers 100 shows the different structure of first and second output chopper circuit 12a, 12b.

Such as, in structure shown in Fig. 7, the first the first and second inputs exporting chopper circuit 12a are electrically connected to the drain electrode of the first and second PMOS load transistors 21,22 respectively.In addition, the first the first and second outputs exporting chopper circuit 12a are electrically connected to the source electrode of the first and second PMOS cascades difference transistors 23,24.In addition, the second the first and second inputs exporting chopper circuit 12b are electrically connected to the source electrode of the first and second NMOS cascades difference transistors 33,34.In addition, the second the first and second outputs exporting chopper circuit 12b are electrically connected to the drain electrode of the first and second NMOS load transistors 31,32 respectively.Before other details of Chopper amplifiers 100 can be similar to described those.

Fig. 8 A is the circuit diagram in the difference transistor pond 150 according to an embodiment.Difference transistor pond 150 comprises public source terminal S, first grid terminal GA, second grid terminal GB, the first drain terminal DA, the second drain terminal DB, first to fourth nmos pass transistor 121-124, first to fourth drain electrode selector switch 131-134, and first to fourth grid selector switch 141-144.Difference transistor pond 150 is configured to receive the control signal with the first control bit CTL<1>, the second control bit CTL<2>, the 3rd control bit CTL<3> and the 4th control bit CTL<4>.Difference transistor pond 150 shows the illustrative embodiments in the first difference transistor pond 14 of Fig. 2, Fig. 3, Fig. 6 and 7.

In structure in fig. 8 a, the source electrode of first to fourth nmos pass transistor 124-124 by electricity to public source terminal S.In addition, first to fourth drain electrode selector switch 131-134 and first to fourth grid selector switch 141-144 is operating as the selection circuit that can utilize the control signal in pond to control.Such as, first to fourth drain electrode selector switch 131-134 can be used for based on CTL<1>, the second control bit CTL<2> of described first control bit, the state of the 3rd control bit CTL<3> and the 4th control bit CTL<4>, the drain electrode of first to fourth nmos pass transistor 121-124 being selectively connected to the first drain terminal DA or the second drain terminal DB respectively.In addition, first to fourth grid selector switch 141-144 can be used for respectively based in described first control bit CTL<1>, the second control bit CTL<2>, 3rd control bit CTL<3>, is optionally connected the grid of described first to fourth nmos pass transistor 121-124 to first grid terminal GA or second grid terminal GB with the state of the 4th control bit CTL<4>.The part being connected to the transistor of the first drain terminal DA and first grid terminal GA can be associated with the first transistor group, and the part being connected to the second drain terminal DB and second grid terminal GB can be associated with transistor seconds group.

In some embodiments, the design of first to fourth nmos pass transistor 121-124 has identical driving intensity and/or geometry.The first to fourth grid selector switch 141-144 of first to fourth drain electrode selector switch 131-134 can be used to connect the Part I of nmos pass transistor 121-124 to the first drain terminal DA and first grid terminal GA, and the Part II connecting nmos pass transistor 121-124 is to the second drain terminal DB and second grid terminal GB.In some embodiments, the configuration of the selection of transistor can be determined during factory testing, and retains in programmable storage on chip.

Although Fig. 8 A shows the structure using four NMOS transistors and Correlation selection circuit, difference transistor pond can adapt to the transistor comprising varying number.In one embodiment, difference transistor pond 150 comprises between about 4 to about 24 transistors.

Fig. 8 B is the circuit diagram in the difference transistor pond 190 according to another embodiment.Difference transistor pond 190 comprises public source terminal S, first grid terminal GA, second grid terminal GB, the first drain terminal DA, the second drain terminal DB, first to fourth nmos pass transistor 151-154, the 5th to the 8th nmos pass transistor 161-164, first to fourth drain electrode selector switch 171-174 and the 5th to the 8th drain electrode selector switch 181-184.Difference transistor pond 190 is configured to reception and has control bit CTLA<1>, CTLA<2>, CTLA<3>, CTLA<4>, CTLB<1>, CTLB<2>, the control signal of CTLB<3> and CTLB<4>.Difference transistor pond 190 shows another illustrative embodiments in the first difference transistor pond 14 of Fig. 2, Fig. 3, Fig. 6 and 7.

In the structure shown in Fig. 8 B, the gridistor 151-154 of first to fourth NMOS is electrically connected to first grid terminal GA, the gridistor 161-164 of the 5th to the 8th NMOS is electrically connected to second grid terminal GB, and first to the 8th nmos pass transistor 151-154, the source electrode of 161-164 is electrically connected to public source terminal S.In addition, first to fourth drain electrode selector switch 171-174 can be used to optionally connect first to fourth nmos pass transistor 151-154 to the first drain terminal DA, to form the first transistor group.In addition, the 5th to the 8th drain electrode selector switch 181-184 can use and be connected and sweep the second drain terminal DB, to form the second group transistor by the partial selective of the 5th to the 8th nmos pass transistor 161 to 164.The first to the eight drain electrode selector switch 171-174, 181-184 can respectively according to control bit CTLA<1>, CTLA<2>, CTLA<3>, CTLA<4>, CTLB<1>, CTLB<2>, the specific transistor arrangement of condition selecting of CTLB<3> and CTLB<4>.

Although Fig. 8 B shows the formation that difference transistor pond is included in four transistors in two groups or two ponds, other configurations comprising more or less transistor also can be used.In addition, in some embodiments, each group can comprise the transistor of different number.

Fig. 8 C is the figure of the difference transistor group 220 according to another embodiment circuit.Difference transistor group 220 comprises public source terminal S, public grid terminal G, the first drain terminal DA, the second drain terminal DB, first to fourth nmos pass transistor 201-204 and first to fourth drain electrode selector switch 211-214.Difference transistor group 220 is configured to receive the control signal of CTL<1>, the second control bit CTL<2>, the 3rd control bit CTL<3> and the 4th control bit CTL<4> with the first control bit.Difference transistor group 220 show Fig. 3,4 and 6 the illustrative embodiments in the 3rd difference transistor pond 16.

In the structure shown in Fig. 8 C, the source electrode of first to fourth nmos pass transistor 201-204 is electrically connected to public source terminal S, and the grid of first to fourth nmos pass transistor 201-204 is electrically connected to public grid terminal G.In addition, the first to fourth drain electrode selector switch 211-214 connection that can optionally utilize the first control bit CTL<1>, the second control bit CTL<2>, the 3rd control bit CTL<3> and the 4th control bit CTL<4> to control between the drain electrode and first or second drain terminal DA, DB of the first to the four nmos pass transistor 201-204 respectively.The part being connected to the transistor of the first drain terminal DA can be associated with the first transistor group, and the part of the transistor be connected in described second drain terminal DB can be associated with transistor seconds group.The additional detail of difference transistor group 220 can as being described before.

Fig. 8 D is the schematic diagram in the difference transistor pond 250 according to another embodiment circuit.Difference transistor pond 250 comprises the first source terminal SA, the second source terminal SB, public grid terminal G, the first drain terminal DA, the second drain terminal DB, first to fourth nmos pass transistor 221-224, first to fourth light source selector switch 231-234 and first to fourth drain electrode selector switch 241-244.Difference transistor pond 250 is configured to receive the control signal with the first control bit CTL<1>, the second control bit CTL<2>, the 3rd control bit CTL<3> and the 4th control bit CTL<4>.Difference transistor pond 250 shows the illustrative embodiments in the 5th difference transistor pond 18 of Fig. 5 A.

In the configuration shown in Fig. 8 D, the grid of first to fourth nmos pass transistor 221-224 is electrically connected to public grid terminal G.In addition, first to fourth light source selector switch 231234 can use the control signal in pond optionally to control to connect between the source electrode of first to fourth nmos pass transistor 221-224 and the first or second source S A, SB.In addition, the first to fourth drain electrode selector switch 241-244 connection that can optionally use control signal to control between the drain electrode and first or second drain terminal DA, DB of the first to the four nmos pass transistor 221-224.The part being connected to the nmos pass transistor of the first source terminal SA and the first drain terminal DA can be associated with the first transistor group, and the part of the nmos pass transistor being connected to the second source terminal SB and the second drain terminal DB can be associated with transistor seconds group.The more details in difference transistor pond 250 can as being described before.

Although Fig. 8 A-8D shows difference transistor pond comprise multiple n-type transistor, instruction is herein applicable to the configuration using p-type transistor or N-shaped and p-type transistor combination.Such as, in one embodiment, Fig. 3, Fig. 4 and 6 the second difference transistor group 15 use the complementary PMOS structure in the nmos differential transistor pond 220 of Fig. 8 C to realize.In another embodiment, the 4th difference transistor pond 17 of Fig. 5 A uses the complementary PMOS structure in the nmos differential transistor pond of Fig. 8 D to realize.In another embodiment, Chopper amplifiers comprises P type differential input transistor, and comprises the difference transistor pond using the complementary PMOS structure in the nmos differential transistor pond in Fig. 8 A or 8B to realize.

Fig. 9 is the circuit diagram of an execution mode of chopper circuit 260.Input chopper circuit comprises first to fourth chopping switch 251-254.First to fourth chopping switch 251-254 can be used to cut the input signal chopping and receive between first input end IN1 and the second input IN2, cuts output signal to produce short that the first output OUT1 and second exports between OUT2.The chopper circuit 260 of Fig. 9 shows the example embodiment of input and output chopper circuit described herein.But other configurations are also possible.

First to fourth chopping switch 251-254 uses chopper clock signal to handle, it comprise the first chopper clock signal phase place (CLK) and the second chopper clock signal phase place ( ).Such as, first input end IN1 can be connected to the first output OUT1 and the second input IN2 is connected to the second output OUT2 by the first and second chopping switch 251,252 during the first chopper clock signal phase place.In addition, first input end IN1 can be connected to the second output OUT2 during the second chopper clock signal phase place at the third and fourth chopping switch 253,254 and the second input IN2 is connected to the first output OUT1.In some configuration, the phase place of the first chopper clock signal and the phase place of the second chopper clock signal can be nonoverlapping.

In one embodiment, the MOS transistor that first to fourth chopping switch 251-254 uses realizes, such as, and nmos pass transistor, PMOS transistor or their combination.

Figure 10 is the circuit diagram of the Chopper amplifiers 310 according to another embodiment.The chopper amplifier 310 of Figure 10 is similar to the Chopper amplifiers 50 in Fig. 2, except Chopper amplifiers 310 shows a kind of configuration, wherein the input chopper circuit 11 of Fig. 2 and the first difference transistor pond 14 of Fig. 2 are omitted, to adopt copped wave difference transistor pond 304.

As shown in Figure 10, copped wave difference transistor pond 304 comprises the first grid terminal being electrically connected to described non-inverting input VIN+, be electrically connected to the second grid terminal of reversed input terminal VIN, be configured to the control terminal of reception first control signal CTL1, be configured to the clock terminal receiving chopper clock signal CLKCHOP, be configured to the public source terminal receiving bias current from current source 13, be electrically connected to the drain electrode of a PMOS load transistor 21 and source electrode to a PMOS cascode transistors 23 the first drain terminal, with the second drain terminal of the source electrode of the drain electrode and described 2nd PMOS cascode transistors 24 that are electrically connected to described 2nd PMOS load transistor 22.

In some implementations, difference transistor group can integrated input chopper circuit to provide copped wave difference transistor pond, this can comprise in the scheme in independent integrated input chopper circuit and difference transistor pond relative to wherein chopper amplifier the digital switch reduced in signal path.The realization in two example copped wave difference transistor ponds 304 will be described below with further reference to Figure 12 A-12B.

Figure 11 is the circuit diagram of the Chopper amplifiers 320 according to another embodiment.The chopper amplifier 320 of Figure 11 be similar to Figure 10 chopper amplifier 310, difference is that Chopper amplifiers 310 shows a kind of configuration, wherein first and second PMOS cascode transistors 23, the 24 and first output chopper circuit 12a of Figure 10 are omitted, to comprise the second copped wave difference transistor pond 305, and wherein first and second NMOS load transistors 31, the 32 and second output chopper circuit 12b of Figure 10 are omitted, to comprise 306 of the 3rd copped wave difference transistor pond.

As shown in Figure 11, input and/or the output chopper circuit of Chopper amplifiers can be integrated with one or more difference transistor pond, thus can be reduced in the number of switches in the signal path of chopper amplifier.Before other details of Chopper amplifiers 320 can be similar to described those.

Figure 12 A is the circuit diagram in the copped wave difference transistor pond 330 according to an embodiment.Copped wave difference transistor pond 330 comprises public source terminal S, first grid terminal GA, second grid terminal GB, the first drain terminal DA, the second drain terminal DB, first to fourth nmos pass transistor 121-24, first to fourth drain electrode selector switch 131-34, first to fourth grid selector switch 141-44, and first to fourth chopper clock signal control switch 321-24.Copped wave difference transistor pond 330 is configured to receive chopper clock signal and receives the control signal with the first control bit CTL<1>, two control bit CTL<2>, the 3rd control bit CTL<3> and the 4th control bit CTL<4>.Difference transistor pond 330 describes the example embodiment cutting difference transistor pond 304 of Figure 10-11.

The copped wave difference transistor pond 330 of Figure 12 A be similar in Fig. 8 A difference transistor pond 150, difference is that copped wave difference transistor pond 330 also comprises first to fourth chopper clock signal control switch 321-324, and this is used to control first to fourth and drains selector switch 131-134 and first to fourth grid selector switch 141-144.First to fourth chopper clock signal control switch 321-324 is as multiplexer.Although an execution mode of multiplexer has been described, those of ordinary skill in the art will be understood that, multiplexingly can provide by other modes.

As illustrated in fig. 12, in first to fourth chopper clock signal control switch 321-324 each can the first chopper clock signal phase place (CLK) and a second chopper clock signal phase place ( ) between select chopper clock signal.But, it will be understood to those of skill in the art that other configuration can use.

First chopper clock signal control switch 321 can be selected by use first control bit CTL<1> and produce the first clock signal clk <1> between the first and second chopper clock signal phase places.In addition, the second chopper clock signal control switch 322 can be selected by use second control bit CTL<2> and produce second clock signal CLK<2> between the first and second chopper clock signal phase places.In addition, the 3rd chopper clock signal control switch 323 can be selected by use the 3rd control bit CTL<3> and produce the 3rd clock signal clk <3> between the first and second chopper clock signal phase places.In addition, the 4th chopper clock signal control switch 324 can be selected by use the 4th control bit CTL<4> and produce the 4th clock signal clk <4> between the first and second chopper clock signal phase places.As illustrated in fig. 12, the first clock signal clk <1>, second clock signal CLK<2>, the 3rd clock signal clk <3> and the 4th clock signal clk <4> can be used for control first to fourth and to drain the switching manipulation of selector switch 131-134 and first to fourth grid selector switch 141-144.

Figure 12 B is the circuit diagram in the individual copped wave difference transistor pond 350 according to another embodiment.The copped wave difference transistor pond 350 of Figure 12 B be similar to Figure 12 A copped wave difference transistor pond 330, difference is that copped wave difference transistor pond 350 eliminates first to fourth chopper clock signal control switch 321-324, to comprise combinational logic 355.The additional detail in copped wave difference transistor pond 350 can be similar to above-mentioned those.

Figure 13 is the flow chart of the method 500 according to an embodiment calibration chopper amplifier.Method 500 can be used for calibrating such as Figure 1A, 2-7,10 or 11 any chopper amplifier, it is to be appreciated that method discussed in this article can comprise more or less operation.

The illustrated method 500 of calibration chopper amplifier starts from block 501, under wherein one or more operating conditions respectively to the multiple selected transistor arrangement in difference transistor pond observe chopper amplifier input be biased.The input of Chopper amplifiers is biased can be observed in a variety of ways, comprises, such as, by the difference between the noninverting and inverting input of observing amplifier, or its amplified version, when amplifier uses negative feedback to connect.In some implementations, the chopper clock that such voltage difference can operate at steady-state is observed.In another embodiment, the input of Chopper amplifiers is biased is that output signal by observing chopper amplifier is in the size variation of the composition of chopping frequency.

In some embodiments, the input of Chopper amplifiers is biased is observe in multiple service conditions, comprises at least two or more values in same operation variable.The input observing Chopper amplifiers between multiple values of at least one performance variable is biased and can be used for determining how input offset voltage changes in opereating specification.Such as, the input of amplifier is biased with the change of temperature, supply voltage, bias current and input common mode voltage or can change.By observing input offset voltage between two or more values of at least one performance variable, the transistor arrangement of relatively little input offset change is provided to be selected.

Although method 500 is illustrated as chopper amplifier when comprising a difference transistor pond, Chopper amplifiers can comprise multiple difference transistor pond, and the amount of bias of Chopper amplifiers can be observed for each selection transistor arrangement in pond.In some embodiments, the different crystal pipe configuration that the input of Chopper amplifiers is biased for one of multiple difference transistor pond is observed, and another difference transistor pond is the configuration of fixed crystal pipe.Once specific difference transistor pond is configured, the method can repeat, until the pond of all difference transistors is configured.In other embodiments, when changing the transistor arrangement in two or more difference transistor pond, input is biased to be observed.

At block 502 subsequently, selected in the special transistor configuration with reduction or minimum biased difference transistor pond of one or more operating condition.In some configuration, the configuration of selected transistor can correspond to has the biased transistor arrangement of minimum input in specific working point.But in other configuration, the configuration of selected transistor can correspond to the transistor arrangement that the relative little change that is biased with the input in multiple operating condition or change are associated.Such as, the configuration of selected transistor can correspond to the structure of transistor, and wherein the input of amplifier is biased the minimal drift of approximately change cross-over temperature, supply voltage, bias current and/or input common mode voltage.In one embodiment, the configuration of selected transistor corresponding to have within the scope of operating condition about minimum average B configuration square error transistor arrangement.

Method 500 proceeds to block 503, and the data wherein corresponding to selected transistor arrangement are stored in programmable storage, and chopper amplifier and selected transistor arrangement are operated.

In some embodiments, described programmable storage is that a kind of nonvolatile memory is integrated on chip or with chopper amplifier in jointly encapsulating, and nonvolatile memory uses shop test data to programme.

But other configuration is possible, such as, wherein realize in Chopper amplifiers power calibration procedure and/or at calibration cycle.

Figure 14 is the flow chart of the method 510 of calibration chopper amplifier according to another embodiment.The method 510 can be used for calibrating such as Figure 1A, 2-7,10 or 11 any chopper amplifier.

The illustrated method 510 of calibration chopper amplifier starts from block 511, wherein be biased the input of multiple difference transistor groups observation chopper amplifiers in difference transistor pond respectively under multiple service conditions, selected transistor arrangement is corresponding to all crystals pipe configuration being less than difference transistor pond.

As described above, the input of Chopper amplifiers is biased can be observed in a variety of ways, and can observe across multiple operating condition, comprises two or more value or scans at least one performance variable.

In illustrated method 510, all possible transistor arrangement observation input that is less than for difference transistor pond is biased.The configuration being less than all possible transistor by observing input is biased, and the alignment time of Chopper amplifiers can reduce.In one example, determine that the input of all crystals pipe in the difference transistor pond comprising 16 transistors is biased can relate to 16 and select 8 or 12870 observations.In one embodiment, the transistor arrangement observation input for multiple Line independent is biased.

The method 510 proceeds to block 512, wherein indicates the effect data of the transistor in pond under multiple operating condition on the impact that input is biased to be determined.In some configuration herein, the contribution of each transistor as vector can be solved.In addition, the contribution of each transistor can be decomposed into some effects further, and this itself can be vector.In some configuration, one or more effect can minimize selectively or reduce.In one embodiment, effect data comprises multiple vector, comprise representative under each described multiple operating condition multiple transistor for the data of the impact of input offset voltage.

At square frame 513 subsequently, effect data has minimizing or minimum biased difference transistor pond customized configuration for selecting under multiple operating condition.The input that the configuration of the selected transistor in difference transistor pond can correspond to one of transistor arrangement that the input of observing amplifier be biased or amplifier is biased unobserved transistor arrangement.In some implementations, provide the linear combination of various combination of the vector calculating effect data, and determine to have the linear combination of lowest mean square length and select transistor arrangement.

Described method 510 can be used to select transistor arrangement, can provide and be biased, as temperature, supply voltage, bias current and/or input common mode voltage across the low of multiple operating point.Be biased the scheme of observing each transistor arrangement in difference transistor pond relative to the input of wherein chopper amplifier, the method 510 can relate to the less alignment time.

The method 510 proceeds to block 514, and the configuration data wherein corresponding to selected transistor is stored in programmable storage, makes chopper amplifier and selected transistor arrangement work.

The additional detail of the method 510 of Figure 14 can be similar to the method 500 of previously described Figure 13.

Description above and claims can finger element feature " is connected " or " coupling " together.As used herein, unless explicitly claimed, otherwise the element/feature that is meant to of " connection " is connected directly or indirectly to another element/feature, and not necessarily mechanically.Similarly, unless explicitly claimed, otherwise the element/feature that is meant to of " coupling " is coupled to another element/feature directly or indirectly, and not necessarily mechanically.Therefore, although the exemplary arrangement of various diagram elements depicted shown in the figure and parts, additional intermediate members, equipment, feature or assembly may reside in practical embodiments (supposes that the function of described circuit can not be affected).

Application

Adopt the equipment of such scheme can be implemented into various electronic equipment.The example of electronic equipment can include, but is not limited to imaging of medical and monitoring, consumption electronic product, consumer, electronic test equipment etc.The example of electronic equipment can also comprise memory chip, memory module optical-fiber network or other communication network, and the circuit of disc driver circuit.Consumption electronic product can include, but is not limited to mobile phone, phone, TV, computer monitor, computer, handheld computer, personal digital assistant (PDA), microwave oven, refrigerator, automobile, stereophonic sound system, cassette tape recorder or player, DVD player, CD Player, VCR, MP3 player, broadcast receiver, video camera, camera, digital camera, pocket memory chip, washing machine, dryer, washer/dryer, photocopier, facsimile machine, scanner, multi-function peripheral device, wrist-watch, clock and watch etc.In addition, this electronic installation can comprise the product do not completed.

Although the present invention is described in certain embodiments, to those of ordinary skill in the art's other embodiment apparent, comprise the embodiment that those do not provide all feature and advantage described in this paper, also within the scope of the invention.In addition, above-mentioned various embodiment can be combined to provide further embodiment.In addition, some feature shown in context in one embodiment also can be incorporated in other embodiment.Therefore, scope of the present invention limits by means of only with reference to appended claims.

Claims

1. a device, comprising:

Programmable storage, is configured to generation first control signal; With

Chopper amplifier, be configured to amplify differential input voltage signal to produce output signal, wherein said Chopper amplifiers comprises:

First difference transistor group, comprise selection circuit and multiple transistor, wherein said selection circuit is configured to the Part I selecting the multiple transistors operated in the first transistor group based on described first control signal, and wherein said selection circuit is configured to the Part II selecting the multiple transistors operated in transistor seconds group based on described first control signal further

The input offset voltage of wherein said Chopper amplifiers changes to some extent based on the selection of transistor in described first and second transistor groups.

2., wherein, there is not manufacture deviation in device according to claim 1, the driving intensity of each in described multiple transistor or geometry identical in fact.

3. device according to claim 1, wherein selection circuit is configured to the transistor selecting identical number in described first and second transistor groups.

4. device according to claim 1, also comprises:

Input chopper circuit, comprise first input end, the second input, input end of clock, the first output and the second output, wherein, described input chopper circuit is configured to the differential input voltage signal between reception first and second input, and cut differential input voltage signal based on the chopper clock signal received in clock input

Wherein said difference transistor pond also comprises: the first grid input being electrically connected to the first output of described input chopper circuit, and the second second grid exported being electrically connected to described input chopper circuit inputs.

5. device according to claim 1, wherein, the selection circuit in described first difference transistor pond comprises multiple switch, and wherein said multiple switch is configured to provide the input chopping operation of Chopper amplifiers or export one of chopping operation.

6. device according to claim 1, wherein, described first difference transistor group is placed in the amplification path along described Chopper amplifiers, wherein the first difference transistor pond operation, as one of the transistor of the difference cascode of the differential input transistor of chopper amplifier, the differential load transistor of Chopper amplifiers or chopper amplifier.

7. device according to claim 1, also comprises the second difference transistor group, and wherein, the transistor arrangement of described second difference transistor group controls based on the second control signal from programmable storage.

8. device according to claim 7, also comprises the 3rd difference transistor group, and wherein, the transistor arrangement of described 3rd difference transistor group controls based on the 3rd control signal from programmable storage,

Wherein, described first difference transistor pond operates the differential input transistor as chopper amplifier,

Wherein, described second difference transistor pond operates the differential load transistor as chopper amplifier, and

Wherein, described 3rd difference transistor pond operation is as the difference cascode transistor of chopper amplifier.

9. device according to claim 1, wherein, described output signal comprises single ended output voltage signal.

10. device according to claim 1, also comprises integrated circuit (IC), and wherein said IC comprises described Chopper amplifiers and described programmable storage.

11. devices according to claim 10, wherein, described programmable storage comprises the data be stored therein, wherein said data are associated with the selected state of described first control signal, wherein compared with at least the second state of the first control signal, the selected state of described first control signal corresponds to the special transistor configuration of multiple transistors in the first and second transistor groups with less input configuration.

12. devices according to claim 11, wherein, compared with the every other state of the first control signal, the selected state of described first control signal corresponds to the special transistor configuration in the first and second transistor groups with multiple transistors that minimum input is biased.

13. devices according to claim 1, wherein, described first difference transistor group is placed in the amplification path along described Chopper amplifiers, wherein, first difference transistor pond comprises multiple transistor group, wherein, each described multiple transistor group comprises two or more input transistors, cascode transistor or load transistor.

14. 1 kinds of methods of calibrating chopper amplifier, the method comprises:

For each of the multiple selected transistor arrangement in the first difference transistor pond of chopper amplifier, observe the input offset voltage of the multiple Chopper amplifiers of each of chopper amplifier, wherein, described first difference transistor group comprises multiple transistor, and wherein selected transistor arrangement comprises the various combination of the multiple transistors in the first transistor group and the second group transistor;

Based on described input offset voltage observation and select transistor arrangement; With

The data corresponding to selected transistor arrangement are stored in programmable storage.

15. methods according to claim 14, wherein, selected transistor arrangement comprises all possible transistor arrangement being less than difference transistor pond.

16. methods according to claim 14, also comprise:

Use the observation of input offset voltage, determine the effect data of each transistor in difference transistor pond,

Wherein, transistor arrangement is selected based on effect data at least in part.

17. methods according to claim 16, wherein, selected transistor arrangement is not from multiple selected transistor arrangement.

18. methods according to claim 16, also comprise: for each of multiple operating condition, and observe the input offset voltage of each of multiple selected transistor arrangement, described multiple operating condition comprises two or more values of at least one performance variable.

19. methods according to claim 18, wherein determine that effect data comprises: determine multiple vector, comprise each described multiple transistor of representative for multiple operating condition to the data of the impact of input offset voltage.

20. methods according to claim 19, wherein, select particular combination to comprise further: the linear combination determining the vector with lowest mean square length.

21. methods according to claim 18, wherein, at least one performance variable described comprises the one or more of temperature, supply voltage, bias current or input common mode voltage.

22. methods according to claim 14, also comprise:

Stored data are retrieved when IC conducting; With

Apply the data stored, make chopper amplifier use selected transistor arrangement operation.

23. methods according to claim 14, wherein said first difference transistor group is placed in the amplification path along described Chopper amplifiers, wherein, first difference transistor pond comprises multiple transistor group, wherein, each described multiple transistor group comprises two or more input transistors, cascode transistor or load transistor.