DE102014111208B4 - Apparatus and methods for chopper amplifiers - Google Patents

Abstract

An apparatus, comprising: a programmable memory (9) configured to generate a first control signal (CTL1); anda chopper amplifier (10, 50, 60, 70, 75, 80, 84, 85, 88, 90, 310, 320) configured to amplify a differential input voltage signal to produce an output signal, the chopper amplifier ( 10, 50, 60, 70, 75, 80, 84, 85, 88, 90, 310, 320) comprises: a first differential transistor array (14, 86) having a selection circuit and a plurality of transistors, the selection circuit being configured to have a first part of the plurality of transistors for operation in a first transistor group (6a) based on the first control signal (CTL1), and wherein the selection circuit is further configured to connect a second part of the plurality of transistors for operation in a second transistor group (6b ) on the basis of the first control signal (CTL1), wherein an input offset voltage of the chopper amplifier (10, 50, 60, 70, 75, 80, 84, 85, 88, 90, 310, 320) is selected on the basis of a selection of the transistors in the first and the second transistor group varies.

Description

BACKGROUND

area

Embodiments of the invention relate to electronic devices, and more particularly to chopper amplifiers.

Description of the associated technology

An amplifier such. An operational amplifier or instrumentation amplifier may include chopper circuitry for reducing the input offset voltage of the amplifier. For example, in a conventional chopper amplifier, input chopping switches can be used to chop or modulate the input signal of the amplifier during an input chopping operation, thereby increasing the frequency of the amplifier's input signal. In addition, the amplifier may include a filter for filtering the input offset of the amplifier, which may be frequency separated from the chopped input signal. The amplifier may further include output chopping switches for demodulating or reducing the frequency of the chopped input signal during an output chopping operation.

Although the inclusion of chopper circuitry in an amplifier can reduce the input offset voltage of the amplifier, chopping can also produce ripples in the output of the amplifier at the chopping frequency and at harmonics thereof.

In the US 6,262,626 B1 there is disclosed an amplifier which is provided with a pair of choppers to reduce the DC offset and noise generated by the amplifier (AMP). To ensure optimum noise reduction, the chopper pairs operate at a high frequency.

There is a need for amplifiers with improved performance. In addition, there is a need for chopper amplifiers with reduced input offset voltage and reduced output ripple.

SUMMARY

In one embodiment, an apparatus includes a programmable memory configured to generate a first control signal and a chopper amplifier configured to amplify a differential input voltage signal to produce an output signal. The chopper amplifier comprises a first differential transistor array with a selection circuit and a plurality of transistors. The selection circuit is configured to select a first portion of the plurality of transistors for operation in a first transistor group based on the first control signal and to select a second portion of the plurality of transistors for operation in a second transistor group based on the first control signal. An input offset voltage of the chopper amplifier varies based on a selection of transistors in the first and second transistor groups.

In a further embodiment, a method for calibrating a chopper amplifier is provided. The method includes observing an input offset voltage of the chopper amplifier for each of a plurality of selected transistor configurations of a first differential transistor row of the chopper amplifier. The first differential transistor series comprises a plurality of transistors, and the selected transistor configurations include various combinations of the plurality of transistors in a first transistor group and in a second transistor group. The method further includes selecting a transistor configuration based on the observations of the input offset voltage and in a programmable memory storing data corresponding to the selected transistor configuration.

list of figures

• 1A Fig. 10 is a schematic block diagram illustrating one embodiment of an integrated circuit (IC).
• 1B and 1C FIG. 12 are schematic block diagrams of a differential transistor array according to an embodiment. FIG.
• 2-7 FIG. 12 are circuit diagrams of chopper amplifiers according to various embodiments. FIG.
• 8A-8D 12 are schematic diagrams of differential transistor arrays according to various embodiments.
• 9 is a circuit diagram of an implementation of a chopper circuit.
• 10 is a circuit diagram of a chopper amplifier according to another embodiment.
• 11 is a circuit diagram of a chopper amplifier according to another embodiment.
• 12A FIG. 12 is a circuit diagram of a chopping differential transistor array according to one embodiment. FIG.
• 12B FIG. 12 is a circuit diagram of a chopping differential transistor series according to another embodiment. FIG.
• 13 FIG. 10 is a flow chart of a method for calibrating a chopper amplifier according to an embodiment. FIG.
• 14 FIG. 10 is a flow chart of a method for calibrating a chopper amplifier according to another embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description of certain embodiments illustrates various descriptions of specific embodiments of the invention. However, the invention may be embodied in a variety of different ways as defined and covered by the claims. In this description, reference is made to the drawings, in which like reference numerals may indicate identical or functionally similar elements.

For certain applications such. For example, with high precision amplification, it may be desirable for an amplifier to have a low input offset. To assist in achieving a low input offset, certain amplifiers may use automatic zeroing and / or chopping schemes.

Although the use of automatic zero adjustment and / or chopping in an amplifier may reduce input skew, such techniques may have disadvantages. For example, autozeroing may produce a relatively high low-frequency noise power spectral density (PSD) due to broadband noise aliasing in the auto-zero frequency band.

In addition, chopping may reduce the input offset of the amplifier, but may also introduce ripples in the output of the amplifier due to the modulation of the input offset. For example, the chopper amplifier input chopper switches may operate to modulate or boost the frequency spectrum of the input signal by the chopping frequency, and the chopper amplifier output chopper switches may operate to demodulate or reduce the frequency spectrum of the amplified input signal by the chopping frequency. However, the input gain stage of the amplifier may be placed in the signal path of the chopper amplifier after the input chopping switches, and thus the input offset would not be modulated by the input chopping switches. Rather, the input offset in frequency would be modulated or boosted by the output hack switches, which can result in ripples in the output signal at the chopping frequency and at harmonics thereof.

Although a low pass filter may be provided in the signal path of the chopper amplifier to attenuate frequency components associated with the input offset, the low pass filter may not completely filter out the input offset and / or may reduce the bandwidth of the chopper amplifier below the chopping frequency. Further, even if the chopping frequency is selected to be relatively high to provide a relatively broad bandwidth, the high chopping frequency may increase charge injection related artifacts and may result in a reduction in amplifier settling time with concomitant increase in power consumption. In other configurations, the bandwidth may be extended by configuring the chopper amplifier to include multiple gain paths. However, such configurations may include additional transfer function poles and / or may include one path with high bandwidth, which has a high power consumption, occupies a large amount of chip area and increases the design complexity. Furthermore, such configurations may suffer from path mismatch artifacts.

Devices and methods for chopper amplifiers are provided here. In certain configurations, a chopper amplifier includes at least one differential transistor array, such as a transistor. A row associated with differential input pair transistors, differential load transistors or differential cascode transistors of the amplifier. Each differential transistor array may comprise a selection circuit and a plurality of transistors, and the selection circuit may select a first portion of the transistors for operation in a first transistor group and a second portion of the transistors for operation in a second transistor group. During calibration, the input offset of the chopper amplifier can be observed or measured for different transistor configurations of the differential transistor arrays. Although the transistors of a particular row may be designed to have approximately the same drive strength and / or geometry, the chopper amplifier may have a different input offset in different transistor configurations. For example, before chopping, the chopper amplifier may have different amounts of input offset voltage in different transistor configurations. For example, the input offset of the chopper amplifier may be at different transistor configurations due to a manufacturing mismatch between transistors, such as. A manufacturing mismatch associated with process variation.

Although a chopper amplifier may have a relatively small amount of input offset when the amplifier chops, the input offset voltage of the amplifier may be converted to output voltage ripple before chopping by the chopping operations. Consequently, it may be desirable for the chopper amplifier to have a low input offset voltage prior to chopping. Thus, the chopper amplifiers can be programmed here to operate with the selected transistor configurations of the differential transistor arrays to provide the amplifier with a low input offset.

The chopper amplifiers herein can achieve a low input offset with a relatively small effect on the size, power consumption and / or gain characteristics of the amplifier relative to certain other input offset reduction schemes. Further, certain chopper amplifiers herein may have a small output ripple, a small input offset current, a low input offset drift, and / or a low flicker noise.

Overview of chopper amplifiers with reduced input offset

1A FIG. 12 is a schematic block diagram illustrating one embodiment of an integrated circuit (IC). FIG. 20 represents. The IC 20 includes a programmable memory 9 and a chopper amplifier 10 ,

The programmable memory 9 can be a programming signal PGRM which can be used to a state of programmable memory 9 to program. Even though 1A the programmable memory 9 as a programming signal receiving, the programmable memory 9 receive additional programming signals and / or the programming signal PGRM can span several bits. The programmable memory 9 can be a control signal CTL based on the state of the programmable memory. Even though 1A the programmable memory 9 represents as a control signal generating, the programmable memory 9 generate additional control signals. In certain implementations, the programmable memory may be 9 generate a plurality of control signals and / or the control signal CTL can span several bits.

The illustrated chopper amplifier 10 includes an input chopping circuit 1 , an output chopping circuit 2 and a differential transistor array 4 , The chopper amplifier 10 can the control signal CTL and an input signal that is a difference between a positive or non-inverted input voltage V _{IN +} and a negative or inverted input voltage V _IN- corresponds, received. In addition, the chopper amplifier 10 amplify the input signal to an output voltage V _OUT to create.

Even though 1A represents a configuration in which the chopper amplifier 10 generates an unbalanced output voltage signal, the chopper amplifier 10 be configured to generate other output signals including, for example, a differential output voltage signal, an asymmetrical output current signal, a differential output current signal, or a combination thereof. Even though 1A the chopper amplifier 10 in an open-loop configuration, the chopper amplifier can 10 also be used in closed loop.

The input and output chopping circuits 1 . 2 can be used to perform input or output chopping operations on the input signal to compensate for the error in the output voltage V _OUT , which is assigned to the input offset voltage of the chopper amplifier to reduce. The input chopping circuit 1 can be used to chop or modulate the input signal before passing through an input gain stage of the chopper amplifier 10 is reinforced. The output chopping circuit 2 can be used to chop or demodulate the amplified differential input signal, which can be further amplified and / or otherwise processed to the output voltage V _OUT to create.

The differential transistor series 4 may comprise at least a first terminal, a second terminal, a selection circuit and a plurality of transistors. The plurality of transistors may be individually selected for operation in a first transistor group or subcircuit associated with the first terminal or for operation in a second transistor group or subcircuit associated with the second terminal. The differential transistor series 4 can along the gain path of the chopper amplifier 10 be arranged. For example, in certain implementations, the differential transistor series 4 as differential input transistors, differential load transistors or differential cascode transistors of the chopper amplifier 10 work. In certain implementations, the transistors have approximately the same geometry Lithography masks on which for the production of the IC 20 be used.

As in 1A shown, the differential transistor series 4 a control signal CTL from a programmable memory 9 receive. The control signal CTL Can be used to drive the differential transistor 4 with a special configuration of transistors that are coupled to the terminals of the series to configure. The selection circuit of the series can, for example, the control signal CTL to select a first portion of the transistors for operation in the first transistor group and a second portion of the transistors for operation in the second transistor group.

During device fabrication, each transistor can be driven by the differential transistor array 4 suffer an arbitrary offset voltage, which coincides with the operating point such. As the temperature, the supply voltage, the bias current and / or the common mode input voltage can vary. For a given transistor configuration, the total offset of the differential transistor series of selectively connected transistors may be approximately equal to the sum of all the offsets of the transistors in the first transistor group of the row minus a sum of all the offsets of the transistors in the second transistor group of the row.

In certain configurations, the input offset of the chopper amplifier 10 during calibration for a variety of transistor configurations of the differential transistor array 4 to be observed. In addition, the data can be used to provide a special transistor configuration of the differential transistor array 4 with a low input offset. In addition, the programmable memory 9 be programmed with data corresponding to the selected transistor configuration, so that the chopper amplifier 10 with the selected transistor configuration of the differential transistor series 4 works during operation. Examples of calibration processes for a chopper amplifier such. B. the chopper amplifier 10 will be described below with reference to 13 and 14 further described.

Consequently, the differential transistor series 4 of the chopper amplifier 10 be programmed to have a transistor configuration with a reduced minimum input offset relative to other possible transistor configurations of the differential transistor array 4 includes. The low input offset may also result in a small output ripple and / or a low input offset current associated with the charging and discharging of the input capacitance during chopping.

In certain configurations, the programmable memory may be 9 a nonvolatile memory including, for example, a flash memory, a read only memory (ROM), a memory implemented using fuses and / or antifuses, and / or a magnetic memory device. Other configurations are possible, such. B. implementations in which the programmable memory 9 is a volatile memory that is programmed during power up or on to include data that corresponds to the selected transistor configuration and / or that is programmed with the data during a calibration sequence.

Even though 1A the chopper amplifier 10 as a differential transistor array, the teachings herein are applicable to configurations in which a chopper amplifier comprises additional differential transistor arrays. In such configurations, the programmable memory 9 be configured to provide additional control signals for the additional differential transistor rows.

1B and 1C are schematic block diagrams of a differential transistor array 8th according to one embodiment. The differential transistor series 8th represents an implementation of the differential transistor series 4 from 1A represents. 1B represents the differential transistor series 8th before configuration by a control signal CTL and 1C shows an example of the differential transistor series 8th after configuration by the control signal CTL represents.

The differential transistor series 8th includes a first port A , a second connection B , first to tenth transistors 5a - 5y and a selection circuit 7 that is configured to receive the control signal CTL to recieve.

The selection circuit 7 can the control signal CTL use a first part of the transistors 5a - 5y for operation in a first transistor group 6a select and a second part of the transistors 5a - 5y for operation in a second subcircuit 6b select.

In certain implementations, the transistors are 5a - 5y designed to have substantially the same drive strength and / or geometry without manufacturing variation, and the selection circuit 7 is configured to have an equal number of transistors in the first and second subcircuit 6a . 6b take.

During the fabrication of an IC with the differential transistor series 8th can any of the transistors 5a - 5y to suffer an arbitrary offset voltage. For a given configuration of the transistors in the first and second subcircuits 6a . 6b may be the total offset of the differential transistor array 8th approximately equal to the sum of the offsets of the transistors in the first subcircuit 6a minus a sum of the offsets of the transistors in the second subcircuit 6b his.

During calibration of a chopper amplifier, the differential transistor array 8th may include various selected combinations of transistors in the first and second subcircuits 6a . 6b and an input offset of the amplifier can be observed for each selected transistor configuration. In certain configurations, an input offset of the amplifier is observed if the amplifier does not chop. In other configurations, a residual input offset of the amplifier is observed as the amplifier chops.

In addition, using the data, a specific transistor configuration may be selected, such as: B. a combination of transistors with the smallest gain input offset. In addition, a programmable memory such. B. the programmable memory 9 from 1A be programmed with data corresponding to the selected transistor configuration. The programmable memory may be the control signal CTL generate that selection circuit 7 can use to select the transistors in the first and second subcircuits 6a . 6b work.

In the example shown, the selection circuit has 7 the control signal CTL used to the second, the third, the fifth and the ninth transistor 5b . 5c . 5e . 5i for operation in the first transistor group 6a select. Besides, the selection circuit has 7 the control signal CTL used to the fourth, the sixth, the seventh and the tenth transistor 5d . 5f . 5g . 5y for operation in the second transistor group 6b select. Furthermore, in the example shown, the first and the eighth transistor 5a . 5h not for operation in either the first or second transistor group 6a . 6b selected.

1C provides an example of a possible distribution of the transistors 5a - 5y between the first and second transistor groups 6a . 6b The in 1C however, the distribution shown is illustrative and the differential transistor series 8th can be programmed in other ways.

Although the illustrated differential transistor series 8th includes ten transistors, a differential transistor series may be designed to include more or less transistors. In one embodiment, a differential transistor array includes between about 4 and about 24 transistors. Other configurations are possible.

As described above, the selection circuit 7 the control signal CTL use a first part of the transistors 5a-5j to select them in the first transistor group 6a and a second part of the transistors 5a-5j to select them in the second transistor group 6b take. In the illustrated configuration, less than all of the transistors 5a-5j for operation in the first and second transistor groups 6a . 6b selected. Other configurations are possible, such. B. implementations in which each of the transistors 5a-5j in either the first transistor group 6a or the second transistor group 6b is recorded.

In certain implementations, the selection circuit may 7 circuitry for selectively picking up any particular transistor in either the first transistor group 6a or in the second transistor group 6b include. However, in other configurations, certain transistors may be selectively included in only a particular transistor group. For example, in one embodiment, the selection circuit selects 7 the first transistor group 6a from a first set or a first collection of transistors and selects the second transistor group 6b of a second set of transistors, wherein at least a portion of the transistors in the first and second sets of transistors are different.

The transistors 5a-5h For example, transistors may correspond to a wide variety of types. In one embodiment, the transistors comprise 5a-5h Field effect transistors (FETs) such. As metal oxide semiconductor transistors (MOS transistors) or junction field effect transistors (JFETs). Other configurations are possible, such. B. implementations in which the transistors 5a-5h Bipolar transistors include.

In certain configurations, the transistors contained in a particular transistor group are electrically connected in parallel. For example, in a configuration using FETs, those for operation in the first sub-circuit may be 6a selected transistors drain, which are connected to each other, sources that are connected to each other, and / or gates that are connected to each other. Likewise, those for operation in the second subcircuit 6b selected transistors drain, which are connected to each other, sources that are connected to each other, and / or gates that are connected to each other.

Even though 1B and 1C the differential transistor array 8th as comprising two terminals, the differential transistor array 8th be designed so that it includes additional connections. In a configuration using FETs, the differential transistor series can 8th For example, terminals may include the drains, sources, and / or gates of the transistors in the first and second subcircuits 6a . 6b assigned. Various examples of differential transistor series will be described in more detail below.

2-7 FIG. 12 are circuit diagrams of chopper amplifiers according to various embodiments. FIG.

2 is a circuit diagram of a chopper amplifier 50 according to one embodiment. The chopper amplifier 50 includes a first or non-inverting input terminal V _{IN +} , a second or inverting input terminal V _IN- , an output terminal V _OUT , an input chopping circuit 11 , a first output chopping circuit 12a , a second output chopping circuit 12b , a power source 13 , a first differential transistor array 14 , First and Second P-Type Metal Oxide Semiconductor Load Transistors (PMOS Transistors) 21 . 22 , first and second PMOS cascode transistors 23 . 24 , First and Second N-Type Metal Oxide Semiconductor Load Transistors (NMOS Load Transistors) 31 . 32 , first and second NMOS cascode transistors 33 . 34 , an output amplification circuit 41 , an integration capacitor 42 and a feedback capacitor 43 ,

As used herein, and as one skilled in the art will appreciate, MOS transistors may include gates made of materials other than metals, such as metals. As polysilicon, and may have dielectric regions that not only with silicon oxide, but with other dielectrics such. B. dielectrics with high k are implemented.

The input chopping circuit 11 includes a first input connected to the non-inverted input terminal V _{IN +} is electrically connected to a second input connected to the inverted input terminal V _IN- is electrically connected, a clock input configured to a Zerhacktaktsignal CLK _CHOP to receive a first output connected to a first gate terminal of the first differential transistor array 14 is electrically connected, and a second output terminal connected to a second gate terminal of the first differential transistor array 14 electrically connected. The power source 13 is between a common source of the first differential transistor series 14 and a first supply voltage V ₁ electrically connected, which may be, for example, a low or power supply. The power source 13 may be used to apply a bias current to the common source of the first differential transistor array 14 to deliver. The first differential transistor array 14 further comprises a control terminal configured to receive a first control signal CTL1 from a programmable memory such. B. the programmable memory 9 from 1A to recieve. The first differential transistor array 14 further includes a first drain connected to a drain of the first PMOS load transistor 21 and a source of the first PMOS cascode transistor 23 electrically connected. The first differential transistor array 14 further includes a second drain connected to a drain of the second PMOS load transistor 22 and a source of the second PMOS cascode transistor 24 electrically connected.

The first PMOS load transistor 21 further includes a gate connected to a first reference voltage V _REF1 and a gate of the second PMOS load transistor 22 electrically connected. The first PMOS load transistor 21 further comprises a source connected to a second supply voltage V ₂ is electrically connected, which may for example be a high power supply. The second PMOS load transistor 22 further includes a source connected to the second supply voltage V ₂ electrically connected. The first PMOS cascode transistor 23 further includes a gate connected to a second reference voltage V _REF2 and a gate of the second PMOS cascode transistor 24 electrically connected. The first PMOS cascode transistor 23 further includes a drain connected to a first input of the first output chopping circuit 12a electrically connected. The second PMOS cascode transistor 24 further includes a drain connected to a second input of the first output chopping circuit 12a electrically connected. The first output chopping circuit 12a further comprises a clock input configured to receive the chopping clock signal CLK _CHOP to recieve. The first output chopping circuit 12a further comprises a first output connected to an inverting input of the output amplifying circuit 41 with a first end of the feedback capacitor 43 and a first input of the second output chopping circuit 12b electrically connected. The first output chopping circuit 12a further comprises a second output coupled to a second input of the second output chopping circuit 12b , with a non-inverting input of the output amplification circuit 41 and a first end of the integration capacitor 42 electrically connected. The integration capacitor 42 further includes a second end connected to the first supply voltage V ₁ electrically connected. The feedback capacitor 43 further comprises a second end connected to an output of the output amplifying circuit 41 and with the output terminal V _OUT electrically connected.

The second output chopping circuit 12b further comprises a clock input configured to receive the chopping clock signal CLK _CHOP receive a first output connected to a drain of the first NMOS cascode transistor 33 is electrically connected, and a second output connected to a drain of the second NMOS cascode transistor 34 electrically connected. The first NMOS cascode transistor 33 further includes a gate connected to a third reference voltage V _REF3 and a gate of the second NMOS cascode transistor 34 electrically connected. The first NMOS cascode transistor 33 further includes a source connected to a drain of the first NMOS load transistor 31 electrically connected. The second NMOS cascode transistor 34 further includes a source connected to a drain of the second NMOS load transistor 32 electrically connected. The first NMOS load transistor 31 further includes a source connected to the first supply voltage V ₁ is electrically connected, and a gate having a fourth reference voltage V _REF4 and a gate of the second NMOS load transistor 32 electrically connected. The second NMOS load transistor 32 further includes a source connected to the first supply voltage V ₁ electrically connected.

In the illustrated configuration, the first differential transistor array becomes 14 used as a differential input transistor pair of the chopper amplifier 50 to work. The first differential transistor array 14 includes several transistors. A first portion of the transistors may operate in a first transistor group associated with the first drain terminal, the first gate terminal, and the common source terminal of the row, and a second portion of the transistors may operate in a second transistor group connected to the second drain terminal, the second gate terminal and the common source of the series is assigned. The first part of the transistors may include, for example, drains electrically connected to the first drain, gates electrically connected to the first gate, and sources electrically connected to the common source. In addition, the second portion of the transistors may include drains electrically connected to the second drain terminal, gates electrically connected to the second gate terminal, and sources electrically connected to the common source terminal. Two example implementations of the first differential transistor series 14 will be described below with reference to 8A-8B further described.

2 FIG. 10 illustrates an example of a chopper amplifier that may include a differential transistor array. The first differential transistor array 14 can be done using the first control signal CTL1 be programmed to work with a special transistor configuration with a low input offset. Although the chopper amplifier 50 from 2 As an example of a chopper amplifier, which may include a differential transistor array, the teachings herein are applicable to a wide variety of chopper amplifiers, including, for example, chopper amplifiers implemented using other circuit topologies.

Even though 2 represents a configuration in which the first differential transistor array 14 In addition, the teachings herein are applicable to configurations using p-type input transistors and / or a combination of n-type and p-type input transistors.

3 is a circuit diagram of a chopper amplifier 60 according to another embodiment. The chopper amplifier 60 from 3 is to the chopper amplifier 50 from 22 similar, except that the chopper amplifier 60 illustrates a configuration in which the first and second PMOS load transistors 21 . 22 from 2 in favor of the inclusion of a second differential transistor series 15 and the first and second NMOS load transistors 31 . 32 from 2 in favor of the inclusion of a third differential transistor array 16 were omitted.

As in 3 includes the second differential transistor array 15 a control terminal configured to receive a second control signal CTL2 to receive a common source connected to the second supply voltage V ₂ is electrically connected, a first drain terminal connected to the source of the first PMOS cascode transistor 23 is electrically connected, a second drain terminal connected to the source of the second PMOS cascode transistor 24 is electrically connected, and a common gate connected to the first reference voltage V _REF1 electrically connected. In addition, the third differential transistor array includes 16 a control terminal configured to receive a third control signal CTL3 to receive a common source connected to the first supply voltage V ₁ is electrically connected, a first drain terminal connected to the source of the first NMOS cascode transistor 33 is electrically connected, a second drain terminal connected to the source of the second NMOS cascode transistor 34 is electrically connected, and a common gate connected to the fourth reference voltage V _REF4 electrically connected.

The second control signal CTL2 can be used to control the transistor configuration of the second differential transistor array 15 to control. In addition, the third control signal CTL3 used to control the transistor configuration of the third differential transistor array 16 to control. The second and the third control signal CTL2 . CTL3 can be controlled by a programmable memory such. B. the programmable memory 9 from 1A be generated.

The inclusion of multiple differential transistor arrays may assist in further reducing an input offset of a chopper amplifier relative to single row configurations. In the illustrated configuration, the first, second, and third differential transistor arrays may be used 14 - 16 separately using the first, second and third control signals, respectively CTL1 - CTL3 be configured to calibrate the low input offset amplifier.

4A is a circuit diagram of a chopper amplifier 70 according to a further embodiment. The chopper amplifier 70 from 7A is similar to the chopper amplifier 60 from 3 except that the chopper amplifier 70 represents a configuration in which the first differential transistor array 14 from 3 in favor of the inclusion of the first and second NMOS input transistors 61 . 62 have been omitted, which operate as a differential input transistor pair of the chopper amplifier.

As in 4A are the sources of the first and second input NMOS transistors 61 . 62 connected together and can the bias current from the power source 13 receive. In addition, the gates of the first and second input NMOS transistors 61 . 62 with the first and the second output of the input chopping circuit 11 electrically connected. Further, the drains of the first and second input NMOS transistors 61 . 62 with the first and the second drain terminal of the differential transistor series 15 electrically connected.

The differential transistor arrays described herein may be included in a wide variety of arrangements in a chopper amplifier. For example, in the illustrated configuration, the differential transistor arrays operate as load transducers of the chopper amplifier. However, the teachings herein are applicable to a wide variety of configurations, including, for example, configurations in which differential transistor arrays operate as differential input pair transistors, differential load transistors, and / or differential chopper transistors of a chopper amplifier.

4B is a circuit diagram of a chopper amplifier 75 according to a further embodiment. The chopper amplifier 75 from 4B is similar to the chopper amplifier 70 from 4A except that the chopper amplifier 75 represents a configuration in which the third differential transistor array 16 from 4A in favor of the inclusion of the first and second NMOS load transistors 31 . 32 was omitted.

In certain implementations, a differential transistor series may be used for PMOS load transistors, but not for NMOS load transistors, or vice versa. Additional details of the chopper amplifier 75 may be similar to those previously described.

5A is a circuit diagram of a chopper amplifier 80 according to a further embodiment. The chopper amplifier 80 from 5A is to the chopper amplifier 50 from 2 similar, except that the chopper amplifier 80 represents a configuration in which the first differential transistor array 14 from 2 in favor of the inclusion of the first and second NMOS input transistors 61 . 62 was omitted. In addition, the chopper amplifier provides 80 a configuration in which the first and second PMOS cascode transistors 23 . 24 from 2 in favor of the inclusion of a fourth differential transistor series 17 and the first and second NMOS cascode transistors 33 . 34 from 2 in favor of the inclusion of a fifth differential transistor series 18 were omitted.

As in 5A includes the fourth differential transistor array 17 a control terminal configured to receive a fourth control signal CTL4 receive a first source terminal connected to the drain of the first PMOS load transistor 21 is electrically connected, a second source terminal connected to the drain of the second PMOS load transistor 22 is electrically connected, a first source terminal connected to the first input of the first output chopping circuit 12a is electrically connected, a second source terminal connected to the second input of the first output chopping circuit 12a is electrically connected, and a common gate connected to the second reference voltage V _REF2 electrically connected. In addition, the fifth differential transistor array includes 18 a control terminal configured to receive a fifth control signal CTL5 receive a first source terminal connected to the drain of the first NMOS load transistor 31 is electrically connected, a second source terminal connected to the drain of the second NMOS load transistor 32 is electrically connected, a first drain terminal connected to the first output of the second output chopping circuit 12b electrically connected, one second drain connected to the second output of the second output chopping circuit 12b is electrically connected, and a common gate connected to the third reference voltage V _REF3 electrically connected.

The fourth control signal CTL4 can be used to control the transistor configuration of the fourth differential transistor array 17 to control. In addition, the fifth control signal CTL5 used to control the transistor configuration of the fifth differential transistor array 18 to control. The fourth and the fifth control signal CTL4 . CTL5 can be controlled by a programmable memory such. B. the programmable memory 9 from 1A be generated. The illustrated configuration leaves the first, second, and third differential transistor arrays 14-16 from 3 path. However, the teachings herein are applicable to a variety of configurations, including, for example, configurations having any combination of the first, second, third, fourth, and / or fifth differential transistor series 14-18 , Additional details of the chopper amplifier 80 may be similar to those previously described.

5B is a circuit diagram of a chopper amplifier 85 according to a further embodiment. The chopper amplifier 85 from 5B is to the chopper amplifier 80 from 5A similar, except that the chopper amplifier 85 represents a configuration in which the fifth differential transistor array 18 from 5A in favor of the inclusion of the first and second NMOS cascode transistors 33 . 34 was omitted.

In certain implementations, a differential transistor array may be used for PMOS cascode transistors, but not for NMOS cascode transistors, or vice versa. Additional details of the chopper amplifier 85 may be similar to those previously described.

5C is a circuit diagram of a chopper amplifier 84 according to a further embodiment. The chopper amplifier 84 includes the input chopping circuit 11 , the first output chopping circuit 12a , the second output chopping circuit 12b , the power source 13 , the output amplification circuit 41 , the integration capacitor 42 , the feedback capacitor 43 and the first and second input NMOS transistors 61 . 62 which may be as previously described. The chopper amplifier 84 further includes a first differential transistor array 86 and a second differential transistor array 87 ,

In certain implementations, a differential transistor array may include a combination of cascode transistors, a load transistor, and / or input transistors that are grouped or paired.

In the illustrated configuration, the first differential transistor array includes 86 for example, multiple PMOS load transistors and multiple PMOS cascode transistors grouped together. In particular, the plurality of PMOS load transistors and the plurality of PMOS cascode transistors are implemented such that a drain of a particular PMOS load transistor is tied to a source of a respective PMOS cascode transistor. Likewise, the second differential transistor array includes 87 a plurality of NMOS load transistors and a plurality of NMOS cascode transistors grouped together. In particular, the multiple NMOS load transistors and the plurality of NMOS cascode transistors are implemented such that a drain of a particular NMOS load transistor is tied to a source of a respective NMOS cascode transistor.

In the illustrated configuration, the control signal CTL4 be used to a first part of the transistor pairs of the first differential transistor series 86 for electrical connection between the drain of the first NMOS input transistor 61 and the first input of the first output chopping circuit 12a and a second portion of the transistor pairs of the first differential transistor array 86 for electrical connection between the drain of the second NMOS input transistor 62 and the second input of the first output chopping circuit 12a select. In addition, the control signal CTL5 be used to a first part of the transistor pairs of the second differential transistor series 87 for the electrical connection between the first input of the second output chopping circuit 12b and the first supply voltage V ₁ and a second portion of the transistor pairs of the second differential transistor array 87 for the electrical connection between the second input of the second output chopping circuit 12b and the first supply voltage V ₁ select.

Although illustrated in the context of differential transistor arrays having transistor groups each comprising a cascode transistor and a load transistor, other configurations are possible. A differential transistor array may include, for example, cascode transistors, load transistors, and / or input transistors that are grouped or paired. Further, in a particular configuration, degeneration resistors are grouped or paired with the transistors of a differential transistor array.

Additional details of the chopper amplifier 84 may be similar to those previously described.

5D is a circuit diagram of a chopper amplifier 88 according to a further embodiment. The chopper amplifier 88 includes the input chopping circuit 11 , the first output chopping circuit 12a , the second output chopping circuit 12b , the power source 13 , the differential transistor array 16 , the first and second PMOS cascode transistors 23 . 24 , the first and second NMOS cascode transistors 33 . 34 , the output amplification circuit 41 , the integration capacitor 42 and the feedback capacitor 43 which may be as previously described. The chopper amplifier 88 further includes a differential transistor array 89 ,

In the illustrated configuration, the differential transistor array includes 89 a plurality of NMOS input transistors and a plurality of PMOS load transistors coupled together. In particular, the plurality of NMOS input transistors and the plurality of PMOS load transistors are implemented such that a drain of a particular NMOS input transistor is tied to a drain of a respective PMOS load transistor. In addition, the control signal CTL1 used to form a first portion of the transistor pairs of the differential transistor array 89 for the electrical connection between the first output of the input chopping circuit 12 and the source of the first PMOS cascode transistor 23 and a second portion of the transistor pairs of the differential transistor array 89 for the electrical connection between the second output of the input chopping circuit 12 and the source of the second PMOS cascode transistor 24 select.

Although illustrated with transistor groups in the context of a differential transistor array, each comprising an input transistor and a load transistor, other configurations are possible. For example, in one embodiment, a differential transistor array includes a plurality of transistor groups each having an input transistor and a load transistor. In another embodiment, a differential transistor array comprises a plurality of transistor groups each having a load transistor and a cascode transistor. In yet another embodiment, a differential transistor array includes a plurality of transistor groups each having an input transistor, a cascode transistor, and a load transistor.

Additional details of the chopper amplifier 88 may be similar to those previously described.

6 is a circuit diagram of a chopper amplifier 90 according to a further embodiment. The chopper amplifier 90 from 6 is to the chopper amplifier 60 from 3 similar, except that the chopper amplifier 90 illustrates another configuration of output chopping circuitry. In contrast to the chopper amplifier 60 from 3 , the first and the second output chopping circuit 12a . 12b includes, includes the chopper amplifier 90 for example, an output chopping circuit 12 ,

As in 6 includes the output chopping circuit 12 a first input connected to the drain of the first PMOS cascode transistor 23 and to the drain of the first NMOS cascode transistor 33 is electrically connected, a second input connected to the drain of the second PMOS cascode transistor 24 and to the drain of the second NMOS cascode transistor 34 is electrically connected, a clock input configured to the Zerhacktaktsignal CLK _CHOP to receive a first output connected to the inverting input of the output amplification circuit 41 and with the first end of the feedback capacitor 43 is electrically connected, and a second output connected to the non-inverting input of the output amplifying circuit 41 and with the first end of the integration capacitor 42 electrically connected.

As those skilled in the art will appreciate, the teachings herein are applicable to a wide variety of input and output hack configurations. The chopper amplifiers here may include, for example, multiple input and / or output chopping circuits. In addition, in certain configurations, one or more of the input and / or output chopping circuits may receive different clock signals, such as clock signals. As clock signals with different delays, overlaps, non-overlaps and / or phases.

As below with reference to 10-12 will be described in more detail, in certain implementations, a chopper circuit may further be integrated with a differential transistor array. The integration of a chopping circuit and a differential transistor array may reduce a number of switches in a signal path relative to a scheme in which the chopper amplifier comprises a separate input chopping circuit and differential transistor array.

7 is a circuit diagram of a chopper amplifier 100 according to a further embodiment. The chopper amplifier 100 from 7 is to the chopper amplifier 50 from 2 similar, except that the chopper amplifier 100 another configuration of the first and the second output chopping circuit 12a . 12b represents.

In the in 7 shown configuration, for example, the first and the second input of first output chopping circuit 12a with drains of the first and the second PMOS load transistor 21 . 22 electrically connected. In addition, the first and second outputs of the first output chopping circuit 12a with sources of the first and the second PMOS cascode transistor 23 . 24 electrically connected. Further, the first and second inputs of the second output chopping circuit 12b with the sources of the first and the second NMOS cascode transistor 33 . 34 electrically connected. In addition, the first and second outputs of the second output chopping circuit 12b with the drains of the first and second NMOS load transistors 31 . 32 electrically connected. Additional details of the chopper amplifier 100 may be similar to those previously described.

8A-8D 12 are schematic diagrams of differential transistor arrays according to various embodiments.

8A is a circuit diagram of a differential transistor series 150 according to one embodiment. The differential transistor series 150 includes a common source S , a first gate connection GA , a second gate terminal GB , a first drain THERE , a second drain connection DB , first to fourth NMOS transistors 121 - 124 , first to fourth drain selection switches 131 - 134 and first to fourth gate selector switches 141 - 144 , The differential transistor series 150 is configured to provide a control signal with a first control bit CTL <1> , a second control bit CTL <2> , a third tax bill CTL <3> and a fourth control bit CTL <4> to recieve. The differential transistor series 150 FIG. 12 illustrates an example implementation of the first differential transistor series. FIG 14 from 2 . 3 . 6 and 7 represents.

In the in 8A the configuration shown are the sources of the first to fourth NMOS transistors 124-124 with the common source connection S electric. In addition, the first to fourth drain selection switches operate 131 - 134 and the first to fourth gate selection switches 141 - 144 as a selection circuit that can be controlled using the control signal of the series. The first to fourth drain selection switches 131-134 For example, the drains of the first to fourth NMOS transistors may be used 121-124 selectively with either the first drain THERE or the second drain DB based on the state of the first control bit CTL <1> , the second control bit CTL <2> , the third control bit CTL <3> or the fourth control bit CTL <4> connect to. In addition, the first to fourth gate selection switches 141 - 144 used to selectively gate the first to fourth NMOS transistors 121 - 124 either with the first gate connection GA or the second gate terminal GB based on the state of the first control bit CTL <1> , the second control bit CTL <2> , the third control bit CTL <3> or the fourth control bit CTL <4> connect to. The part of the transistors connected to the first drain THERE and the first gate terminal GA may be associated with a first transistor group, and the part of the transistors connected to the second drain DB and the second gate terminal GB may be associated with a second transistor group.

In certain implementations, the first to fourth NMOS transistors are 121-124 designed with the same drive strength and / or geometry. The first to fourth drain selection switches 131-134 and the first to fourth gate selection switches 141-144 can be used to make a first part of the NMOS transistors 121-124 with the first drain connection THERE and the first gate terminal GA to connect and to a second part of the NMOS transistors 121-124 with the second drain connection DB and the second gate terminal GB connect to. In certain implementations, the selected configuration of the transistors may be determined during a work test and may be retained in programmable memory on the chip.

Even though 8A 1 illustrates a configuration using four NMOS transistors and associated select circuitry, the differential transistor array may be configured to include a different number of transistors. In an embodiment, the differential transistor array comprises 150 between about 4 and about 24 transistors.

8B is a circuit diagram of a differential transistor series 190 according to another embodiment. The differential transistor series 190 includes a common source S , a first gate connection GA , a second gate terminal GB , a first drain THERE , a second drain connection DB , first to fourth NMOS transistors 151-154 , fifth to eighth NMOS transistors 161-164 , first to fourth drain selection switches 171-174 and fifth to eighth drain selector switches 181-184 , The differential transistor series 190 is configured to provide a control signal with control bits CTLA <1> . CTLA <2> . CTLA <3> . CTLA <4> . CTLB <1> . CTLB <2> . CTLB <3> and CTLB <4> to recieve. The differential transistor series 190 illustrates another example implementation of the first differential transistor series 14 from 2 . 3 . 6 and 7 represents.

In the in 8B the configuration shown are the gates of the first to fourth NMOS transistors 151-154 with the first gate connection GA electrically connected, the gates of the fifth to pay attention to NMOS transistors 161-164 are with the second gate connection GB electrically connected and the sources of the first to eighth NMOS transistors 151-154 . 161-164 are with the common source S electrically connected. In addition, the first to fourth drain selection switches 171-174 be used to selectively part of the first to fourth NMOS transistors 151-154 with the first drain connection THERE to connect to form a first transistor group. In addition, the fifth to eighth drain selection switches 181-184 used to selectively part of the fifth to eighth NMOS transistors 161-164 with the second drain connection DB to connect to form a second transistor group. The first to eighth drain selector switches 171-174 . 181-184 can have a special transistor configuration based on a state of the control bits CTLA <1> . CTLA <2> . CTLA <3> . CTLA <4> . CTLB <1> . CTLB <2> . CTLB <3> or. CTLB <4> choose.

Even though 8B 1 represents a configuration in which the differential transistor array comprises four transistors in two sets or accumulations, other configurations with more or fewer transistors may be used. Further, in certain implementations, each of the sets may include a different number of transistors.

8C is a circuit diagram of a differential transistor series 220 according to a further embodiment. The differential transistor series 220 includes a common source S , a common gate connection G , a first drain THERE , a second drain connection DB , first to fourth NMOS transistors 201-204 and first to fourth drain selection switches 211-214 , The differential transistor series 220 is configured to provide a control signal with a first control bit CTL <1> , a second control bit CTL <2> , a third tax bill CTL <3> and a fourth control bit CTL <4> to recieve. The differential transistor series 220 FIG. 3 illustrates an example implementation of the third differential transistor array. FIG 16 from 3 . 4 and 6 represents.

In the in 8C the configuration shown are the sources of the first to fourth NMOS transistors 201-204 with the common source connection S electrically connected and the gates of the first to fourth NMOS transistors 201-204 are with the common gate connection G electrically connected. In addition, the first to fourth drain selection switches 211-214 selectively, the connection between the drains of the first to fourth NMOS transistors 201-204 and the first or second drain THERE . DB using the first control bit CTL <1> , the second control bit CTL <2> , the third control bit CTL <3> or the fourth control bit CTL <4> control. The part of the transistors connected to the first drain THERE may be associated with a first transistor group and the part of the transistors connected to the second drain DB may be associated with a second transistor group. Additional details of the differential transistor series 220 can be as previously described.

8D is a circuit diagram of a differential transistor series 250 according to a further embodiment. The differential transistor series 250 includes a first source terminal SA , a second source connection SB , a common gate connection G , a first drain THERE , a second drain connection DB , first to fourth NMOS transistors 221-224 , first to fourth source selectors 231-234 and first to fourth drain selection switches 241-244 , The differential transistor series 250 is configured to provide a control signal with a first control bit CTL <1> , a second control bit CTL <2> , a third tax bill CTL <3> and a fourth control bit CTL <4> to recieve. The differential transistor series 250 FIG. 12 illustrates an example implementation of the fifth differential transistor array 18 of FIG 5A represents.

In the in 8D the configuration shown are the gates of the first to fourth NMOS transistors 221-224 with the common gate terminal G electrical. In addition, the first to fourth source select switches 231-234 selectively, the connection between the sources of the first to fourth NMOS transistors 221-224 and the first or second source terminal SA . SB control using the control signal of the series. In addition, the first to fourth drain selection switches 241-244 selectively, the connection between the drains of the first to fourth NMOS transistors 221-224 and the first or second drain THERE . DB control using the control signal. The part of the NMOS transistors connected to the first source SA and the first drain THERE may be associated with a first transistor group, and the part of the NMOS transistors connected to the second source SB and the second drain terminal DB may be associated with a second transistor group. Additional details of the differential transistor array 250 may be as previously described.

Even though 8A-8D Representing differential transistor arrays comprising a plurality of n-type transistors, the teachings herein are applicable to configurations using p-type transistors or a combination of n-type and p-type transistors. For example, in one embodiment, the second differential transistor array becomes 15 from 3 . 4 and 6 using a complementary PMOS configuration of the NMOS differential transistor array 220 from 8C implemented. In another embodiment, the fourth differential transistor array 17 from 5A using a complementary PMOS configuration of the NMOS differential transistor array of 8D implemented. In another embodiment, the chopper amplifier includes p-type differential input transistors and includes a differential transistor array that is constructed using a complementary PMOS configuration of the NMOS differential transistor array of FIG 8A or 8B is implemented.

9 is a circuit diagram of an implementation of a chopper circuit 260 , The input chopping circuit includes first to fourth chopping switches 251-254 , The first to fourth chopper switches 251-254 can be used to chop an input signal between a first input IN1 and a second entrance IN 2 is received to a chopped output signal between a first output OUT1 and a second exit OUT2 to create. The chopping circuit 260 from 9 FIG. 3 illustrates an example implementation of the input and output chopping circuits described herein. However, other configurations are possible.

The first to fourth chopper switches 251-254 operate using a chopping clock signal that includes a first chopping clock signal phase ( CLK ) and a second burst clock signal phase (CLK, ). The first and second chopping switches 251 . 252 for example, the first input IN1 with the first exit OUT1 and the second entrance IN 2 with the second exit OUT2 during the first Zerhacktaktsignalphase connect. In addition, the third and fourth chopper switches 253 . 254 the first entrance IN1 with the second exit OUT2 and the second entrance IN 2 with the first exit OUT1 during the second Zerhacktaktsignalphase connect. In certain configurations, the first chopping clock signal phase and the second chopping clock signal phase may not be overlapping.

In one embodiment, the first to fourth chopping switches 251-254 using MOS transistors such. As NMOS transistors, PMOS transistors or a combination thereof implemented.

10 is a circuit diagram of a chopper amplifier 310 according to a further embodiment. The chopper amplifier 310 from 10 is to the chopper amplifier 50 from 2 similar, except that the chopper amplifier 310 represents a configuration in which the input chopping circuit 11 from 2 and the first differential transistor array 14 from 2 in favor of the use of a chopping differential transistor array 304 are omitted.

As in 10 includes the chopping differential transistor array 304 a first gate connected to the non-inverting input terminal V _{IN +} is electrically connected, a second gate terminal connected to the inverting input terminal V _IN- is electrically connected, a control terminal configured to the first control signal CTL1 receive a clock port configured to receive the chopping clock signal CLK _CHOP to receive a common source, which is configured to the bias current from the power source 13 receive a first drain connected to the drain of the first PMOS load transistor 21 and to the source of the first PMOS cascode transistor 23 is electrically connected, and a second drain connected to the drain of the second PMOS load transistor 22 and to the source of the second PMOS cascode transistor 24 electrically connected.

In certain implementations, a differential transistor array may be integrated with an input chopping circuit to provide a chopping differential transistor array that may reduce a number of switches in a signal path relative to a scheme in which the chopper amplifier includes a separate input chopping circuit and differential transistor array. Two example implementations of the chopping differential transistor series 304 will be described below with reference to 12A-12B further described.

11 is a circuit diagram of a chopper amplifier 320 according to another embodiment. The chopper amplifier 320 from 11 is to the chopper amplifier 310 from 10 similar, except that the chopper amplifier 310 illustrates a configuration in which the first and second PMOS cascode transistors 23 . 24 and the first output chopping circuit 12a from 10 in favor of the inclusion of a second chopping differential transistor series 305 and the first and second NMOS load transistors 31 . 32 and the second output chopping circuit 12b from 10 in favor of including a third chopping differential transistor series 306 were omitted.

As in 11 As shown, an input of the chopper amplifier and / or an output chopping circuitry may be integrated with one or more differential transistor arrays, which may reduce a number of switches in the signal path of the chopper amplifier. Additional details of the chopper amplifier 320 may be similar to those previously described.

12A is a circuit diagram of a chopping differential transistor array 330 according to one embodiment. The chopping differential transistor array 330 includes a common source S , a first gate connection GA , a second gate terminal GB , a first drain THERE , a second drain connection DB , first to fourth NMOS transistors 121-124 , first to fourth drain selection switches 131-134 , first to fourth gate selection switches 141-144 and first to fourth chopping clock signal control switches 321-324 , The chopping differential transistor array 330 is configured to receive a chopping clock signal and a control signal having a first control bit CTL <1> , a second control bit CTL <2> , a third tax bill CTL <3> and a fourth control bit CTL <4> to recieve. The differential transistor series 330 FIG. 4 illustrates an example implementation of the chopping differential transistor series 304 from 10-11 represents.

The chopping differential transistor array 330 from 12A is to the differential transistor array 150 from 8A similar except that the chopping differential transistor series 330 Furthermore, first to fourth Zerhacktaktsignal control switch 321-324 which are used to provide the first to fourth drain selection switches 131-134 and the first to fourth gate selection switches 141-144 to control. The first to fourth clocking clock signal control switches 321-324 work as a multiplexer. Although an implementation of a multiplexer has been illustrated, those skilled in the art will recognize that multiplexing may be provided in other ways.

As in 12A Each of the first through the fourth clock signal control switches may be shown 321-324 between a first burst clock signal phase (CLK) and a second clock clock signal phase (CLK, ) of the Zerhacktaktsignals select. However, those skilled in the art will recognize that other configurations may be used.

The first chopping clock signal control switch 321 can be a first clock signal CLK <1> by selecting between the first and second chopping clock signal phases using the first control bit CTL <1> produce. In addition, the second Zerhacktaktsignal control switch 322 a second clock signal CLK <2> by selecting between the first and second chopping clock signal phases using the second control bit CTL <2> produce. Further, the third Zerhacktaktsignal control switch 323 a third clock signal CLK <3> by selecting between the first and second chopping clock signal phases using the third control bit CTL <3> produce. In addition, the fourth Zerhacktaktsignal control switch 324 a fourth clock signal CLK <4> by selecting between the first and second chopping clock signal phases using the fourth control bit CTL <4> produce. As in 12A shown, the first clock signal CLK <1> , the second clock signal CLK <2> , the third clock signal CLK <3> and the fourth clock signal CLK <4> used to switch operations of the first to fourth drain selection switches 131 - 134 or the first to fourth gate selector switch 141-144 to control.

12B is a circuit diagram of a chopping differential transistor array 350 according to another embodiment. The chopping differential transistor array 350 from 12B is similar to the chopping differential transistor series 330 from 12A except that the chopping differential transistor array 350 the first to fourth chopping clock signal control switches 321 - 324 in favor of the inclusion of combinatorial logic 355 omits.

Additional details of the chopping differential transistor series 350 may be similar to those described above.

13 is a flowchart of a method 500 for calibrating a chopper amplifier according to an embodiment. The procedure 500 can be used to, for example, any of the chopper amplifiers of 1A . 2-7 . 10 or 11 to calibrate. Of course, the methods discussed herein may include more or fewer operations.

The illustrated method 500 to calibrate a chopper amplifier starts in the block 501 in that an input offset of a chopper amplifier is observed over one or more operating conditions for each of a plurality of selected transistor configurations in a differential transistor array. The input offset of the chopper amplifier can be observed in a variety of ways, including, for example, by observing the difference between the non-inverting and inverting inputs of the amplifier or a boosted version thereof when the amplifier is connected using negative feedback. In certain implementations, such a voltage difference can be observed when the chopping clocks are operating under steady state conditions. In another embodiment, the input offset of the chopper amplifier is monitored by observing an amount of a component of the output of the chopper amplifier at the chopping frequency.

In certain implementations, the input offset of the chopper amplifier is observed at several operating conditions, including at least two or more values of the same operating variable. Observing the input offset of the chopper amplifier over a plurality of values of at least one operating variable may be used to determine how the input offset voltage is over an operating range varied. For example, the input offset of an amplifier may vary or vary with temperature, supply voltage, bias current, and common mode input voltage. By observing the input offset voltage over two or more values of at least one operating variable, a transistor configuration that provides a relatively small input offset variation can be selected.

Although the procedure 500 for the case of a differential transistor series chopper amplifier, the chopper amplifier may comprise a plurality of differential transistor arrays and the offset of the chopper amplifier may be observed for each selected transistor configuration of the rows. In certain implementations, the input offset of the chopper amplifier is observed for different transistor configurations from one of the several differential transistor arrays, while the other differential transistor arrays are in a fixed transistor configuration. Once a special differential transistor array has been configured, the process may repeat until all differential transistor arrays are configured. In other implementations, the input offset is observed when the transistor configurations of two or more of the plurality of differential transistor arrays are changed.

In a following block 502 For example, a particular transistor configuration of the differential transistor series is selected with reduced or minimum offset over the one or more operating conditions. In certain configurations, the selected transistor configuration may correspond to a transistor configuration having the smallest input offset at a particular operating point. However, in other configurations, the selected transistor configuration may correspond to a transistor configuration associated with a relatively small change or variation of the input offset over multiple operating conditions. For example, the selected transistor configuration may correspond to a transistor configuration in which the input offset of the amplifier has approximately the smallest drift over changes in temperature, supply voltage, bias current, and / or common mode input voltage. In one embodiment, the selected transistor configuration corresponds to a transistor configuration having about the smallest mean squared error over the range of operating conditions.

The procedure 500 drives in a block 503 in which data corresponding to the selected transistor configuration is stored in a programmable memory such that the chopper amplifier operates with the selected transistor configuration.

In certain implementations, the programmable memory is a nonvolatile memory integrated with the chopper amplifier on the chip or in a common device, and the nonvolatile memory is programmed with the data during the factory test.

Other configurations are possible, such. B. Implementations in which the chopper amplifier is calibrated during power up and / or during a calibration cycle.

14 is a flowchart of a method 510 for calibrating a chopper amplifier according to another embodiment. The procedure 510 can be used, for example, any of the chopper amplifier of 1A . 2-7 . 10 or 11 to calibrate.

The illustrated method 510 to calibrate a chopper amplifier starts in the block 511 in which an input offset of a chopper amplifier is observed over several operating conditions for each of a plurality of selected transistor configurations of a differential transistor array, the selected transistor configurations corresponding to less than all possible transistor configurations of the differential transistor array.

As described above, the input offset of the chopper amplifier may be observed in a variety of ways and may be observed over multiple operating conditions, including two or more values or one pass of at least one operating variable.

In the illustrated method 510 For example, the input offset is observed for less than all possible transistor configurations of the differential transistor array. By observing the input offset for less than all possible transistor configurations, the calibration time of the chopper amplifier can be reduced. In one example, determining the input offset for all transistor configurations of a 16 transistor differential transistor array 16 contain over 8 or 12870 observations. In one embodiment, the input offset is observed for multiple linearly independent transistor configurations.

The procedure 510 drives in a block 512 in which effect data indicating an effect of the series transistors on the input offset over the multiple operating conditions is determined. In certain configurations here, a contribution of each transistor as a vector can be solved. In addition, the contribution of each transistor can be further decomposed into several effects, which themselves can be vectors. In certain configurations, one or more effects may be selectively minimized or reduced. In one embodiment, the effect data includes a plurality of vectors of data representing an effect of the plurality of transistors on the input offset voltage for each of the plurality of operating conditions.

In a following block 513 For example, the effect data is used to select a particular differential transistor array configuration with reduced or minimum offset over the multiple operating conditions. The selected transistor configuration of the differential transistor array may correspond to one of the transistor configurations for which the input offset of the amplifier was observed or a transistor configuration for which the input offset of the amplifier was not observed. In certain implementations, the selected transistor configuration is selected by calculating a linear combination of different combinations of the vectors of the effect data and determining the linear combination having the smallest mean square length.

The procedure 510 can be used to select a transistor configuration that provides a low offset over multiple operating points, such as, for example. Temperature, supply voltage, bias current and / or common mode input voltage. The procedure 510 may involve less calibration time relative to a scheme in which the input offset of the chopper amplifier is observed for each transistor configuration of a differential transistor array.

The procedure 510 drives in a block 514 in which data corresponding to the selected transistor configuration is stored in a programmable memory such that the chopper amplifier operates with the selected transistor configuration.

Additional details of the procedure 510 from 14 can to the before for the procedure 500 from 13 be described similar.

The foregoing description and claims may refer to elements or features as being "connected" or "coupled" together. As used herein, "connected", unless expressly stated otherwise, means that one element / feature is directly or indirectly connected to another element / feature and not necessarily mechanically connected. Likewise, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature and not necessarily mechanically linked. Thus, while the various diagrams shown in the figures represent example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the illustrated circuits is not adversely affected).

applications

Devices using the schemes described above may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, medical imaging and monitoring, consumer electronic products, electronic consumer product parts, electronic test equipment, etc. Examples of the electronic devices may also include memory chips, memory modules, optical network circuits or other communication networks, and disk drive circuits. The electronic consumer products may include a mobile phone, a telephone, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave oven, a refrigerator, a motor vehicle, a stereo system, a cassette recorder or a A cassette player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washing machine, a clothes dryer, a washer-dryer, a copier, a fax machine , a scanner, a multifunction peripheral, a wristwatch, a watch, etc., but are not limited thereto. Furthermore, the electronic device may include unfinished products.

Although this invention has been described in terms of particular embodiments, other embodiments that will be apparent to those skilled in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Moreover, the various embodiments described above may be combined to provide further embodiments. In addition, certain features shown in connection with an embodiment may also be incorporated into other embodiments. Thus, the scope of the present invention is defined only with reference to the appended claims.

Claims (23)

Apparatus comprising: a programmable memory (9) configured to generate a first control signal (CTL1); and a chopper amplifier (10, 50, 60, 70, 75, 80, 84, 85, 88, 90, 310, 320) configured to amplify a differential input voltage signal to produce an output signal, the chopper amplifier (10, 50, 60, 70, 75, 80, 84, 85, 88, 90, 310, 320) comprising: a first differential transistor array (14, 86) having a selection circuit and a plurality of transistors, the selection circuit being configured to select a first portion of the plurality of transistors for operation in a first transistor group (6a) based on the first control signal (CTL1), and wherein the selection circuit is further configured to connect a second portion of the plurality of transistors for operation in a second transistor group (FIG. 6b) based on the first control signal (CTL1), wherein an input offset voltage of the chopper amplifier (10, 50, 60, 70, 75, 80, 84, 85, 88, 90, 310, 320) is selected based on a selection of the transistors in the he and the second transistor group varies. Device after Claim 1 wherein, without manufacturing variation, a drive strength and / or a geometry of each of the plurality of transistors are substantially equal. Device after Claim 1 or 2 wherein the selection circuit is configured to select an equal number of transistors in the first and second transistor groups (6a, 6b). Device after Claim 1 . 2 or 3 further comprising: an input chopping circuit (1,11) having a first input, a second input, a clock input, a first output and a second output, the input chopping circuit configured to convert the differential input voltage signal between the first and second The differential transistor array (14, 86) further comprises a first gate input electrically connected to the first output of the input chopping circuit and a second input terminal Gate input, which is electrically connected to the second output of the input chopping circuit (1, 11) comprises. The apparatus of any preceding claim, wherein the selection circuit of the first differential transistor series comprises a plurality of switches, and wherein the plurality of switches are configured to perform one of an input chopping operation or an output chopping operation of the chopper amplifier (10, 50, 60, 70, 75, 80, 84, 85). 88, 90, 310, 320). The device of any preceding claim, wherein the first differential transistor row is disposed along a gain path of the chopper amplifier (10, 50, 60, 70, 75, 80, 84, 85, 88, 90, 310, 320), the first differential transistor row being one of Differential input transistors of the chopper amplifier (10, 50, 60, 70, 75, 80, 84, 85, 88, 90, 310, 320), chopper amplifier differential load transistors or differential chopper transistors of the chopper amplifier (10, 50, 60, 70, 75, 80, 84 , 85, 88, 90, 310, 320). Apparatus according to any preceding claim, further comprising a second differential transistor array (15, 87), wherein a transistor configuration of said second differential transistor array is controlled by said programmable memory (9) based on a second control signal (CTL2). Device after Claim 7 further comprising a third differential transistor array, wherein a transistor configuration of the third differential transistor array (16) is controlled by the programmable memory (9) based on a third control signal (CTL3), the first differential transistor array (14) operating as differential input transistors of the chopper amplifier second differential transistor array (15) operates as differential load transistors of the chopper amplifier, and wherein the third differential transistor array (16) operates as differential chopper transistors of the chopper amplifier. Apparatus according to any preceding claim, wherein the output signal comprises a single-ended output voltage signal. Apparatus according to any preceding claim, further comprising an integrated circuit (IC), the IC comprising the chopper amplifier and the programmable memory (9). Device after Claim 10 wherein the programmable memory (9) comprises data stored therein, the data associated with a selected state of the first control signal (CTL1), the selected state of the first control signal (CTL1) of a particular transistor configuration of the plurality of transistors in the first and second Transistor group with a smaller input offset compared to at least a second state of the first control signal (CTL1) corresponds. Device after Claim 11 wherein the selected state of the first control signal (CTL1) corresponds to a particular transistor configuration of the plurality of transistors in the first and second transistor groups with a minimum input offset compared to all other states of the first control signal (CTL1). Device after Claim 1 wherein the first differential transistor array is disposed along a gain path of the chopper amplifier, the first differential transistor array (14, 86) comprising a plurality of transistor groups, each of the plurality of transistor groups comprising two or more of an input transistor, a cascode transistor, or a load transistor. A method of calibrating a chopper amplifier, the method comprising: Observing an input offset voltage of the chopper amplifier for each of a plurality of selected transistor configurations of a first differential transistor series of the chopper amplifier (10, 50, 60, 70, 75, 80, 84, 85, 88, 90, 310, 320), the first differential transistor series comprising a plurality of transistors, and wherein the selected transistor configurations comprise different combinations of the plurality of transistors in a first transistor group (6a) and in a second transistor group (6b); Selecting a transistor configuration based on the observations of the input offset voltage; and in a programmable memory (9) storing data corresponding to the selected transistor configuration. Method according to Claim 14 wherein the selected transistor configurations comprise less than all possible transistor configurations of the differential transistor array. Method according to Claim 14 or 15 and further comprising: determining effect data for each differential transistor array transistor using observations of the input offset voltage, wherein the selected transistor configuration is selected based at least in part on the effect data. Method according to Claim 16 wherein the selected transistor configuration is not from the plurality of selected transistor configurations. Method according to Claim 16 or 17 further comprising observing the input offset voltage for each of the plurality of selected transistor configurations for each of a plurality of operating conditions, the plurality of operating conditions comprising two or more values of at least one operating variable. Method according to Claim 18 wherein determining the effect data comprises determining a plurality of vectors with data representing an effect of the plurality of transistors on the input offset voltage for each of the plurality of operating conditions. Method according to Claim 19 In addition, selecting the particular combination further comprises determining a linear combination of the least mean square length vectors. Method according to Claim 18 or 19 wherein the at least one operating variable comprises one or more of the temperature, the supply voltage, the bias current, or the common mode input voltage. Method according to Claim 14 or any of Claim 14 dependent claim, further comprising: retrieving the stored data when turning on the IC (20); and applying the stored data such that the chopper amplifier operates with the selected transistor configuration. Method according to Claim 14 or any of Claim 14 dependent claim, wherein the first differential transistor series along an amplification path of the chopper amplifier (10, 50, 60, 70, 75, 80, 84, 85, 88, 90, 310, 320) is arranged, wherein the first differential transistor series comprises a plurality of transistor groups, each the plurality of transistor groups comprises two or more of an input transistor, a cascode transistor or a load transistor.

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