CN104426493B

CN104426493B - The apparatus and method of chopper amplifier

Info

Publication number: CN104426493B
Application number: CN201410418603.3A
Authority: CN
Inventors: 周捷; A·J·卡尔布; M·D·莱西格
Original assignee: Analog Devices Inc
Current assignee: Analog Devices Inc
Priority date: 2013-08-23
Filing date: 2014-08-22
Publication date: 2018-04-27
Anticipated expiration: 2034-08-22
Also published as: CN104426493A

Abstract

The apparatus and method that chopper amplifier is provided herein.In some configurations, chopper amplifier includes at least one difference transistor pond with selection circuit and multiple transistors.Selection circuit can select the Part I of the transistor operated in the first transistor group, and the Part II of the transistor operated in second transistor group.During calibration, the different crystal pipe in difference transistor pond is configured, the input biasing of Chopper amplifiers can be observed.Although the transistor of particular pool can be designed as having about the same driving intensity and/or geometry, since the manufacture between transistor mismatches (such as process deviation), chopper amplifier can have different inputs in different transistor configurations.Chopper amplifiers can be programmed to using the selected transistor configuration operation in difference transistor pond to provide the amplifier with low input biasing.

Description

The apparatus and method of chopper amplifier

Technical field

The embodiment of the present invention is related to electronic equipment, and more particularly, to chopper amplifier.

Background technology

Amplifier (such as, operational amplifier or instrument amplifier) can include chopper circuit, for step-down amplifier Input offset voltage.For example, in conventional chopper amplifier, input chopping switch can be used to cut during chopping operation chop or The input signal of amplifier is adjusted, so that the frequency of the input signal of up-conversion amplifier.In addition, amplifier may include to filter Device, for filtering the input deviation of the amplifier, it can be in frequency independently of chopped input signal.Amplifier can be with Including exporting chopping switch, for the frequency of demodulation or down coversion chopped input signal during chopping operation is exported.

Although including the input offset voltage that chopper circuit can reduce amplifier in the amplifier, copped wave can also cut Wave frequency rate and its harmonic wave generate ripple (ripple) in the output signal of the amplifier.

In the presence of for the needs with the amplifier for improving performance.In addition it is also necessary to reduction input offset voltage With the chopper amplifier of the output voltage ripple of reduction.

The content of the invention

In one embodiment, a kind of device includes：Programmable storage, is configured as producing first control signal, and One chopper amplifier, is configured to amplification differential input voltage signal to produce output signal.Chopper amplifier includes：Including First difference transistor pond of selection circuit and multiple transistors.Selection circuit is configured as based on first control signal selection the Multiple transistors of a part, for the operation in the first transistor group, and based on first control signal selection Part II Multiple transistors, for the operation in second transistor group.The input offset voltage of chopper amplifier is according to first and In two-transistor group transistor selection and it is different.

In another embodiment, there is provided a kind of method for calibrating chopper amplifier.This method includes：Observe copped wave Amplifier is inclined for the input of each of multiple selected transistor configurations in the first difference transistor pond of Chopper amplifiers Put voltage.First difference transistor pond includes multiple transistors, and selected transistor arrangement includes：The first transistor group and The various combination of multiple transistors in two group transistor groups.This method further comprises：Sight based on the input offset voltage Examine and selection transistor configuration, and storage corresponds to the data of selected transistor configuration in programmable storage.

Brief description of the drawings

Figure 1A is the schematic block diagram of the one embodiment for showing integrated circuit (IC).

Figure 1B and 1C is the schematic block diagram according to the difference transistor pond of one embodiment.

Fig. 2-7 is the circuit diagram of chopper amplifier according to various embodiments.

Fig. 8 A-8D are the circuit diagrams in difference transistor pond according to various embodiments.

Fig. 9 is the circuit diagram of an embodiment of chopper circuit.

Figure 10 is the circuit diagram of chopper amplifier according to another embodiment.

Figure 11 is the circuit diagram of chopper amplifier according to another embodiment.

Figure 12 A are the circuit diagrams according to the copped wave difference transistor pond of one embodiment.

Figure 12 B are the circuit diagrams in copped wave difference transistor pond according to another embodiment.

Figure 13 is the flow chart for the method that chopper amplifier is calibrated according to one embodiment.

Figure 14 is the flow chart for the method for calibrating chopper amplifier according to another embodiment.

Embodiment

Some embodiments it is described in detail below in propose the various descriptions of the particular embodiment of the present invention.However, this Invention can be embodied in various ways.In the present specification, attached drawing is with reference to, wherein similar reference numeral can be with Indicate identical or functionally similar element.

Some applications for such as high-precision amplification, it is desirable to which there is the amplifier of low input biasing.In order to help to realize Low input biasing, some amplifiers can use auto zero and/or copped wave plan.

Although input biasing can be reduced using auto zero and/or copped wave in the amplifier, this technology can have scarce Point.For example, since broadband noise aliasing enters auto zero frequency range, auto zero can produce of a relatively high low-frequency noise work( Rate spectrum density (PSD).

In addition, copped wave can reduce the input biasing of amplifier, but due to the modulation of input biasing, can also be in amplifier Output signal in introduce pulsation.For example, the input chopping switch of Chopper amplifiers can be operated with by chopping frequency tune The frequency spectrum of section or up-conversion input signal, and the output chopping switch of Chopper amplifiers can be operated with by chopping frequency solution Adjust or amplify to down coversion the frequency spectrum of input signal.Opened however, the input amplifying stage of amplifier can be positioned in input copped wave In the signal path of chopper amplifier after pass, and thus input biasing will not be modulated by input chopping switch.But Input biasing will be output chopping switch modulation or upconvert, it can be in chopping frequency and its harmonic wave cause output signal Ripple.

It is related to inputting biasing to decay although low-pass filter may be provided in the signal path of chopper amplifier The frequency component of connection, low-pass filter can incompletely filter out input biasing and/or can be reduced below cutting for chopping frequency The bandwidth of twt amplifier.In addition, even if when chopping frequency is selected as of a relatively high to provide relatively wide bandwidth, high copped wave frequency Rate can increase electric charge and inject relevant distortion (artifact), and can cause stabilization time and the work(for reducing amplifier Rate consumption thing followed increase.In other configurations, bandwidth can be by configuring chopper amplifier with including multiple amplification paths Footpath is extended.However, such configuration can include the limit of additional transmission function and/or can include having high power Consume, occupy the high bandwidth path of a large amount of chip areas, and add the complexity of design.In addition, such configuration can meet with By the unmatched distortion in path.

Apparatus and method for chopper amplifier are provided herein.In some configurations, chopper amplifier is included extremely A few difference transistor pond, is such as total to the difference common source of, differential load transistor or amplifier with differential input transistor The pond that gate transistor is associated.Each difference transistor pond can include selection circuit and multiple transistors, and selection circuit It can select the Part I of transistor for being operated in the first transistor group and for being grasped in second transistor group The Part II of the transistor of work.During calibration, the input biasing of Chopper amplifiers can be for difference transistor pond The configuration of different crystal pipe is observed or measured.Although the transistor of particular pool can be designed as having about the same driving Device intensity and/or geometry, chopper amplifier can have different inputs to bias in different transistor configurations.Example Such as, before copped wave, chopper amplifier can have different input offset voltage amounts in different transistor configurations.Input The amount of bias of chopper amplifier can change as different transistor configures, due to the manufacture mismatch between transistor, such as The manufacture mismatch being associated with change in process.

Although chopper amplifier can show the input biasing of relatively small amount, putting before copped wave when amplifier copped wave The input offset voltage of big device can be converted into output voltage ripple by chopping operation.Therefore, before copped wave, chopper amplifier It is preferable with low input offset voltage.Therefore, the Chopper amplifiers of this paper can be programmed to operation difference transistor The selected transistor configuration in pond, to provide the amplifier with low input biasing.

The chopper amplifier of this paper can realize low input biasing, and Reduced measures are biased relative to some other inputs, Relatively small influence can be produced on the size, power consumption and/or amplification characteristic of amplifier.In addition, some copped waves of this paper are put Big device can have small output ripple, small input bias current, low input offset drift and/or low flash noise.

The general introduction of chopper amplifier with low input biasing

Figure 1A is the schematic block diagram for the embodiment for showing integrated circuit (IC) 20.Integrated circuit 20 includes programmable storage Device 9 and chopper amplifier 10.

Programmable storage 9 can receive programming signal PGRM, it can be used for the state for programming programmable storage 9. Although Figure 1A, which shows programmable storage 9 as a programming signal, programmable storage 9 is received, can receive extra programming Signal and/or programming signal PGRM can include multiple positions.Programmable storage 9 can the shape based on the programmable storage State generation control signal CTL.Although Figure 1A shows programmable storage 9 to produce a control signal, programmable storage 9 can To produce additional control signal.In some embodiments, programmable storage 9 can generate multiple control signal and/or Control signal CTL can include multiple positions.

Shown chopper amplifier 10 includes input chopper circuit 1, output chopper circuit 2 and difference transistor pond 4.Copped wave Amplifier 10 can receive control signal CTL and input signal, corresponding to just or non-inverting input voltage V_IN+With it is negative or anti-phase defeated Enter voltage V_IN-Between difference.In addition, the chopper amplifier 10 can amplify input signal, to produce output voltage V_OUT。

Although Figure 1A is shown in which that chopper amplifier 10 produces the configuration of single ended output voltage signal, the chopper is put Big device 10 can be used for producing other output signals, including for example, differential output voltage signal, Single-end output current signal, difference Divide output current signal, or combinations thereof.In addition, although Figure 1A shows the Chopper amplifiers 10 in open-loop configuration, cut Ripple device amplifier 10 can be used for closed loop.

Output and input chopper circuit 1,2 to can be used for outputting and inputting chopping operation to input signal execution respectively, to subtract Few output voltage V associated with the input offset voltage of Chopper amplifiers_OUTIn error.By chopper amplifier 10 Input before amplifying stage amplification, input chopper circuit 1 can be used for cutting chopping or modulating input signal, and output chopper circuit 2 can be used to The differential input signal for chopping or demodulating amplification is cut, so as to be further amplified and/or otherwise handle to produce output Voltage V_OUT。

Difference transistor pond 4 may include at least the first terminal, Second terminal, selection circuit and multiple transistors.It is described more A transistor, which can be individually chosen, to be used in the first transistor group or with being operated in the relevant sub-circuit of the first terminal, or is used for In second transistor group or with being operated in the relevant sub-circuit of Second terminal.Difference transistor pond 4 can be placed in along chopper and put The amplification path of big device 10.For example, in some embodiments, difference transistor pond 4 can be as the difference of chopper amplifier 10 Divide input transistors, differential load transistor or differential cascade transistor.In some implementations, the transistor is for making Making has about identical geometry on the mask of IC20.

As shown in Figure 1A, difference transistor pond 4 can receive control signal CTL from programmable storage 9.Control signal CTL can be used to configure particular configuration of the difference transistor pond 4 with the transistor coupled with the terminal in pond.For example, the selection in pond Circuit can select the Part I of transistor for being operated in the first transistor group and using control signal CTL The Part II of the transistor operated in two-transistor group.

In device fabrication, each transistor in difference transistor pond 4 can produce random bias voltage, it can be with work Make point and change, such as temperature, supply voltage, bias current and/or input common mode voltage.Configured for given transistor, Transistor in the integral biased the first transistor group that may approximately equal to pond in the difference transistor pond of the transistor selectively connected The sum of all biasings subtract the sum of all biasings of transistor in the second transistor group in pond.

In some configurations, the input biasing of chopper amplifier 10 can match somebody with somebody in the various transistors in difference transistor pond 4 Observed in the calibration process put.In addition, data can be used for the specific crystalline substance in difference transistor pond 4 of the selection with low input biasing Body pipe configures.In addition, the programmable storage 9 can use the data for corresponding to the configuration of selected transistor to be programmed so that Chopper amplifier 10 is operated with together with the difference transistor pond 4 of selected transistor configuration in operation.Will be below in reference to Figure 13 and 14 further describes the example of the chopper amplifier (such as, Chopper amplifiers 10) of calibration process.

Therefore, the difference transistor pond 4 of Chopper amplifiers 10 can be programmed, with including with relative to differential crystal The reduction of other possible transistor arrangements in pipe pond 4 or the transistor configuration of minimum input biasing.Low input biasing can also Cause small output ripple and/or the low input bias current related with input capacitance is charged and discharged during charging.

In some configurations, programmable storage 9 can be nonvolatile memory, including for example, flash memory, only Read memory (ROM), the memory, and/or magnetic storage apparatus realized using fuse and/or anti-fuse.However, other configurations And it is possible, storage is may be programmed during powering on or opening and/or programmed using data such as wherein during calibrating sequence Device 9 is the embodiment for being programmed to include the volatile memory corresponding to selected transistor configuration data,.

Although the chopper amplifier 10 shown in Figure 1A is the pond for including a difference transistor, teachings herein is suitable for it Middle chopper amplifier includes the configuration in extra difference transistor pond.In such an arrangement, programmable storage (9) can be by Additional control signal is configured to provide for, for additional difference transistor pond.

Figure 1B and 1C is the schematic block diagram according to the difference transistor pond 8 of one embodiment.Difference transistor pond 8 is shown One embodiment in the difference transistor pond 4 of Figure 1A.Figure 1B shows the differential crystal before being configured by control signal CTL Pipe pond 8, and Fig. 1 C show an example in the difference transistor pond 8 after being configured by control signal CTL.

Difference transistor pond 8 includes the first terminal A, Second terminal B, the first to the tenth transistor 5a-5j and selection circuit 7, it is configured as receiving control signal CTL.

The selection circuit 7 can select the crystal for being operated in the first transistor group 6a using control signal CTL The Part I of pipe 5a-5j, and the Part II of the transistor 5a-5j for being operated in the second sub-circuit 6b.

In some embodiments, transistor 5a-5j is designed to have essentially identical driver intensity and/or geometry There is no manufacture deviation, and selection circuit 7 to be configured as including equal number in described first and second sub-circuits 6a, 6b Transistor.

During the manufacture of the IC including difference transistor pond 8, each transistor 5a-5j can cause random biased electrical Pressure.Given configuration for the transistor in first and second sub-circuit 6a, 6b, the integral biased of difference transistor pond 8 can The transistor in the second sub-circuit 6b is subtracted to be approximately equal to the sum of amount of bias of transistor in the first sub-circuit 6a The sum of amount of bias.

During the calibration of the chopper amplifier including difference transistor pond 8, the combinations of the different selections of transistor can be with It is included in first and second sub-circuit 6a, 6b, and the input biasing of amplifier can match somebody with somebody for each selected transistor Put and observed.In some configurations, the biasing of input amplifier is observed when amplifier is not in copped wave.In other configurations, Observe the remaining input biasing of amplifier, and at the same time amplifier in copped wave.

In addition, using data specific transistor can be selected to configure, the input biasing such as with minimum amplifier Transistor combination.In addition, programmable memory (such as, the programmable storage 9 of Figure 1A) can be used corresponding to selected The transistor configuration selected is programmed.Programmable storage can produce control signal CTL, and the selection circuit 7 can be used for selecting The transistor operated in first and second sub-circuit 6a, 6b.

In the example in the figures, selection circuit 7 using control signal CTL with select second, third, the 5th and the 9th crystal Pipe 5b, 5c, 5e, 5i, for being operated in the first transistor group 6a.In addition, selection circuit 7 employs control signal CTL To select the four, the six, the 7th and the tenth transistor 5d, 5f, 5g, 5j, for being operated in the 2nd crystal nest of tubes 6b.In addition, In example illustrated, first and the 8th transistor 5a, 5h be not chosen so as to grasp in first or second group transistor 6a, 6b Make.

Fig. 1 C show the example of the possibility distribution of the transistor 5a-5j between the first and second transistor groups 6a, 6b.So And the distribution shown in Fig. 1 C is illustrative, and difference transistor pond 8 can be programmed in other ways.

Although including 10 transistors in the difference transistor pond 8 of diagram, difference transistor pond may be adapted to include more Or less transistor.In one embodiment, difference transistor pond is including between about 4 to about 24 transistors.However, other Configuration is also possible.

As described above, selection circuit 7 can use control signal CTL with the Part I of selection transistor 5a-5j to wrap Include in the first transistor group 6a and the Part II of selection transistor 5a-5j is to be included in the 2nd 2 transistor group 6b.Scheming In the configuration shown, all or less than transistor 5a-5j be selected for operation in the first and second transistor groups 6a, 6b.So And other configurations are also possible, such as wherein each transistor 5a-5j is included in the first transistor group 6a or the second crystal Embodiment in pipe group 6b.

In some embodiments, selection circuit 7 may include circuit, for selectively in the first transistor group 6a or Two-transistor group 6b includes any specific transistor.However, in other configurations, some transistors selectively can be wrapped only Include in a specific transistor group.For example, in one embodiment, selection circuit 7 is selected from the first transistor group or pond The first transistor group 6a and from the second group transistor select second transistor group 6b, wherein in the Part I group and second group At least part transistor in transistor is different.

Transistor 5a-5h can correspond to polytype transistor.In one embodiment, transistor 5a-5h includes Field-effect transistor (FET), such as metal-oxide semiconductor (MOS) (MOS) transistor or junction field effect transistor (JFET). However, other configurations are also possible, such as wherein transistor 5a-5h includes the embodiment of bipolar transistor.

In some configurations, it is electrically connected in the coupled in parallel that specific transistor group includes.For example, using FET Configuration in, the transistor for operating in the first sub-circuit 6a selection can have the drain electrode being connected with each other, be connected with each other Source electrode and/or the grid being connected with each other.Similarly, the transistor for operating selection in the second sub-circuit 6b can have each other Connected drain electrode, the source electrode being connected with each other and/or the grid being connected with each other.

Although Figure 1B and Fig. 1 C show that difference transistor pond 8 is to include two terminals, difference transistor pond 8 may adapt to Including additional terminal.For example, in the configuration using FET, difference transistor pond 8 can include and in the first and second sub-circuits The terminal that the drain electrode of transistor, source electrode and/or grid are connected in 6a, 6b.The various embodiments in difference transistor pond will be below It is further described.

Fig. 2 is the circuit diagram according to the chopper amplifier 50 of one embodiment.Chopper amplifiers 50 include first or Non-inverting input V_IN+, second or reversed input terminal V_IN-, output terminal V_OUT, input chopper circuit 11, first export copped wave electricity Road 12a, the second output chopper circuit 12b, current source 13, the first difference transistor pond 14, the first and second p-type metal oxides The load transistor 21,22 of semiconductor (PMOS), the first and second PMOS cascode transistors 23,24, the first and second N-shapeds It is the load transistor 31,32 of metal-oxide semiconductor (MOS) (NMOS), the first and second NMOS cascode transistors 33,34, defeated Go out amplifying circuit 41, integrating condenser 42 and feedback condenser 43.

As used herein and it will be understood by those skilled in the art that MOS transistor can have by nonmetallic Material (such as, polysilicon) made of grid, and can have and not have to the dielectric area that silica is implemented, but by it Its dielectric (such as, high-k dielectric).

Input chopper circuit 11 includes：It is electrically connected to the non-inverting input V_IN+First input, be electrically connected to it is anti-phase Input terminal V_IN-The second input terminal, be configured as receiving chopper clock signal CLK_CHOPClock input, be electrically connected to it is described The first of first difference transistor pond 14 exports and is electrically connected to the second grid terminal in the first difference transistor pond 14 Second output.Current source 13 is connected electrically between the common source terminal in the first transistor pond 14 and the first service voltage V1, It for example can be low-power or ground power supply.Current source 13 can be used to provide bias current to the first difference transistor pond 14 Common source terminal.First difference transistor pond 14 further comprises control terminal, is configured as receiving the from programmable storage One control signal CTL1, such as the programmable storage 9 of Figure 1A.First difference transistor pond 14, which further includes, is electrically connected to first The drain electrode of PMOS load transistor 21 and the first drain terminal of the source electrode of the first PMOS cascode transistors 23, the first difference Transistor pond 14 further includes the drain electrode for being electrically connected to second PMOS load transistor 22 and the 2nd PMOS cascades Second drain terminal of the source electrode of transistor 24.

First PMOS load transistor 21, which further includes, is electrically connected to the first reference voltage V_REF1With second PMOS load The grid of the grid of transistor 22, the first PMOS load transistor 21, which further includes, is electrically connected to second source voltage source V₂, (it can To be, for example, high power power) source electrode.Second PMOS load transistor 22, which further includes, is electrically connected to second source voltage V2's Source electrode.First PMOS cascode transistors 23, which further include, is electrically connected to the second reference voltage V_REF2With the 2nd PMOS cascades The grid of the grid of transistor 24.First PMOS cascode transistors 23, which further include, is electrically connected to the first output copped wave electricity The drain electrode of the first input of road 12a.2nd PMOS cascode transistors 24, which further include, is electrically connected to the first output chopper circuit The drain electrode of the second input of 12a.First output chopper circuit 12a further comprises being configured to receive chopper clock signal CLK_CHOPClock input.First output chopper circuit 12a further includes the inverting input for being electrically connected to output amplifier 41 To the first output of the first input of the first end of feedback condenser 43 and the second output chopper circuit 12b.First output is cut Wave circuit 12a, which is further included, to be electrically connected the second of the second output chopper circuit 12b and is input to the noninverting defeated of output amplifier 41 Enter the second output of the first end of end and integrating condenser 42.Integrating condenser 42, which further includes, is electrically connected to the first supply voltage The second end of V1.Feedback condenser 43 further includes the output for being electrically connected to the output amplifier 41 and output terminal V_OUT's Second end.

Second output chopper circuit 12b further includes the clock input for being configured to receive chopper clock signal CLKCHOP, is electrically connected It is connected to the first output of the drain electrode of the first NMOS cascode transistors 33 and is electrically connected to the 2nd NMOS cascades Second output of the drain electrode of transistor 34.First NMOS cascode transistors 33, which further include, is electrically connected to the 3rd reference voltage V_REF3With the grid of the grid of the 2nd NMOS cascode transistors 34, the first NMOS cascode transistors 33, which further include, to be electrically connected It is connected to the source electrode of the drain electrode of the first NMOS load transistors 31.2nd NMOS cascode transistors 34, which further include, is electrically connected to institute State the source electrode of the drain electrode of the 2nd NMOS load transistors 32.First NMOS load transistors 31, which further include, is electrically connected to described first The source electrode of supply voltage V1 and be electrically connected to the 4th reference voltage V REF4 and the 2nd NMOS load transistors 32 grid grid Pole, the 2nd NMOS load transistors 32, which further include, is electrically connected to the first supply voltage V₁Source electrode.

In the configuration of diagram, the first difference transistor pond 14 is used to operate brilliant for the Differential Input of Chopper amplifiers 50 Body pipe pair.First difference transistor pond 14 includes multiple transistors.The Part I of transistor can drain with the first of pond Operated in the first transistor group that terminal, first grid terminal and public source terminal are associated, and the Part II of transistor It can be grasped in the second transistor group associated with second drain terminal, second grid terminal and public source terminal in pond Make.For example, the Part I of transistor can have be electrically connected to the drain electrode of the first drain terminal, to be electrically connected to the first grid extreme The grid of son, the source electrode for being electrically connected to public source terminal.In addition, the Part II of transistor, which can have, is electrically connected to second The drain electrode of drain terminal, the grid for being electrically connected to second grid terminal, the source electrode for being electrically connected to public source terminal.Will be below Two example embodiments in the first difference transistor pond 14 are further described with reference to Fig. 8 A-8B.

Fig. 2 shows the example that may include the Chopper amplifiers in difference transistor pond.First difference transistor pond 14 can make It is programmed with first control signal CTL1, is configured with operating the special transistor with low input biasing.Although cutting in Fig. 2 Twt amplifier 50 shows an example of the chopper amplifier that can include difference transistor pond, and teaching herein can be applied to Various chopper amplifiers, including for example, using other circuit topologies come the chopper amplifier realized.

In addition, although Fig. 2 shows the configuration that wherein the first difference transistor pond 14 is associated with N-shaped input transistors, this The teaching of text can be applied to the configuration using p-type input transistors, and/or the combination of N-shaped and p-type input transistors.

Fig. 3 is the circuit diagram of chopper amplifier 60 according to another embodiment.The Chopper amplifiers 60 of Fig. 3 are similar to figure Chopper amplifiers 50 in 2, except showing a kind of configuration using Chopper amplifiers 60, first and in wherein Fig. 2 Two PMOS load transistors 21,22 are omitted, so as to including the second difference transistor group 15, and first and second in Fig. 2 NMOS load transistors 31,32 are omitted, so as to including the 3rd difference transistor group 16.

As shown in figure 3, the second difference transistor group 15 includes being configured as the control terminal for receiving second control signal CTL2 Son, be electrically connected to the common source terminal of second source voltage V2, be electrically connected to the source electrode of the first PMOS cascode transistors 23 The first drain terminal, be electrically connected to the 2nd PMOS cascode transistors 24 source electrode the second drain terminal, and electricity It is connected to first reference voltage V_REF1Public grid terminal.In addition, the 3rd difference transistor group 16 includes being configured as Receive the control terminal of the 3rd control signal CTL3, be electrically connected to the first supply voltage V₁Public source terminal, be electrically connected to First drain terminal of the source electrode of the first NMOS cascode transistors 33, be electrically connected to the 2nd NMOS cascades Second drain terminal of the source electrode of transistor 34, and it is electrically connected to the 4th reference voltage V_REF4Public grid terminal.

Second control signal CTL2 can be used for controlling the configuration of the transistor of the second difference transistor group 15.In addition, the Three control signal CTL3 can be used for controlling the configuration of the transistor of the 3rd difference transistor group 16.And second and the 3rd controls letter Number CTL2, CTL3 can be generated by programmable storage (such as, the programmable storage 9 of Figure 1A).

Further reduction chopper amplifier is can aid in relative to the configuration in single pond, including multiple difference transistor ponds Input biasing.In shown structure, the first, the second and the three difference transistor pond 1416 can use first, second He 3rd control signal CTL1-CTL3 is respectively configured, to calibrate the amplifier with low input biasing.

Fig. 4 A are the circuit diagrams of chopper amplifier 70 according to another embodiment.The Chopper amplifiers 70 of Fig. 4 A are similar to Chopper amplifiers 60 in Fig. 3, except chopper amplifier 70 shows a kind of configuration, the first differential crystal in wherein Fig. 3 Pipe pond 14 has been omitted from, so that including the first and second nmos input transistors 61,62, it is defeated as the difference of Chopper amplifiers Enter transistor to operating.

As shown in Figure 4 A, the source electrode of the first and second nmos input transistors 61,62 is connected to each other, and can receive institute Bias current is stated from current source 13.In addition, the grid of the first and second nmos input transistors 61,62 be electrically connected respectively to it is defeated Enter the first and second outputs of chopper circuit 11.In addition, the drain electrode of the first and second nmos input transistors 61,62 is electrically connected respectively It is connected to the first and second drain terminals of the second difference transistor group 15.

Difference transistor pond described herein can be included in the various configurations of chopper amplifier.For example, shown Configuration in, difference transistor pond operation, the load transistor as Chopper amplifiers.However, teaching herein is also suitable In various constructions, including for example, wherein difference transistor pond operation is brilliant to, differential load as differential input transistor The configuration of the difference cascode transistor of body pipe and/or chopper amplifier.

Fig. 4 B are the circuit diagrams of chopper amplifier 75 according to another embodiment.The Chopper amplifiers 75 of Fig. 4 B are similar to The chopper amplifier 70 of Fig. 4 A, difference are that chopper amplifier 75 shows a kind of configuration, wherein the 3rd difference of Fig. 4 A Transistor pond 16 has been left out, so as to including the first and second NMOS load transistors 31,32.

In some embodiments, difference transistor pond can be used for PMOS load transistor, but cannot be used for NMOS and bear Transistor is carried, or vice versa.The additional detail of Chopper amplifiers 75 is described such before can be similar to.

Fig. 5 A are 80 circuit diagrams of chopper amplifier according to another embodiment.The chopper amplifier 80 of Fig. 5 A is similar to Fig. 2 In Chopper amplifiers 50, except chopper amplifier 80 shows a kind of configuration, the first difference transistor pond in wherein Fig. 2 14 have been omitted, so as to including the first and second nmos input transistors 61,62.In addition, chopper amplifier 80 shows one Kind configures, and the first and second PMOS cascode transistors 23,24 in wherein Fig. 2 have been omitted, so as to poor including the 4th Point transistor pond 17, and the first and second NMOS cascode transistors 33,34 in Fig. 2 have been omitted, so as to including 5th difference transistor pond 18.

As shown in Figure 5A, the 4th difference transistor pond 17 includes：It is configured to receive the control of the 4th control signal CTL4 Terminal, be electrically connected to first PMOS load transistor 21 drain electrode the first source terminal, be electrically connected to the 2nd PMOS and bear Carry the second source terminal of the drain electrode of transistor 22, be electrically connected to the first output chopper circuit 12a the first input the Source-side, be electrically connected to the described first the second the second source terminal inputted for exporting chopper circuit 12a and be electrically connected to The second reference voltage V_REF2Public grid terminal.In addition, the 5th difference transistor group 18 includes：It is configured to reception The control terminal of five control signal CTL5, be electrically connected to the first NMOS load transistors 31 drain electrode the first source terminal Second source terminal of drain electrode that is sub, being electrically connected to the 2nd NMOS load transistors 32, be electrically connected to the second output copped wave First drain terminal of the first output of circuit 12b, be electrically connected to the second output chopper circuit 12b the second output the Two drain terminals and it is electrically connected to the 3rd reference voltage V_REF3Common gate terminal.

4th control signal CTL4 can be used for controlling the configuration of the transistor in the 4th difference transistor pond 17.In addition, the Five control signal CTL5 can be used for the configuration of the transistor of the 5th difference transistor group 18 of control.4th and the 5th control signal CTL4, CTL5 can be generated by programmable storage (such as, the programmable storage 9 of Figure 1A).In the construction illustrated Eliminate the first, second, and third difference transistor pond 14-16 of Fig. 3.However, teaching herein is suitable for various configurations, bag Include e.g., including first, second, third, fourth and/or the 5th difference triode pond 14-18 any combination configuration.Copped wave The additional detail of amplifier 80 can be similar to before it is described those.

Fig. 5 B are the circuit diagrams of chopper amplifier 85 according to another embodiment.The chopper amplifier 85 of Fig. 5 B is similar to figure The chopper amplifier 80 of 5A, difference are that chopper amplifier 85 shows a kind of configuration, and the 5th difference of wherein Fig. 5 A is brilliant Body pipe pond 18 has been omitted, so as to including the first and second NMOS cascode transistors 33,34.

In some embodiments, difference transistor pond can be used for PMOS cascode transistors, but be not used in NMOS Cascode transistors, or vice versa.The additional detail of Chopper amplifiers 85 can be similar to before it is described that A bit.

Fig. 5 C are the circuit diagrams of chopper amplifier 84 according to another embodiment.Chopper amplifiers 84 include input copped wave Circuit 11, first exports chopper circuit 12a, the second output chopper circuit 12b, current source 13, output amplifier 41, integration electricity Container 42, feedback condenser 43, and the first and second nmos input transistors 61,62, it can be as previously described.Chopper Amplifier 84 further includes the first difference transistor pond 86 and the second difference transistor pond 87.

In some embodiments, difference transistor group can include cascode transistors, load transistor and/or divide The combination of group or the input transistors of pairing.

For example, in shown configuration, the first difference transistor pond 86 include packet multiple PMOS load transistors and Multiple PMOS cascode transistors.Especially, the multiple PMOS load transistor and the multiple PMOS cascades are brilliant Body pipe is implemented so that the drain electrode of specific PMOS load transistor is connected to the source of corresponding PMOS cascode transistors Pole.Equally, the second difference transistor pond 87 includes multiple NMOS load transistors of packet and multiple NMOS cascades crystal Pipe.Especially, the multiple NMOS load transistors and the multiple NMOS cascode transistors are implemented so that specific The drain electrode of NMOS load transistors is connected to the source electrode of corresponding NMOS cascode transistors.

In the configuration of diagram, control signal CTL4 can be used for selecting transistor pair in the first difference triode group 86 Part I is to be connected electrically in the drain electrode of the first nmos input transistor 61 and the first input of the first output chopper circuit 12a Between, and the transistor pair in the first difference transistor group 86 of selection Part II to be connected electrically in the 2nd NMOS input crystals Between the drain electrode of pipe 62 and the second input of the first output chopper circuit 12a.In addition, control signal CTL5 can be used to select second The Part I of transistor pair in difference triode group 87, to be connected electrically in the first of the second output chopper circuit 12b the input With the first supply voltage V₁Between, and the Part II of the transistor pair in the second difference transistor pond 87 is selected, to be connected electrically in The second input terminal and the first supply voltage V of second output chopper circuit 12b₁Between.

Although including the difference transistor pond of each transistor group including cascode transistors and load transistor Environment in show, other configurations are possible.For example, difference transistor group can include cascode transistors, load crystalline substance Body pipe and/or the input transistors of packet or pairing.In addition, in some configurations, negative feedback resistor is grouped or matches The transistor of difference transistor group.

Other details of the chopper amplifier 84 before being similar to it is described those.

Fig. 5 D are the circuit diagrams of chopper amplifier 88 according to another embodiment.Chopper amplifiers 88 include input copped wave Circuit 11, first exports chopper circuit 12a, the second output chopper circuit 12b, current source 13, difference transistor group 16, the first and 2nd PMOS cascode transistors 23, the 24, first and second NMOS cascode transistors 33,34, output amplifier 41, Integrating condenser 42 and feedback condenser 43, it can be as previously described.Chopper amplifiers 88 further include difference transistor Pond 89.

In the configuration of diagram, multiple nmos input transistors and PMOS that difference transistor pond 89 includes mutually matching are born Carry transistor.Especially, multiple nmos input transistors and multiple PMOS load transistors are implemented so that specific NMOS is defeated The drain electrode for entering transistor is connected to the drain electrode of corresponding PMOS load transistor.In addition, control signal CTL1 can be used for selecting The Part I of transistor pair in difference transistor pond 89, to be connected electrically in the first output terminal and the of input chopper circuit 12 Between the source electrode of one PMOS cascode transistors 23, and the Part II of transistor pair in difference transistor pond 89 is selected, with It is connected electrically between the second output terminal of input chopper circuit 12 and the source electrode of the 2nd PMOS cascode transistors 24.

Although the feelings in the difference transistor pond including each transistor group including input transistors and load transistor Shown under condition, other configurations are possible.For example, in one embodiment, difference transistor pond includes multiple each include The transistor group of input transistors and load transistor.In another embodiment, difference transistor pond includes each of multiple bags Include the transistor group of load transistor and cascode transistors.In another embodiment, difference transistor pond includes multiple crystalline substances Body pipe group, every group includes input transistors, cascode transistors and load transistor.

Other details of the chopper amplifier 88 before being similar to it is described those.

Fig. 6 is 90 circuit diagram of chopper amplifier according to another embodiment.The chopper amplifier 90 of Fig. 6 is similar to Fig. 3's Chopper amplifiers 60, difference are that chopper amplifier 90 shows the different configurations of output chopper circuit.It is for example, opposite In the Chopper amplifiers 60 of Fig. 3 including first and second output chopper circuit 12a, 12b, Chopper amplifiers 90 include defeated Go out chopper circuit 12.

As shown in fig. 6, output chopper circuit 12 include be electrically connected to the first PMOS cascode transistors 23 drain electrode and The first input end of first NMOS cascode transistors 33, the 2nd PMOS cascades of the drain electrode crystalline substance for being electrically connected to the drain electrode Body pipe 24 and to the 2nd NMOS cascode transistors 34 the second input terminal, be configured to receive chopper clock signal CLK_CHOP Clock input, be electrically connected to the inverting input and first input end of clock and feedback condenser of output amplifier 41 First output of 43 drain electrode and be electrically connected to output amplifier 41 non-inverting input and integrating condenser 42 the Second output of one end.

As it will be understood by those skilled in the art that teaching herein is suitable for various inputs, output copped wave configuration. For example, Chopper amplifiers can include multiple input and/or output chopper circuit herein.In addition, in some configurations, one Or multiple input and/or output chopper circuit can receive different clock signals, such as with different delays, overlapping, non-heavy Folded and/or phase clock signal.

In addition, as it is following will be described in further reference to Figure 10 Figure 12, in some embodiments, chopper circuit can To integrate difference transistor pond.Include individually input chopper circuit and difference transistor pond relative to the wherein chopper amplifier Scheme, number of switches in signal path can be reduced by integrating chopper circuit and difference transistor pond.

Fig. 7 is the circuit diagram of Chopper amplifiers 100 according to another embodiment.The chopper amplifier 100 of Fig. 7 is similar to The chopper amplifier 50 of Fig. 2, difference be Chopper amplifiers 100 show the first and second output chopper circuit 12a, The different structure of 12b.

For example, in structure shown in Fig. 7, the first and second input terminals of the first output chopper circuit 12a are electrically connected respectively It is connected to the drain electrode of the first and second PMOS load transistors 21,22.In addition, the first and second of the first output chopper circuit 12a Output terminal is electrically connected to the source electrode of the first and second PMOS cascades difference transistor 23,24.In addition, the second output copped wave The first and second input terminals of circuit 12b are electrically connected to the source of the first and second NMOS cascades difference transistor 33,34 Pole.In addition, the first and second output terminals of the second output chopper circuit 12b are electrically connected respectively to the first and second NMOS loads The drain electrode of transistor 31,32.Other details of Chopper amplifiers 100 before being similar to it is described those.

Fig. 8 A are the circuit diagrams according to the difference transistor pond 150 of one embodiment.Difference transistor pond 150 includes public Source terminal S, first grid terminal GA, second grid terminal GB, the first drain terminal DA, the second drain terminal DB, first to 4th nmos pass transistor 121-124, first to fourth drain electrode selecting switch 131-134, and the selection of first to fourth grid are opened Close 141-144.Difference transistor pond 150, which is configured to receive, has the first control bit CTL<1>, the second control bit CTL<2>, Three control bit CTL<3>With the 4th control bit CTL<4>Control signal.Difference transistor pond 150 show Fig. 2, Fig. 3, Fig. 6 and One illustrative embodiments in 7 the first difference transistor pond 14.

In fig. 8 a in shown structure, the source electrode of first to fourth nmos pass transistor 124-124 arrives public source by electricity Terminal S.In addition, first to fourth drain electrode selecting switch 131-134 and first to fourth grid selecting switch 141-144 operations are Selection circuit that can be using the control signal in pond to control.For example, first to fourth drain electrode selecting switch 131-134 can be used for It is based respectively on the CTL of first control bit<1>, the second control bit CTL<2>, the 3rd control bit CTL<3>With the 4th control bit CTL<4>State the drain electrode of first to fourth nmos pass transistor 121-124 is selectively connected to the first drain terminal DA or Two drain terminal DB.In addition, first to fourth grid selecting switch 141-144 can be used for being based respectively on first control bit CTL<1>, the second control bit CTL<2>In, the 3rd control bit CTL<3>, and the 4th control bit CTL<4>State and optionally The grid of the first to fourth nmos pass transistor 121-124 is connected to first grid terminal GA or second grid terminal GB.Even Being connected to a part of of the transistor of the first drain terminal DA and first grid terminal GA can be associated with the first transistor group, with And it is connected to the second drain terminal DB and the part of second grid terminal GB can be associated with second transistor group.

In some embodiments, the design of first to fourth nmos pass transistor 121-124 has identical driving intensity And/or geometry.The first to fourth grid selecting switch 141-144 of first to fourth drain electrode selecting switch 131-134 can For connecting the Part I of nmos pass transistor 121-124 to the first drain terminal DA and first grid terminal GA, and connect The Part II of nmos pass transistor 121-124 is to the second drain terminal DB and second grid terminal GB.In some embodiments, The configuration of the selection of transistor can be determined during factory testing, and be retained on chip in programmable storage.

Although Fig. 8 A show the structure using four NMOS transistors and Correlation selection circuit, difference transistor pond can fit It should include the transistor of varying number.In one embodiment, difference transistor pond 150 include about 4 to about 24 transistors it Between.

Fig. 8 B are the circuit diagrams in difference transistor pond 190 according to another embodiment.Difference transistor pond 190 includes public Source terminal S, first grid terminal GA, second grid terminal GB, the first drain terminal DA, the second drain terminal DB, first to 4th nmos pass transistor 151-154, the 5th to the 8th nmos pass transistor 161-164, first to fourth drain electrode selecting switch 171- 174 and the 5th to the 8th drain electrode selecting switch 181-184.Difference transistor pond 190, which is configured to receive, has control bit CTLA< 1>、CTLA<2>、CTLA<3>、CTLA<4>、CTLB<1>、CTLB<2>、CTLB<3>And CTLB<4>Control signal.Difference is brilliant Body pipe pond 190 shows the another exemplary embodiment in Fig. 2, Fig. 3, Fig. 6 and 7 the first difference transistor pond 14.

In the structure shown in Fig. 8 B, the gridistor 151-154 of first to fourth NMOS is electrically connected to first grid The gridistor 161-164 of terminal GA, the 5th to the 8th NMOS are electrically connected to second grid terminal GB, and first to the 8th The source electrode of nmos pass transistor 151-154,161-164 are electrically connected to public source terminal S.In addition, first to fourth drain electrode choosing Switch 171-174 is selected to can be used to be selectively connected first to fourth nmos pass transistor 151-154 to the first drain terminal DA, with Form the first transistor group.In addition, the 5th to the 8th drain electrode selecting switch 181-184 can be used the 5th to the 8th NMOS crystal The second drain terminal DB is swept in the partially selectively connection of pipe 161 to 164, to form the second group transistor.First to the 8th leakage Pole selecting switch 171-174,181-184 can be respectively according to control bit CTLA<1>、CTLA<2>、CTLA<3>、CTLA<4>、 CTLB<1>、CTLB<2>、CTLB<3>And CTLB<4>The specific transistor arrangement of condition selecting.

Although Fig. 8 B show that difference transistor pond is included in the composition of four transistors in two groups or two ponds, can also make With the other configurations for including more or less transistors.In addition, in some embodiments, each group can include different numbers Transistor.

Fig. 8 C are the figures of the difference transistor group 220 of circuit according to another embodiment.Difference transistor group 220 includes public Source terminal S, public grid terminal G, the first drain terminal DA, the second drain terminal DB, first to fourth nmos pass transistor The drain electrode selecting switch of 201-204 and first to fourth 211-214.Difference transistor group 220, which is configured to receive, has first The CTL of control bit<1>, the second control bit CTL<2>, the 3rd control bit CTL<3>With the 4th control bit CTL<4>Control signal. Difference transistor group 220 shows the illustrative embodiments in the 3rd difference transistor pond 16 of Fig. 3,4 and 6.

In the structure shown in Fig. 8 C, the source electrode of first to fourth nmos pass transistor 201-204 is electrically connected to public source Terminal S, and the grid of first to fourth nmos pass transistor 201-204 are electrically connected to public grid terminal G.In addition, first to 4th drain electrode selecting switch 211-214 can optionally be utilized respectively the first control bit CTL<1>, the second control bit CTL<2>、 3rd control bit CTL<3>With the 4th control bit CTL<4>Control in the drain electrode of the first to the 4th nmos pass transistor 201-204 and the One or the second connection between drain terminal DA, DB.Being connected to a part of of the transistor of the first drain terminal DA can be with One transistor group is associated, and the part for the transistor being connected in the second drain terminal DB can be with second transistor Group is associated.The additional detail of difference transistor group 220 can be as being described before.

Fig. 8 D are the schematic diagrames in the difference transistor pond 250 of circuit according to another embodiment.Difference transistor pond 250 includes First source terminal SA, the second source terminal SB, public grid terminal G, the first drain terminal DA, the second drain terminal DB, One to the 4th nmos pass transistor 221-224, first to fourth light source selecting switch 231-234 and first to fourth drain electrode selection Switch 241-244.Difference transistor pond 250, which is configured to receive, has the first control bit CTL<1>, the second control bit CTL<2>、 3rd control bit CTL<3>With the 4th control bit CTL<4>Control signal.Difference transistor pond 250 shows the 5th of Fig. 5 A The illustrative embodiments in difference transistor pond 18.

In the configuration shown in Fig. 8 D, the grid of first to fourth nmos pass transistor 221-224 is electrically connected to public grid Terminal G.In addition, first to fourth light source selecting switch 231234 can use pond control signal optionally control first to Connected between the source electrode of 4th nmos pass transistor 221-224 and the first or second source S A, SB.In addition, first to fourth drain electrode Selecting switch 241-244 can optionally control the leakage in the first to the 4th nmos pass transistor 221-224 using control signal Connection between pole and first or second drain terminal DA, DB.It is connected to the first source terminal SA's and the first drain terminal DA The part of nmos pass transistor can be associated with the first transistor group, and is connected to the second source terminal SB and the second drain electrode end The part of the nmos pass transistor of sub- DB can be associated with second transistor group.The more details in difference transistor pond 250 can be with It is described as before.

Although Fig. 8 A-8D show that difference transistor pond includes multiple n-type transistors, teaching herein is applicable to use P-type transistor or N-shaped and the configuration of p-type transistor combination.For example, in one embodiment, Fig. 3, Fig. 4 and 6 the second difference Transistor group 15 is realized using the complementary PMOS structures in the nmos differential transistor pond 220 of Fig. 8 C.In another embodiment In, the 4th difference transistor pond 17 of Fig. 5 A is realized using the complementary PMOS structures in the nmos differential transistor pond of Fig. 8 D. In another embodiment, Chopper amplifiers include p-type differential input transistor, and the NMOS included the use of in Fig. 8 A or 8B is poor The complementary PMOS structures in point transistor pond are come the difference transistor pond realized.

Fig. 9 is the circuit diagram of an embodiment of chopper circuit 260.Input chopper circuit includes first to fourth copped wave Switch 251-254.First to fourth chopping switch 251-254, which can be used to cut, to be chopped in first input end IN1 and the second input terminal IN2 Between the input signal that receives, to produce the chopped output signal between the first output OUT1 and the second output OUT2.Fig. 9's cuts Wave circuit 260 shows the example embodiment described herein for outputting and inputting chopper circuit.However, other configurations are also It is possible.

First to fourth chopping switch 251-254 is manipulated using chopper clock signal, it includes the first chopper clock signal Phase (CLK) and the second chopper clock signal phase (CLK).For example, the first and second chopping switch 251,252 can be first First input end IN1 is connected to the first output OUT1 during chopper clock signal phase and the second input IN2 is connected to the Two output OUT2.In addition, can be during the second chopper clock signal phase by the third and fourth chopping switch 253,254 One input terminal IN1 is connected to the second output OUT2 and the second input IN2 is connected to the first output OUT1.In some configurations, The phase of first chopper clock signal and the phase of the second chopper clock signal can be nonoverlapping.

In one embodiment, MOS transistor used in first to fourth chopping switch 251-254 is realized, such as, Nmos pass transistor, PMOS transistor or combinations thereof.

Figure 10 is the circuit diagram of Chopper amplifiers 310 according to another embodiment.The chopper amplifier 310 of Figure 10 is similar Chopper amplifiers 50 in Fig. 2, except Chopper amplifiers 310 show a kind of configuration, the input copped wave electricity of wherein Fig. 2 Road 11 and the first difference transistor pond 14 of Fig. 2 are omitted, so as to using copped wave difference transistor pond 304.

As shown in Figure 10, copped wave difference transistor pond 304 includes being electrically connected to the first of the non-inverting input VIN+ Gate terminal, the second grid terminal for being electrically connected to reversed input terminal VIN, be configured to receive first control signal CTL1's Control terminal, be configured to receive the clock terminal of chopper clock signal CLKCHOP, be configured to receive biasing from current source 13 The public source terminal of electric current, be electrically connected to the drain electrode of the first PMOS load transistor 21 and brilliant to the first PMOS cascades First drain terminal of the source electrode of body pipe 23 and the drain electrode and described second for being electrically connected to second PMOS load transistor 22 Second drain terminal of the source electrode of PMOS cascode transistors 24.

In some implementations, difference transistor group can integrate input chopper circuit to provide copped wave difference transistor pond, This can include subtracting in the individually scheme in integrated input chopper circuit and difference transistor pond relative to wherein chopper amplifier Digital switch in few signal path.Two example copped wave difference transistors will be described with further reference to Figure 12 A-12B below The realization in pond 304.

Figure 11 is the circuit diagram of Chopper amplifiers 320 according to another embodiment.The chopper amplifier 320 of Figure 11 is similar In the chopper amplifier 310 of Figure 10, difference is that Chopper amplifiers 310 show a kind of configuration, wherein Figure 10's First and second PMOS cascode transistors 23,24 and first output chopper circuit 12a is omitted, so as to including the second copped wave Difference transistor pond 305, and the first and second NMOS load transistors 31,32 and second output chopper circuit of wherein Figure 10 12b is omitted, to include the 306 of the 3rd copped wave difference transistor pond.

As shown in Figure 11, the input of Chopper amplifiers and/or output chopper circuit can be with one or more difference Transistor pond integrates, so as to reduce the number of switches in the signal path of chopper amplifier.Chopper amplifiers 320 Other details before being similar to it is described those.

Figure 12 A are the circuit diagrams according to the copped wave difference transistor pond 330 of one embodiment.Copped wave difference transistor pond 330 include public source terminal S, first grid terminal GA, second grid terminal GB, the first drain terminal DA, the second drain electrode end Sub- DB, first to fourth nmos pass transistor 121-24, first to fourth drain electrode selecting switch 131-34, the choosing of first to fourth grid Select switch 141-44, and first to fourth chopper clock signal controlling switch 321-24.Copped wave difference transistor pond 330 by with It is set to receive chopper clock signal and receive and there is the first control bit CTL<1>, two control bit CTL<2>, the 3rd control bit CTL<3> With the 4th control bit CTL<4>Control signal.Difference transistor pond 330 illustrates that Figure 10's -11 cuts difference transistor pond 304 Example embodiment.

The copped wave difference transistor pond 330 of Figure 12 A is similar to the difference transistor pond 150 in Fig. 8 A, and difference exists First to fourth chopper clock signal controlling switch 321-324 is further included in copped wave difference transistor pond 330, this is for controlling First to fourth drain electrode selecting switch 131-134 and first to fourth grid selecting switch 141-144.First to fourth copped wave 321-324 is as multiplexer for clock signal controlling switch.Although it is stated that an embodiment of multiplexer, ability The those of ordinary skill in domain will be understood that multiplexing can provide in other ways.

As illustrated in fig. 12, each in first to fourth chopper clock signal controlling switch 321-324 can be in the first copped wave Chopper clock signal is selected between clock signal phase (CLK) and (CLK) of a second chopper clock signal phase.However, It will be understood to those of skill in the art that other configurations can use.

First chopper clock signal controlling switch 321 can be by using the first control bit CTL<1>Cut first and second Selected between ripple clock signal phase and produce the first clock signal clk<1>.In addition, the second chopper clock signal controlling switch 322 can be by using the second control bit CTL<2>Selected between the first and second chopper clock signal phases and produce second Clock signal clk<2>.In addition, the 3rd chopper clock signal controlling switch 323 can be by using the 3rd control bit CTL<3> Select between first and second chopper clock signal phases and produce the 3rd clock signal clk<3>.In addition, the 4th chopper clock Signal-controlled switch 324 can be by using the 4th control bit CTL<4>Selected between the first and second chopper clock signal phases Select and produce the 4th clock signal clk<4>.As illustrated in fig. 12, the first clock signal clk<1>, second clock signal CLK<2>、 3rd clock signal clk<3>With the 4th clock signal clk<4>Available for the drain electrode selecting switch of control first to fourth 131-134 With the switching manipulation of first to fourth grid selecting switch 141-144.

Figure 12 B are the circuit diagrams in a copped wave difference transistor pond 350 according to another embodiment.The copped wave difference of Figure 12 B Transistor pond 350 is similar to the copped wave difference transistor pond 330 of Figure 12 A, and difference is copped wave difference transistor pond 350 First to fourth chopper clock signal controlling switch 321-324 is eliminated, so as to including combinational logic 355.Copped wave differential crystal The additional detail in pipe pond 350 can be similar to those above.

Figure 13 is the flow chart for the method 500 that chopper amplifier is calibrated according to one embodiment.Method 500 can be used for calibrating Such as any chopper amplifier of Figure 1A, 2-7,10 or 11, it will be understood that, process discussed herein can include more Or less operation.

The illustrated method 500 of calibration chopper amplifier starts from block 501, under wherein one or more operating conditions respectively Input to multiple selected transistor configuration observation chopper amplifiers in difference transistor pond biases.Chopper amplifiers it is defeated Entering biasing can be observed in a variety of ways, including, for example, the noninverting and anti-phase input by observing amplifier Difference between end, or its amplified version, when amplifier is connected using negative-feedback.In some implementations, such voltage difference can Observed with the chopper clock operated at steady-state.In another embodiment, the input biasing of Chopper amplifiers It is size variation of the output signal in the component of chopping frequency by observing chopper amplifier.

In some embodiments, the input biasing of Chopper amplifiers is observed in multiple service conditions, including identical At least two or multiple values in performance variable.Chopper amplifiers are observed between multiple values of at least one performance variable Input biasing may be used to determine how input offset voltage changes in opereating specification.For example, the input biasing of amplifier can be with Change with temperature, supply voltage, bias current and input common mode voltage or change.By at two of at least one performance variable Or more value between observe input offset voltage, there is provided the transistor arrangement of relatively small input offset change can be chosen Select.

In the case that although method 500 is illustrated as chopper amplifier including a difference transistor pond, Chopper amplifiers It can include multiple difference transistor ponds, and the amount of bias of Chopper amplifiers can configure for each selection transistor in pond Observed.In some embodiments, the input of Chopper amplifiers is biased for one of multiple difference transistor ponds no The configuration of allomeric pipe is observed, and another difference transistor pond is fixed transistor configuration.Once specific difference transistor Pond has been configured, and this method can repeat, until the pond of all difference transistors is configured.In other embodiment In, when changing the transistor configuration in two or more difference transistor ponds, input biasing is observed.

In subsequent block 502, there is reduction or the minimum difference transistor pond biased in one or more operating conditions Special transistor configuration it is selected.In some configurations, the configuration of selected transistor can correspond in specific work Make transistor configuration of the point with minimum input biasing.However, in other configurations, the configuration of selected transistor can be right Ying Yu and the transistor configuration being associated in the relatively small change for inputting biasing of multiple operating conditions or change.For example, institute The configuration of the transistor of selection can correspond to the structure of transistor, and the input of wherein amplifier is biased with about across temperature becoming Change, supply voltage, the minimal drift of bias current and/or input common mode voltage.In one embodiment, selected transistor Configuration correspond to in the range of operating condition about minimum average B configuration square error transistor configuration.

Method 500 proceeds to block 503, wherein being stored in programmable storage corresponding to the data of selected transistor configuration In device so that chopper amplifier is operated with the configuration of selected transistor.

In some embodiments, the programmable storage be a kind of nonvolatile memory be integrated on chip or with Chopper amplifier is in common encapsulation, and nonvolatile memory is programmed using shop test data.

However, other configurations are possible, such as wherein in Chopper amplifiers power calibration procedure and/or in calibration week Phase is realized.

Figure 14 is the flow chart of the method 510 of calibration chopper amplifier according to another embodiment.This method 510 can be used for Calibrate any chopper amplifier of such as Figure 1A, 2-7,10 or 11.

The illustrated method 510 of calibration chopper amplifier starts from block 511, wherein right respectively under multiple service conditions The input biasing of multiple difference transistor groups observation chopper amplifier in difference transistor pond, the configuration of selected transistor correspond to All transistors less than difference transistor pond configure.

As described above, the input biasing of Chopper amplifiers can be observed in a variety of ways, and It can be observed across multiple operating conditions, including two or more values or scan at least one performance variable.

In the method 510 of diagram, observation input is configured all or fewer than possible transistor for difference transistor pond Biasing.Biased by observing configuration of the input all or fewer than possible transistor, the prover time of Chopper amplifiers can subtract It is few.In one example, determine that the input biasing for including all transistors in the difference transistor pond of 16 transistors can relate to And 16 select 8 or 12870 observations.In one embodiment, for the transistor configuration observation input biasing of multiple Line independents.

This method 510 proceeds to block 512, wherein indicating the shadow of the transistor to input biasing in the pond under multiple operating conditions Loud effect data is determined.It is herein in some configurations, the contribution of each transistor as vector can be solved.This Outside, the contribution of each transistor can be further decomposed as some effects, this can be vector in itself.In some configurations, One or more effects selectively can be minimized or reduced.In one embodiment, effect data includes multiple vectors, including Represent data of multiple transistors for the influence of input offset voltage under each the multiple operating condition.

In subsequent square frame 513, effect data is used to select have biasing reduce or minimum under multiple operating conditions Difference transistor pond particular configuration.The configuration of the selected transistor in difference transistor pond can correspond to the defeated of observation amplifier Enter one of transistor configuration of biasing or the input of amplifier biases unobserved transistor configuration.In some implementations, The linear combination of the various combination for the vector for calculating effect data is provided, and determines the linear combination with lowest mean square length And selection transistor configures.

The method 510 can be used to selection transistor configuration, it is possible to provide across the low biasing of multiple operating points, such as temperature, electricity Source voltage, bias current and/or input common mode voltage.Biased relative to the input of wherein chopper amplifier to difference transistor pond The configuration observation of each transistor scheme, this method 510 can be related to less prover time.

This method 510 proceeds to block 514, wherein being stored in programmable deposit corresponding to the configuration data of selected transistor In reservoir so that chopper amplifier and selected transistor configuration work.

The additional detail of the method 510 of Figure 14 can be similar to the method 500 of previously described Figure 13.

Description and claims above can be with finger element or feature " connection " or " coupling " together.Such as this paper institutes With unless explicitly claimed, otherwise, " connection " means that an element/feature is connected directly or indirectly to another yuan Part/feature, and be not necessarily mechanically.Similarly, unless explicitly claimed, otherwise " couple " and mean an element/feature Another element/feature is coupled directly or indirectly to, and is not necessarily mechanically.Therefore, although shown in the figure is various Elements depicted and the exemplary arrangement of component are illustrated, additional intermediate members, equipment, feature or component can reside in practical embodiments In (assuming that the function of described circuit is unaffected).

Using

Equipment using the above scheme can be implemented into various electronic equipments.The example of electronic equipment can include (but unlimited In) imaging of medical and monitoring, consumption electronic product, consumer, electronic test equipment etc..The example of electronic equipment is also It can include memory chip, memory module optical-fiber network or other communication networks, and the circuit of disc driver circuit.Disappear Expense electronic product may include that (but not limited to) mobile phone, phone, TV, computer monitor, computer, hand-held calculate Machine, personal digital assistant (PDA), micro-wave oven, refrigerator, automobile, stereophonic sound system, cassette tape recorder or player, DVD are broadcast Put device, CD Player, VCR, MP3 player, radio, video camera, camera, digital camera, pocket memory chip, wash Clothing machine, dryer, washer/dryer, duplicator, facsimile machine, scanner, multi-function peripheral device, wrist-watch, clock and watch etc..This Outside, which may include unfinished product.

Although the present invention is described in certain embodiments, it is obvious to those of ordinary skill in the art its Its embodiment, including those do not provide the embodiment of all feature and advantage described in this paper, it is also within the scope of the invention. In addition, above-mentioned various embodiments can be combined to provide further embodiment.In addition, in context in one embodiment The some features shown also may be incorporated into other embodiments.Therefore, the scope of the present invention is solely by reference to the appended claims Limit.

Claims

1. a kind of device for chopper amplifier, including：

Programmable storage, is configured to produce first control signal；With

Chopper amplifier, is configured as amplification differential input voltage signal to produce output signal, wherein the chopper amplifier Including：

First difference transistor pond, including selection circuit and multiple transistors, wherein the selection circuit is configured as being based on institute State first control signal and select the Part I of multiple transistors for being operated in the first transistor group, and wherein institute State selection circuit be configured to select based on the first control signal Part II of multiple transistors for Operated in second transistor group, wherein the selected state of the first control signal corresponds to first control signal at least Second state compares, and has the special transistor of multiple transistors of smaller input biasing in the first and second transistor groups Configuration,

The input offset voltage of wherein described chopper amplifier based on to transistor in the first and second transistors group Selection is varied from.

2. device according to claim 1, wherein, there is no manufacture deviation, in the multiple transistor each It is at least one substantially the same in driving intensity or geometry.

3. device according to claim 1, wherein selection circuit are configured as in the first and second transistors group Select equal number of transistor.

4. device according to claim 1, further includes：

Chopper circuit, including first input end, the second input terminal, input end of clock, the first output terminal and the second output terminal are inputted, Wherein, the input chopper circuit is configured to receive the differential input voltage signal between the first and second input terminals, and base Differential input voltage signal is cut in the chopper clock signal in clock input,

Wherein described difference transistor pond further includes：It is electrically connected to the first grid of the first output terminal of the input chopper circuit Input, and it is electrically connected to the second grid input of the second output terminal of the input chopper circuit.

5. device according to claim 1, wherein, the selection circuit in the first difference transistor pond includes multiple open Close, and wherein it is the multiple switch be configured to provide chopper amplifier input chopping operation or output chopping operation it One.

6. device according to claim 1, wherein, the first difference transistor pond putting along the chopper amplifier Big path is placed, wherein the first difference transistor pond is as the differential input transistor of chopper amplifier, the difference of chopper amplifier Divide the operation of one of difference cascode transistor of load transistor or chopper amplifier.

7. device according to claim 1, further includes the second difference transistor pond, wherein, second difference transistor The transistor configuration in pond is controlled based on the second control signal from programmable storage.

8. device according to claim 7, further includes the 3rd difference transistor pond, wherein, the 3rd difference transistor The transistor configuration in pond is controlled based on the 3rd control signal from programmable storage,

Wherein, the first difference transistor pond operates the differential input transistor as chopper amplifier,

Wherein, the second difference transistor pond operates the differential load transistor as chopper amplifier, and

Wherein, the 3rd difference transistor pond operates the difference cascode transistor as chopper amplifier.

9. device according to claim 1, wherein, the output signal includes single ended output voltage signal.

10. device according to claim 1, further includes Integrated circuit IC, wherein the IC includes the chopper amplifier With the programmable storage.

11. device according to claim 10, wherein, the programmable storage includes being stored in data therein, its Described in data it is associated with the selected state of the first control signal.

12. according to the devices described in claim 11, wherein, it is described compared with the every other state of first control signal The selected state of first control signal corresponds to multiple crystal in the first and second transistor groups with minimum input biasing The special transistor configuration of pipe.

13. device according to claim 1, wherein, the first difference transistor pond is along the chopper amplifier Amplification path is placed, wherein, the first difference transistor pond includes multiple transistor groups, wherein, in the multiple transistor group Each transistor group includes two or more in input transistors, cascode transistors or load transistor.

14. a kind of method for calibrating chopper amplifier, this method include：

Each configured for multiple selected transistors in the first difference transistor pond of chopper amplifier, observes chopper amplification The input offset voltage of device, wherein, the first difference transistor pond includes multiple transistors, and wherein selected transistor is matched somebody with somebody Put including multiple transistors the various combination in the first transistor group and second transistor group, wherein the configuration pair of selected transistor Ying Yuyu at least second transistor configurations compare, and have multiple crystalline substances of smaller input biasing in the first and second transistor groups The special transistor configuration of body pipe；

Transistor configuration is selected based on the observation to the input offset voltage；With

Storage corresponds to the data that the selected transistor of institute configures in programmable storage.

15. according to the method for claim 14, wherein, selected transistor arrangement is included less than described in difference transistor pond Whole transistors in multiple transistors.

16. according to the method for claim 14, further include：

Using the observation to input offset voltage, the effect data of each transistor in difference transistor pond is determined,

Wherein, the configuration of selected transistor be at least partially based on effect data and select.

17. according to the method for claim 16, wherein, the selected transistor configuration of institute is not from the multiple selected crystal Pipe configures.

18. according to the method for claim 16, further include：For each of multiple operating conditions, observe multiple selected The input offset voltage of each of transistor configuration, two of the multiple operating condition including at least one performance variable or Multiple values.

19. according to the method for claim 18, wherein determining that effect data includes：Determine multiple vectors, including representative pair In each of multiple operating conditions, the data of influence of the multiple transistor to input offset voltage.

20. according to the method for claim 19, wherein, the selected selected transistor configuration of institute further comprises：Determine have The linear combination of the vector of lowest mean square length.

21. according to the method for claim 18, wherein, at least one performance variable include temperature, supply voltage, partially Put one or more of electric current or input common mode voltage.

22. according to the method for claim 14, further include：

Stored data are retrieved when IC is turned on；With

Apply the data of storage so that chopper amplifier uses the selected transistor configuration operation of institute.

23. according to the method for claim 14, wherein the first difference transistor pond is along the chopper amplifier Amplification path is placed, wherein, the first difference transistor pond includes multiple transistor groups, wherein, in the multiple transistor group Each transistor group includes two or more in input transistors, cascode transistors or load transistor.