CN104425449A - Through-silicon via and forming method thereof - Google Patents
Through-silicon via and forming method thereof Download PDFInfo
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- CN104425449A CN104425449A CN201310365827.8A CN201310365827A CN104425449A CN 104425449 A CN104425449 A CN 104425449A CN 201310365827 A CN201310365827 A CN 201310365827A CN 104425449 A CN104425449 A CN 104425449A
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Abstract
Provided are a through-silicon via and a forming method thereof. The forming method of the through-silicon via comprises the following steps: a semiconductor substrate is provided, wherein the semiconductor substrate has a through via, and the surface of the through via is coated with an insulating layer; and the through via is filled with silicon germanium. By making use of good filling capacity of silicon germanium and filling the through via with silicon germanium, a formed conductive column has no hole inside. Therefore, a through-silicon via formed by the method has stable performance and high reliability.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly relate to a kind of silicon through hole and forming method thereof.
Background technology
Along with semiconductor technology development, the characteristic size of current semiconductor device has become very little, wish that the quantity increasing semiconductor device in the encapsulating structure of two dimension becomes more and more difficult, therefore three-dimension packaging becomes a kind of method that effectively can improve chip integration.Current three-dimension packaging comprises based on chip-stacked (the Die Stacking) of wire bonding, encapsulation stacking (Package Stacking) and three-dimensional stacked based on silicon through hole (Through Silicon Via, TSV).
Three-dimensional stacked technology based on silicon through hole has following three advantages: (1) High Density Integration; (2) shorten the length of electrical interconnection significantly, thus the problems such as the signal delay appeared in two-dimentional system level chip (SOC) technology can be solved well; (3) utilize silicon through hole technology, the chip (as radio frequency, internal memory, logic, MEMS etc.) with difference in functionality can be integrated and realize the multi-functional of packaged chip.Therefore, the described three-dimensional stacked technology of silicon through hole interconnect structure that utilizes becomes a kind of comparatively popular chip encapsulation technology day by day.
Silicon forming process of through hole generally includes and forms through hole in a silicon substrate, forms insulating barrier in described through-hole surfaces, fills the full surperficial described through hole covered by described insulating barrier to form conductive pole with copper or tungsten.But along with the raising of semiconductor degree of integration, the diameter of described through hole is more and more less, when filling described through hole with copper or tungsten, the conductive pole inside formed there will be hole (void).
As shown in Figure 1, arrange silicon through hole in Semiconductor substrate 11, silicon through hole has conductive pole 12, and conductive pole 12 inside has hole 13.Once hole 13 appears in conductive pole 12 inside, silicon through hole resistance will be caused to increase, electric conductivity declines, and electrical connection properties is bad, even occurs electromigration and stress migration, and then causes silicon through hole reliability decrease.
Although already proposed by silicon forming process of through hole, increase the method for via openings, be beneficial to the filling of copper or tungsten, its effect was barely satisfactory, and increased described via openings the surface area of chip also can be caused to reduce.
For this reason, need a kind of new silicon through hole technology, occur the problem of hole to avoid conductive pole inside in silicon through hole.
Summary of the invention
The problem that the present invention solves is to provide a kind of silicon through hole and forming method thereof, occurs the problem of hole to avoid conductive pole inside in silicon through hole.
For solving the problem, the invention provides a kind of formation method of silicon through hole, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate has through hole, and the surface of described through hole has insulating barrier;
Full SiGe is filled in described through hole.
Optionally, adopt Low Pressure Chemical Vapor Deposition in described through hole, fill full described SiGe.
Optionally, the gas that described Low Pressure Chemical Vapor Deposition adopts comprises silane and germane.
Optionally, the gas that described Low Pressure Chemical Vapor Deposition adopts also comprises at least one of boron chloride, phosphorus pentachloride and arsenic pentachloride.
Optionally, the temperature range that described Low Pressure Chemical Vapor Deposition adopts comprises 370 DEG C ~ 450 DEG C, and pressure range comprises 180mTorr ~ 220mTorr, and reaction time range comprises 125min ~ 375min.
Optionally, fill described full SiGe in described through hole after, chemical-mechanical planarization or pattern-free etching is adopted to carry out planarization to described SiGe.
Optionally, the degree of depth of described through hole is greater than or equal to 30 μm, and the depth-to-width ratio of described through hole is less than or equal to 1:10.
For solving the problem, the present invention also provides a kind of silicon through hole, and comprise the insulating barrier being arranged in Semiconductor substrate and the conductive pole being arranged in described insulating barrier, the material of described conductive pole comprises SiGe.
Optionally, the material of described conductive pole also comprises at least one of boron ion, phosphonium ion and arsenic ion.
Optionally, the conductance scope of described conductive pole comprises 7ohm/sq ~ 13ohm/sq.
Compared with prior art, technical scheme of the present invention has the following advantages:
Use SiGe filling vias to form silicon through hole in the technical program.Have good filling capacity by SiGe, it is almost equal at the filling speed of through hole side and via bottoms, therefore, when adopting SiGe to fill described through hole, there is not hole in the conductive pole inside formed, therefore formed silicon through hole electric performance stablity, reliability is high.
Further, adopt Low Pressure Chemical Vapor Deposition in described through hole, fill full described SiGe, compared to electro-coppering and MOCVD method, saved process costs.
Further, the temperature range that low-pressure chemical vapor deposition adopts comprises 350 DEG C ~ 440 DEG C, reduces energy consumption, saves cost, and can be compatible with polytype subsequent technique.
Accompanying drawing explanation
Fig. 1 is the silicon through hole schematic diagram that prior art is formed;
Fig. 2 to Fig. 5 is the schematic diagram of silicon method for forming via embodiment of the present invention.
Embodiment
Existing method, in the process forming silicon through hole, adopts copper or tungsten to fill usually.
When adopting copper to fill, usually take the mode of electro-coppering.Along with the reduction of entire widths in silicon through hole and the increase of via depth, the floor space of through hole reduces, and the bottom of through hole is sharp concavity, the resistance of via bottoms is caused to increase, even occur that via bottoms resistance is greater than the situation of through-hole side surface resistance, therefore, in electro-coppering process, there will be the situation that through hole side copper deposition velocity is greater than via bottoms copper deposition velocity, cause the copper post inside formed easily to occur hole.
When adopting tungsten to fill, usually the mode of MOCVD is taked, described mode is generally in 60% of through hole side deposition velocity in the deposition velocity of via bottoms, and therefore, described method equally easily causes the tungsten post inside formed easily to occur hole.And MOCVD process costs is high.
For this reason, the present invention, in the process forming silicon through hole, adopts SiGe to fill.SiGe has good filling capacity, and it is almost equal at the filling speed of through hole side and via bottoms, therefore, when adopting SiGe to fill, do not occur hole in formed conductive pole inside, therefore formed silicon through hole electric performance stablity, reliability is high.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 2, Semiconductor substrate 1 is provided; Multiple through hole 2 is formed in described Semiconductor substrate 1; Insulating barrier 3 is formed at the surface of described Semiconductor substrate 1 and the sidewall of through hole 2 and bottom.
In the present embodiment, Semiconductor substrate 1 can be body silicon (Bulk Silicon), SiGe or silicon-on-insulator (Silicon On Insulator, SOI), and can doped with other element.All kinds of active semiconductor device and all kinds of passive semiconductor devices can also be formed in semiconductor substrate 1, and corresponding isolation structure, dielectric layer and conductive interconnecting structure can be formed.
In the present embodiment, the technique forming through hole 2 in semiconductor substrate 1 can be dark rie process, described dark rie process can be the dark reactive ion etching of Bosch (BoschDeep Reactive Ion Etching, Bosch DRIE) technique or low temperature moldeed depth reactive ion etching (Cryogenic Deep Reactive Ion Etching, DRIE).And the method adopting the dark rie process of Bosch to form through hole specifically comprises: the photoresist layer (not shown) of 1 formation patterning first on a semiconductor substrate; Take photoresist layer as mask, alternately introduce etching property gas and protective gas, thus alternately Semiconductor substrate is etched, and the sidewall formed after etching is protected, until form the through hole 2 of preliminary dimension; Remove described photoresist layer.
In the present embodiment, the degree of depth of through hole 2 is greater than or equal to 30 μm, and it is less due to insulating barrier 3 thickness that the depth-to-width ratio (ratio of the degree of depth and width) of through hole 2 is less than or equal to 1:10(, therefore can ignore its impact on through hole 2 size).Further, further, the ratio of the degree of depth and width of choosing through hole 2 is between 1:15 to 1:10.When the degree of depth of through hole 2 and depth-to-width ratio are in above-mentioned scope, if adopt existing method filling vias 2, then usually there is hole in formed conductive pole.
In the present embodiment, the material of insulating barrier 3 can be nitride (such as silicon nitride) or oxide.Insulating barrier 3 can be used for electrically completely cutting off silicon substrate and the follow-up conductive pole be filled in through hole.The method forming insulating barrier 3 can be aumospheric pressure cvd (Atmospheric Pressure Chemical VaporDeposition, APCVD) method, plasma enhanced chemical vapor deposition (Plasma Enhance ChemicalVapor Deposition, PECVD) method or low-pressure chemical vapor deposition (Low Pressure ChemicalVapor Deposition, LPCVD) method.
It should be noted that, though do not show in Fig. 2, but after through hole 2 surface forms insulating barrier 3, can also continue to form diffusion layer (not shown) on through hole 2 surface, now diffusion layer covers insulating barrier 3 surface, and diffusion layer can be used for preventing the follow-up conductive pole be filled in through hole from spreading.
Please refer to Fig. 3, in through hole 2, fill full SiGe 4a.
In the present embodiment, adopt Low Pressure Chemical Vapor Deposition in through hole 2, fill full SiGe 4a.The gas that described Low Pressure Chemical Vapor Deposition adopts can comprise silane and germane, and described silane can be monosilane (SiH
4) and disilane (Si
2h
6) at least one, described germane can be first germane (GeH
4).
In the present embodiment, the gas that described Low Pressure Chemical Vapor Deposition adopts can also comprise boron chloride (BCl
3), phosphorus pentachloride (PCl
5) or arsenic pentachloride (AsCl
5) etc. other gas.BCl is introduced in deposition process
3, PCl
5and AsCl
5deng gas, thus introduce the foreign ions such as boron ion, phosphonium ion or arsenic ion in the SiGe 4a formed in deposition, reduce the resistivity of SiGe 4a, make SiGe 4a reach electric conductivity needed for silicon through hole.
The present embodiment specifically adopts SiH
4, GeH
4and BCl
3react, to form the SiGe 4a with boron ion.Wherein SiH
4range of flow control at 15sccm ~ 45sccm, GeH
4range of flow control at 5sccm ~ 15sccm, BCl
3range of flow control at 25sccm ~ 75sccm.Due to BCl
3boiling point (12.5 DEG C) low, therefore adopt BCl
3can energy consumption be reduced and save cost.In the low-pressure chemical vapor deposition process that the present embodiment is concrete, comprise following five processes:
Semiconductor substrate 1 enters the process of reaction chamber: send in reaction chamber by Semiconductor substrate 1, and reaction chamber temperature controls at 350 DEG C ~ 450 DEG C, and the time controling in this stage at 10min ~ 20min, and passes into the nitrogen of 5L ~ 20L.
Reaction chamber temperature stabilization process: control temperature remains on 370 DEG C ~ 450 DEG C, can need to adjust concrete temperature value in this temperature range according to technique, such as 370 DEG C, 380 DEG C, 400 DEG C, 410 DEG C, 420 DEG C, 430 DEG C or 450 DEG C, this phases-time controls at 5 ~ 10min, and pass into 5L ~ 10L nitrogen, adjust air pressure to the 0 ~ 1000pa in reaction chamber simultaneously.
Isothermal reaction process: make temperature constant at 370 DEG C ~ 450 DEG C, controls air pressure at 180mTorr ~ 220mTorr, passes into reacting gas and react.In the present embodiment, SiH
4concentration range can be 40% ~ 60%, GeH
4concentration range can be 20% ~ 40%, BCl
3concentration range can be 5% ~ 30%, the reaction time controls at 200min ~ 300min, can according to the adjusted size of the through hole 2 corresponding reaction time.In course of reaction, because SiGe has excellent filling capacity, it is substantially equal in the speed of growth of through hole 2 sidewall and bottom, and therefore in whole filling process, SiGe inside does not occur hole.
Reaction stopped process: continue control temperature at 350 DEG C ~ 450 DEG C, pass into 5L ~ 20L nitrogen at 10min ~ 20min, controls air pressure at 0 ~ 1000pa.
Semiconductor substrate 1 exits the process of reaction chamber: continue control temperature at 350 DEG C ~ 450 DEG C, time 10 ~ 20min, nitrogen 5L ~ 20L, controls air pressure and gets back to normal pressure.
From the description of above process, in the present embodiment, whole technical process temperature range controls at 350 DEG C ~ 450 DEG C all the time, both energy consumption was reduced, do not affect again other structure in Semiconductor substrate 1, and because the temperature of depositing operation is low, the formation method of silicon through hole that therefore the present embodiment provides can be compatible with polytype subsequent technique.
The surface resistivity scope of the SiGe 4a formed by above-mentioned technique comprises 7ohm/sq ~ 13ohm/sq, and for other technique, the present embodiment obtains the SiGe 4a of low resistivity with lower doping content.
Please refer to Fig. 4, adopting chemical-mechanical planarization to carry out planarization to exposing insulating barrier 3 to the 4a of SiGe shown in Fig. 3, forming conductive pole 4b.Adopt chemical-mechanical planarization that the surface flatness of conductive pole 4b can be made to reach higher level, improve the reliability of silicon through hole further.
Except adopting the mode of chemical-mechanical planarization, pattern-free also can be adopted to etch (blanket etch) planarization is carried out to the 4a of SiGe shown in Fig. 3, form conductive pole 4c, as shown in Figure 5.
The present embodiment adopts Low Pressure Chemical Vapor Deposition to form SiGe 4a with filling vias 2, in the filling process, SiGe 4a is substantially equal in the speed of growth of through hole 2 sidewall and bottom, therefore, can prevent formed SiGe 4a inside from there is hole, therefore the final silicon through hole electric property formed is excellent, and reliability is high.And the process that the present embodiment adopts is for copper plating process and MOCVD technique, cost reduces.
The embodiment of the present invention additionally provides a kind of silicon through hole, and described silicon through hole comprises the insulating barrier that is arranged in Semiconductor substrate and is arranged in the conductive pole of described insulating barrier, and the material of described conductive pole comprises SiGe, and what mainly comprise is SiGe.Described conductive pole also comprises the foreign ions such as boron ion, and boron ion can improve the electric conductivity of described conductive pole.The surface conductivity scope of described conductive pole comprises 7ohm/sq ~ 13ohm/sq.
It should be noted that, in other embodiments of the invention, described conductive pole can include other foreign ion such as phosphonium ion or arsenic ion.And described foreign ion can take the mode of doping or ion implantation to mix in described conductive pole.
In the silicon through hole that the embodiment of the present invention provides, because the material of conductive pole comprises SiGe, SiGe has good filling capacity, and therefore described conductive pole inside does not occur hole, and make described silicon through hole electric performance stablity, reliability is high.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for silicon through hole, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate has through hole, and the surface of described through hole has insulating barrier;
Full SiGe is filled in described through hole.
2. the formation method of silicon through hole as claimed in claim 1, is characterized in that, adopts Low Pressure Chemical Vapor Deposition in described through hole, fill full described SiGe.
3. the formation method of silicon through hole as claimed in claim 2, it is characterized in that, the gas that described Low Pressure Chemical Vapor Deposition adopts comprises silane and germane.
4. the formation method of silicon through hole as claimed in claim 3, it is characterized in that, the gas that described Low Pressure Chemical Vapor Deposition adopts also comprises at least one of boron chloride, phosphorus pentachloride and arsenic pentachloride.
5. the formation method of silicon through hole as claimed in claim 2, it is characterized in that, the temperature range that described Low Pressure Chemical Vapor Deposition adopts comprises 370 DEG C ~ 450 DEG C, and pressure range comprises 180mTorr ~ 220mTorr, and reaction time range comprises 125min ~ 375min.
6. the formation method of silicon through hole as claimed in claim 1, is characterized in that, after filling described full SiGe, adopts chemical-mechanical planarization or pattern-free etching to carry out planarization to described SiGe in described through hole.
7. the formation method of silicon through hole as claimed in claim 1, it is characterized in that, the degree of depth of described through hole is greater than or equal to 30 μm, and the depth-to-width ratio of described through hole is less than or equal to 1:10.
8. a silicon through hole, is characterized in that, comprise the insulating barrier being arranged in Semiconductor substrate and the conductive pole being arranged in described insulating barrier, the material of described conductive pole comprises SiGe.
9. silicon through hole as claimed in claim 8, it is characterized in that, the material of described conductive pole also comprises at least one of boron ion, phosphonium ion and arsenic ion.
10. silicon through hole as claimed in claim 8, it is characterized in that, the conductance scope of described conductive pole comprises 7ohm/sq ~ 13ohm/sq.
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| CN201310365827.8A CN104425449B (en) | 2013-08-20 | 2013-08-20 | Silicon hole and forming method thereof |
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| CN201310365827.8A CN104425449B (en) | 2013-08-20 | 2013-08-20 | Silicon hole and forming method thereof |
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| CN104425449B CN104425449B (en) | 2018-02-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105870054A (en) * | 2016-06-06 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | Through-silicon-hole structure and formation method thereof |
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| US20110212600A1 (en) * | 2009-12-11 | 2011-09-01 | Tsinghua University | Method for forming channel layer with high ge content on substrate |
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Effective date of registration: 20180531 Address after: No. 18 Zhangjiang Road, Pudong New Area, Shanghai Co-patentee after: Core integrated circuit (Ningbo) Co., Ltd. Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: No. 18 Zhangjiang Road, Pudong New Area, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |