CN104425274A - Preparation method of DMOS (Double diffusion Metal-Oxide-Semiconductor) transistor and DMOS transistor - Google Patents
Preparation method of DMOS (Double diffusion Metal-Oxide-Semiconductor) transistor and DMOS transistor Download PDFInfo
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- CN104425274A CN104425274A CN201310395493.9A CN201310395493A CN104425274A CN 104425274 A CN104425274 A CN 104425274A CN 201310395493 A CN201310395493 A CN 201310395493A CN 104425274 A CN104425274 A CN 104425274A
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- silicon chip
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- dmos transistor
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000009792 diffusion process Methods 0.000 title abstract 2
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 68
- 239000010703 silicon Substances 0.000 claims abstract description 65
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000002253 acid Substances 0.000 claims description 13
- 239000000243 solution Substances 0.000 claims description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 4
- 229910017604 nitric acid Inorganic materials 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000000227 grinding Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000005498 polishing Methods 0.000 description 21
- 238000010586 diagram Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 206010061245 Internal injury Diseases 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
Abstract
The invention provides a preparation method of a DMOS (Double diffusion Metal-Oxide-Semiconductor) transistor and the DMOS transistor, and relates to the technical field of manufacturing of semiconductors. The preparation method comprises the following steps: providing a silicon wafer and forming a grid insulating layer and a grid electrode on the silicon wafer; depositing a first metal layer on the front surface of the silicon wafer and etching the first metal layer to form a source electrode; thinning the back surface of the semiconductor silicon wafer once by a grinding wheel with the fineness being less than 600 meshes for the first time; depositing a second metal layer on the back surface of the silicon wafer to be used as a drain electrode so as to form the DMOS transistor. According to the preparation method, a process of 325 meshes and 600 meshes in an existing thinning technology is changed and the roughness of the silicon surface of the back surface is increased, so that the metal on the back surface and the silicon surface of the back surface are fused better; the resistance between the source electrode and the drain electrode is smaller and the Vfsd is smaller, so that the problem that the sector of the Vfsd becomes invalid after a DMOS product is thinned is solved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly the preparation method of DMOS transistor and DMOS transistor.
Background technology
Discrete type Metal-oxide-silicon product and DMOS product (abbreviation of Discrete Metal-Oxide-Silicon) grinding back surface, silicon wafer thickness is reduced to about 300 μm from 625 μm, the resistance between DMOS product source and drain can be reduced, increase the toughness of chip, reduce chip volume, be conducive to chip cooling.Lapping mode has cut-in type to ease up into formula two kinds, as shown in Figure 1, be that cut-in type grinds thinning machine, abrasive wheel 1 and carry the pallet 2 of silicon chip different rotating speeds is relative in the opposite direction and rotate, simultaneous grinding wheel declines by certain speed thus reaches thinning effect, and the lines after thinning is like this fan-shaped distribution.
As shown in Figure 2, be diode forward conduction voltage drop Vfsd(Forward Voltage of diodebetween S, D between source and drain) method of measurement: GS short circuit, S ground connection, SD biasing Vsd, measures electric current I sd between SD.Increase Vsd, the Vsd measured value when Isd reaches set point is Vfsd; Vgs=0V, Isd=set point.As shown in Figure 3, be Vfsd measurement result.
Drain after the back face metalization of DMOS product (Drain), after front-side metallization, do source electrode (Source), the conduction voltage drop that the resistance between source and leakage directly determines source (S) and leaks between (D).V=I*R(Isd is certain), as shown in Figure 4, thinning to silicon chip 5, the metal layer on back 3 on silicon chip surface polishing scratch 4 is as D pole.Thinning polishing scratch weight relationship is to drain resistance, and when polishing scratch is coarse, greatly, merge between Ti and Si, between S, D, resistance is little for back metal and silicon chip surface contact area, and Vfsd is also little in Isd mono-timing; Otherwise, when thinning polishing scratch is thin, back metal and silicon chip surface contact area little, merge bad between Ti and Si, between S, D, resistance is comparatively large, Isd mono-timing Vfsd more greatly, the easy super upper limit.
Be as shown in Figure 5 thinning after back side polishing scratch figure, silicon chip surface polishing scratch 6 after thinning by grinder is in fan-shaped distribution, the Vfsd regulating scope of some DMOS product is very narrow (0 ~ 1.0V), be easy to that Vfsd occurs surpass the upper limit and lost efficacy in fan-shaped distribution, as shown in Figure 6, the fan-shaped failed areas of Vfsd is 7.Existing thinning technique is the thinning major part of abrasive wheel first adopting polishing scratch coarse, again with the thinning 20um of the abrasive wheel that polishing scratch is thin to required thickness, like this because the polishing scratch at the back side is thinner, the contact area of back metal and back side silicon chip is little, contact resistance is large, cause Vfsd greatly, the easy super upper limit, cause the fan-shaped inefficacy of Vfsd.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of preparation method and DMOS transistor of DMOS transistor, solves the problem of the fan-shaped inefficacy of the thinning rear Vfsd of DMOS product.
For solving the problems of the technologies described above, The embodiment provides a kind of preparation method of DMOS transistor, comprising:
One silicon chip is provided;
Described silicon chip is formed gate insulation layer and grid;
At the first metal layer that described front side of silicon wafer deposition source electrode is used;
Etching is carried out to described the first metal layer and forms source electrode;
Being less than 600 object abrasive wheels by fineness carries out once thinning to the semi-conductor silicon chip back side;
Drain at described silicon chip back side depositing second metal layer, form DMOS transistor.
Wherein, be less than after 600 object abrasive wheels carry out once thinning step to the semi-conductor silicon chip back side by fineness and also comprise:
With acid-containing solution, the silicon chip back side after thinning is corroded.
Wherein, with acid-containing solution, the step that the silicon chip back side after thinning corrodes is specially:
With acid-containing solution, 20 seconds are corroded to the silicon chip back side after thinning.
Wherein, described acid-containing solution is: the mixed solution of hydrofluoric acid and nitric acid.
Wherein, be less than 600 object abrasive wheels by fineness to carry out once thinning step to the semi-conductor silicon chip back side and be specially:
Being less than 600 object abrasive wheels by fineness carries out once thinning to the semi-conductor silicon chip back side, until wafer thinning is to the one-tenth-value thickness 1/10 of setting.
Wherein, be specially in the step of described silicon chip back side drain the second metal level used:
Drain at described silicon chip back side evaporation titanium, nickel or silver.
Wherein, described abrasive wheel is fineness is 325 object abrasive wheels.
For solving the problems of the technologies described above, present invention also offers a kind of DMOS transistor, described DMOS transistor is prepared by method described above.
The beneficial effect of technique scheme of the present invention is as follows:
In such scheme, thinning silicon chip back side is carried out by the abrasive wheel (namely fineness is 325 object abrasive wheels) only adopting polishing scratch thick, not only increase speed, too increase the roughness of surperficial polishing scratch, resistance between source and drain is reduced, Vfsd reduces, and greatly reduces the probability of the fan-shaped inefficacy of Vfsd, improves thinning success rate.
Accompanying drawing explanation
Fig. 1 is the operating diagram that cut-in type grinds thinning machine;
Fig. 2 is the method for measurement schematic diagram of diode forward conduction voltage drop Vfsd between source and drain;
Fig. 3 is Vfsd measurement result;
Fig. 4 is silicon chip surface polishing scratch schematic diagram;
Fig. 5 is thinning rear back side polishing scratch figure;
Fig. 6 is the fan-shaped inefficacy figure of Vfsd;
Fig. 7 is the thinning rear polishing scratch schematic diagram of prior art;
Fig. 8 is the thinning rear polishing scratch schematic diagrames of embodiments of the invention.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
The present invention is directed to the problem of the fan-shaped inefficacy of the thinning rear Vfsd of existing DMOS product, a kind of preparation method and DMOS transistor of DMOS transistor are provided.
As shown in Figure 8, the preparation method of a kind of DMOS transistor of embodiments of the invention, comprising:
Step 81, provides a silicon chip;
Step 82, described silicon chip is formed gate insulation layer and grid;
Step 83, at the first metal layer that described front side of silicon wafer deposition source electrode is used; Wherein the first metal is: Al or Si or Cu;
Step 84, carries out etching to described the first metal layer and forms source electrode;
Step 85, is less than 600 object abrasive wheels by fineness and carries out once thinning to the semi-conductor silicon chip back side;
Step 86, drains at described silicon chip back side depositing second metal layer, forms DMOS transistor.
Order is the unit characterizing finish fineness, being less than 600 order abrasive wheel replacement fineness by fineness, to be that 325 orders add 600 order abrasive wheels thinning, not only improves speed, also increase the roughness of surperficial polishing scratch, compared with Fig. 7 prior art polishing scratch 8, in Fig. 8, the fineness of polishing scratch 9 of the present invention is obviously coarse, and like this, metal and silicon chip 5 contact surface area of metal layer on back 3 are large, fusion between metal and silicon well, resistance between source electrode and drain electrode is less, and Vfsd is also little, is not easy fan-shaped inefficacy.
But polishing scratch is thick, stress is comparatively large, just needs to increase back side silicon etching time apparent to improve, eliminates stress, so the preparation method of a kind of DMOS of embodiments of the invention, be less than after 600 object abrasive wheels carry out once thinning step to the semi-conductor silicon chip back side by fineness and also comprise:
With acid-containing solution, the silicon chip back side after thinning is corroded.
By the corrosion of acid solution, eliminate with fineness be less than 600 object abrasive wheels thinning after the more surface silicon bits that stay and stress, release internal injury.
Wherein, with acid-containing solution, the step that the silicon chip back side after thinning corrodes is specially:
With acid-containing solution, 20 seconds are corroded to the silicon chip back side after thinning.
Due to be less than 600 order abrasive wheels thinning after, polishing scratch is thick, and stress is large, so increase back side silicon etching time by 20 seconds, with reach improve apparent, the object eliminated stress.
Wherein, described acid-containing solution is: the mixed solution of hydrofluoric acid and nitric acid.
Namely carry out chemical corrosion with hydrofluoric acid and nitric acid mixed liquor to silicon chip grinding face, reach the object removing surface silicon bits, release internal injury and stress, reaction equation is as follows:
Si+4HNO
3=SiO
2+2H
2O+4NO
2
SiO
2+6HF=H
2SiF
6+2H
2O
Wherein, be less than 600 object abrasive wheels by fineness to carry out once thinning step to silicon chip back side and be:
Being less than 600 object abrasive wheels by fineness carries out once thinning to the semi-conductor silicon chip back side, until wafer thinning is to the one-tenth-value thickness 1/10 of setting.
Decreasing fineness is the use of 600 object abrasive wheels, is less than 600 object abrasive wheels directly by the one-tenth-value thickness 1/10 of wafer thinning to setting, not only improves speed, also increase the roughness of surperficial polishing scratch by fineness.
In actual applications, using back metal as drain electrode, so, in embodiments of the invention, be specially in the step of described silicon chip back side drain the second metal level used:
Drain at described silicon chip back side evaporation titanium, nickel or silver.
In the above-described embodiments, select abrasive wheel fineness to be less than 600 object abrasive wheels, wherein, described abrasive wheel is fineness is 325 object abrasive wheels.
By above-described embodiment, solve the fan-shaped Problem of Failure of the thinning rear Vfsd of DMOS product, the product that therefore decreasing lost efficacy causes is done over again and is scrapped.
In order to realize above-mentioned purpose better, embodiments of the invention also provide a kind of DMOS transistor, and described DMOS transistor is prepared by method as above, and the beneficial effect of the embodiment of described method is all applicable to this DMOS transistor.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (8)
1. a preparation method for DMOS transistor, is characterized in that, comprising:
One silicon chip is provided;
Described silicon chip is formed gate insulation layer and grid;
At the first metal layer that described front side of silicon wafer deposition source electrode is used;
Etching is carried out to described the first metal layer and forms source electrode;
Being less than 600 object abrasive wheels by fineness carries out once thinning to the semi-conductor silicon chip back side;
Drain at described silicon chip back side depositing second metal layer, form DMOS transistor.
2. the preparation method of DMOS transistor according to claim 1, is characterized in that, is less than after 600 object abrasive wheels carry out once thinning step to the semi-conductor silicon chip back side also comprises by fineness:
With acid-containing solution, the silicon chip back side after thinning is corroded.
3. the preparation method of DMOS transistor according to claim 2, is characterized in that, is specially the step that the silicon chip back side after thinning corrodes with acid-containing solution:
With acid-containing solution, 20 seconds are corroded to the silicon chip back side after thinning.
4. the preparation method of the DMOS transistor according to Claims 2 or 3, is characterized in that, described acid-containing solution is: the mixed solution of hydrofluoric acid and nitric acid.
5. the preparation method of DMOS transistor according to claim 1, is characterized in that, is less than 600 object abrasive wheels carries out once thinning step to the semi-conductor silicon chip back side and be specially by fineness:
Being less than 600 object abrasive wheels by fineness carries out once thinning to the semi-conductor silicon chip back side, until wafer thinning is to the one-tenth-value thickness 1/10 of setting.
6. the preparation method of DMOS transistor according to claim 1, is characterized in that, is specially in the step of described silicon chip back side drain the second metal level used:
Drain at described silicon chip back side evaporation titanium, nickel or silver.
7. the preparation method of DMOS transistor according to claim 1, is characterized in that, described abrasive wheel is fineness is 325 object abrasive wheels.
8. a DMOS transistor, is characterized in that, described DMOS transistor is prepared by the method as described in any one of claim 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310395493.9A CN104425274A (en) | 2013-09-03 | 2013-09-03 | Preparation method of DMOS (Double diffusion Metal-Oxide-Semiconductor) transistor and DMOS transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310395493.9A CN104425274A (en) | 2013-09-03 | 2013-09-03 | Preparation method of DMOS (Double diffusion Metal-Oxide-Semiconductor) transistor and DMOS transistor |
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| CN104425274A true CN104425274A (en) | 2015-03-18 |
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| CN201310395493.9A Pending CN104425274A (en) | 2013-09-03 | 2013-09-03 | Preparation method of DMOS (Double diffusion Metal-Oxide-Semiconductor) transistor and DMOS transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021097756A1 (en) * | 2019-11-21 | 2021-05-27 | Texas Instruments Incorporated | Packaged electronic device with low resistance backside contact |
Citations (5)
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|---|---|---|---|---|
| US4144099A (en) * | 1977-10-31 | 1979-03-13 | International Business Machines Corporation | High performance silicon wafer and fabrication process |
| CN100521094C (en) * | 2005-09-29 | 2009-07-29 | 硅电子股份公司 | Unpolished semiconductor wafer and manufacture method thereof |
| CN101498055A (en) * | 2009-01-19 | 2009-08-05 | 郜勇军 | Polishing treatment method for solar grade monocrystal silicon bar |
| CN101842878A (en) * | 2007-10-24 | 2010-09-22 | 松下电器产业株式会社 | Semiconductor device and method for manufacturing the same |
| CN102760754A (en) * | 2012-07-31 | 2012-10-31 | 杭州士兰集成电路有限公司 | Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof |
-
2013
- 2013-09-03 CN CN201310395493.9A patent/CN104425274A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4144099A (en) * | 1977-10-31 | 1979-03-13 | International Business Machines Corporation | High performance silicon wafer and fabrication process |
| CN100521094C (en) * | 2005-09-29 | 2009-07-29 | 硅电子股份公司 | Unpolished semiconductor wafer and manufacture method thereof |
| CN101842878A (en) * | 2007-10-24 | 2010-09-22 | 松下电器产业株式会社 | Semiconductor device and method for manufacturing the same |
| CN101498055A (en) * | 2009-01-19 | 2009-08-05 | 郜勇军 | Polishing treatment method for solar grade monocrystal silicon bar |
| CN102760754A (en) * | 2012-07-31 | 2012-10-31 | 杭州士兰集成电路有限公司 | Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021097756A1 (en) * | 2019-11-21 | 2021-05-27 | Texas Instruments Incorporated | Packaged electronic device with low resistance backside contact |
| US11404385B2 (en) | 2019-11-21 | 2022-08-02 | Texas Instruments Incorporated | Packaged electronic device with low resistance roughened backside contact |
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