CN104409584A - LED structure and manufacturing method thereof - Google Patents
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- CN104409584A CN104409584A CN201410709185.3A CN201410709185A CN104409584A CN 104409584 A CN104409584 A CN 104409584A CN 201410709185 A CN201410709185 A CN 201410709185A CN 104409584 A CN104409584 A CN 104409584A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 189
- 238000000034 method Methods 0.000 claims abstract description 65
- 238000005516 engineering process Methods 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 229910052594 sapphire Inorganic materials 0.000 claims description 38
- 239000010980 sapphire Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 38
- 150000002500 ions Chemical class 0.000 claims description 37
- 238000002161 passivation Methods 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 13
- 238000000926 separation method Methods 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 7
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 7
- -1 oxonium ion Chemical class 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 230000001404 mediated effect Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005282 brightening Methods 0.000 description 1
- 230000002493 climbing effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
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Abstract
The invention provides an LED structure and a manufacturing method thereof. By an ion implantation technology, a plurality of high-resistance state ion implantation layers are formed in a preset area of a light-emitting semiconductor layer; the high-resistance state ion implantation layers divide the light-emitting semiconductor layer into a plurality of insulated and separated independent light-emitting semiconductor layers; at a follow-up chip manufacturing end, isolating grooves are not manufactured by a photoetching process and the isolating grooves are not filled with insulating materials, which are rightly expensive process steps of the chip manufacturing end and technical bottlenecks for improvement on the reliability and the qualified rate; according to the LED structure and the manufacturing method thereof, the LED brightness, the reliability and the qualified rate of LED chips can be improved and the production cost can be reduced.
Description
Technical field
The invention belongs to semiconductor optoelectronic chip manufacturing field, particularly relate to a kind of LED structure and preparation method thereof.
Background technology
Since early 1990s commercialization, through the development of twenties years, GaN base LED has been widely used in the fields such as indoor outer display screen, Projection Display lighting source, backlight, view brightening illumination, advertisement, traffic instruction, and is described as 21st century the most competitive solid light source of new generation.But for light emitting semiconductor device LED, conventional light source be replaced, enter high-end lighting field, must consider three factors: one is the lifting of luminosity, two is liftings of reliability, and three is reductions of production cost.
In recent years, the various technology for improving LED luminosity is arisen at the historic moment, and such as graphical sapphire substrate technology, sidewall coarsening technique, DBR technology, optimizes electrode structure, in Sapphire Substrate or nesa coating, makes 2 D photon crystal etc.Wherein graphical sapphire substrate technology most effect, between 2010 to 2012, the dry method graphical sapphire substrate of cone structure that front and back occur and the wet method pattern Sapphire Substrate of Pyramid instead of the main flow Sapphire Substrate that the smooth Sapphire Substrate in surface becomes LED chip completely, make the crystal structure of LED and luminosity be obtained for revolutionary raising.But the main flow Sapphire Substrate that patterned Sapphire Substrate replaces the smooth Sapphire Substrate in surface to become LED chip adds the production cost of LED undoubtedly, although the cost increased can slowly reduce along with the raising of graphical sapphire substrate manufacturing technology level, cannot eliminate completely.
Along with the high speed development of semiconductor integration technology, a kind ofly be called that the LED structure of high-voltage chip is arisen at the historic moment, the LED of this kind of structure is generally after light emitting semiconductor layer is formed, in described light emitting semiconductor layer, isolation channel is formed by lithographic etch process, fill insulant in isolation channel again, finally makes electrode and forms cascaded structure in the light emitting semiconductor layer of each insulated separation; Although this structure can improve the luminosity of LED to a certain extent, this kind of structure also can reduce the reliability of LED, and its space of improving LED luminosity is also limited simultaneously; This is because the thickness of light emitting semiconductor layer will more than 6 μm, if utilize photoresist to make mask, light emitting semiconductor layer forms isolation channel, then the thickness of photoresist generally will more than 10 μm, the photoresist of this kind of thickness will certainly affect lithographic line width, and then increase the width of isolation channel, reduce the light-emitting area of LED; If utilize silicon dioxide to make mask, light emitting semiconductor layer forms isolation channel, then due to the limitation of Selection radio, and then the steep side walls of isolation channel can be caused, this can affect the climbing effect of follow-up series connection electrode, and then reduces yield and the reliability of LED chip; Moreover, due to the limitation of existing etching technics uniformity, always have subregion to there is semi-conducting material residual phenomena in the isolation channel of formation, this kind of phenomenon can cause series chip to lose efficacy because of short circuit; Moreover, no matter adopt which kind of technique to form isolation channel, all can increase a part of production cost on the basis of existing LED production technology.
In a word, the limited space of existing LED production Technology or raising LED luminosity, or reduce the good reliability yield of LED chip, or improve the production cost of LED, both or three have it concurrently, are unfavorable for that LED substitutes conventional light source and enters lighting field.
Summary of the invention
The object of the present invention is to provide a kind of LED of raising luminosity, LED chip reliability and LED chip yield and can LED structure that its production cost be reduced and preparation method thereof simultaneously.
In order to solve the problem, the invention provides a kind of LED structure manufacture method, comprising:
One Sapphire Substrate is provided;
Described Sapphire Substrate forms light emitting semiconductor layer, and form some high-impedance state ion implanted layers by ion implantation technology in the precalculated position of light emitting semiconductor layer, light emitting semiconductor layer is divided into the independent light emitting semiconductor layer of some insulated separation by described some high-impedance state ion implanted layers, and each independent light emitting semiconductor layer includes the n type semiconductor layer, active layer and the p type semiconductor layer that stack gradually;
In each independent light emitting semiconductor layer, form a groove, described groove runs through described p type semiconductor layer, active layer and at least part of n type semiconductor layer, and a sidewall of each high-impedance state ion implanted layer is come out by a groove;
The p type semiconductor layer of each independent light emitting semiconductor layer forms the first electrode, in the groove of each independent light emitting semiconductor layer, form the second electrode, and the second electrode of independent light emitting semiconductor layer adjacent for part and the electrical connection of the first electrode are formed cascaded structure;
The surface of all exposures of described light emitting semiconductor layer is formed passivation protection layer, and described passivation protection layer has the first electrode in the independent light emitting semiconductor layer headed by the described cascaded structure of exposure and the fairlead for the second electrode in the independent light emitting semiconductor layer of tail.
Optionally, in described LED structure manufacture method, after forming light emitting semiconductor layer by MOCVD technique or molecular beam epitaxy technique in described Sapphire Substrate, described light emitting semiconductor layer forms mask layer, and blocks with described mask layer and carry out ion implantation to form some high-impedance state ion implanted layers in the precalculated position of described light emitting semiconductor layer.
Optionally, in described LED structure manufacture method, formed in the process of light emitting semiconductor layer by MOCVD technique or molecular beam epitaxy technique in described Sapphire Substrate, form some high-impedance state ion implanted layers by ion implantation technique in the precalculated position of described light emitting semiconductor layer simultaneously.
Optionally, in described LED structure manufacture method, in described light emitting semiconductor layer, inject oxonium ion form described some high-impedance state ion implanted layers.
Optionally, in described LED structure manufacture method, form a groove in each independent light emitting semiconductor layer after, the subregion of described p type semiconductor layer forms barrier layer.
Optionally, in described LED structure manufacture method, after the subregion of described p type semiconductor layer forms barrier layer, described p type semiconductor layer and barrier layer form contact layer.
Optionally, in described LED structure manufacture method, the material on described barrier layer is silicon dioxide, and the material of described contact layer is ITO.
Optionally, in described LED structure manufacture method, on the surface of all exposures of described independent light emitting semiconductor layer, form passivation protection layer by pecvd process.Formed in the process of described passivation protection layer by pecvd process, described Sapphire Substrate while revolving round the sun under the drive of carrier described Sapphire Substrate also carry out rotation.
The present invention also provides a kind of LED structure, comprising:
Sapphire Substrate;
Be formed at the light emitting semiconductor layer in described Sapphire Substrate;
Be formed at the some high-impedance state ion implanted layers in described light emitting semiconductor layer, described light emitting semiconductor layer is divided into the independent light emitting semiconductor layer of some insulated separation by described some high-impedance state ion implanted layers, and each independent light emitting semiconductor layer includes the n type semiconductor layer, active layer and the p type semiconductor layer that stack gradually;
Some grooves running through described p type semiconductor layer, active layer and at least part of n type semiconductor layer, each described groove exposes a sidewall of a high-impedance state ion implanted layer;
The second electrode being formed at the first electrode on the p type semiconductor layer of described each independent light emitting semiconductor layer and being formed in the groove of described each independent light emitting semiconductor layer, the second electrode in the independent light emitting semiconductor layer that part is adjacent and the electrical connection of the first electrode, form cascaded structure; And
Be formed at the passivation protection layer on the surface of all exposures of described light emitting semiconductor layer, described passivation protection layer has the first electrode in the independent light emitting semiconductor layer headed by the described cascaded structure of exposure and the fairlead for the second electrode in the independent light emitting semiconductor layer of tail.
Optionally, in described LED structure, also comprise the barrier layer on the subregion being formed at described p type semiconductor layer.
Optionally, in described LED structure, also comprise the contact layer be formed on described p type semiconductor layer and barrier layer.
Optionally, in described LED structure, the material on described barrier layer is silicon dioxide, and the material of described contact layer is ITO.
LED structure provided by the invention and preparation method thereof has following beneficial effect:
1, LED structure manufacture method of the present invention utilizes ion implantation technique, in the process that light emitting semiconductor layer is formed or after its formation, form high-impedance state ion implanted layer over a predetermined area, light emitting semiconductor layer is divided into the independent light emitting semiconductor layer of some insulated separation by described some high-impedance state ion implanted layers, follow-up chip manufacturing end is without the need to carrying out the making of isolation channel again by lithographic etch process, more need not use filling insulating material isolation channel again, and the processing step of these chip manufacturing end cost intensive just, also be that it improves the technical bottleneck of reliability and yield, so LED structure provided by the invention and preparation method thereof solves the technical barrier of chip manufacturing end,
2, the first electrode and second electrode of each independent emitting semiconductor can form metal according to demand and be connected while independent emitting semiconductor first electrode of formation with the second electrode, namely the cascaded structure of any number is formed, the light emitting semiconductor layer forming cascaded structure, without the need to testing separately, has saved testing cost again; Without the need to cutting separately again, save cutting cost; Also without the need to encapsulating separately, packaging cost has been saved again; So LED structure provided by the invention and preparation method thereof is by low testing cost, the cutting cost of chip manufacturing end, also reduce the cost of downstream encapsulation simultaneously;
3, because each light emitting semiconductor layer described while formation electrode, can form cascaded structure, so LED structure provided by the present invention can at larger operating at voltages;
4, because cascaded structure synchronously can be formed with electrode, the tube core mediated can not by the constraint of lithographic line width, the constraint that can not require by routing, the area of luminous zone occupied by it can be less, so this further increases again the luminosity of LED.
Accompanying drawing explanation
With reference to accompanying drawing, according to detailed description below, clearly the present invention can be understood.For the sake of clarity, in figure, the relative thickness of each layer and the relative size of given zone are not drawn in proportion.In the accompanying drawings:
Fig. 1-7 is the structural representations in the LED structure manufacturing process of one embodiment of the invention;
The rotation schematic diagram of Sapphire Substrate when Fig. 8 is one embodiment of the invention formation passivation protection layer.
Fig. 9 is the schematic flow sheet of the LED structure manufacture method of one embodiment of the invention.
Embodiment
Various exemplary embodiment of the present invention is described in detail now with reference to accompanying drawing.
As shown in Figure 9, LED structure manufacture method of the present invention, comprises the steps:
S1 a: Sapphire Substrate is provided;
S2: form light emitting semiconductor layer on a sapphire substrate, and form some high-impedance state ion implanted layers by ion implantation technology in the precalculated position of light emitting semiconductor layer, described light emitting semiconductor layer is divided into the independent light emitting semiconductor layer of some insulated separation by described some high-impedance state ion implanted layers, and each independent light emitting semiconductor layer includes the n type semiconductor layer, active layer and the p type semiconductor layer that stack gradually;
S3: form a groove in each independent light emitting semiconductor layer, described groove runs through described p type semiconductor layer, active layer and at least part of n type semiconductor layer, and a sidewall of each high-impedance state ion implanted layer is come out by a groove;
S4: form the first electrode on the p type semiconductor layer of each independent light emitting semiconductor layer, in the groove of each independent light emitting semiconductor layer, form the second electrode, and the second electrode of independent light emitting semiconductor layer adjacent for part and the electrical connection of the first electrode are formed cascaded structure;
S5: form passivation protection layer on the surface of all exposures of described independent light emitting semiconductor layer, described passivation protection layer has the first electrode in the independent light emitting semiconductor layer headed by the described cascaded structure of exposure and the fairlead for the second electrode in the independent light emitting semiconductor layer of tail.
LED structure provided by the present invention and preparation method thereof is illustrated in greater detail below in conjunction with Fig. 1-8.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
As shown in Figure 1, a Sapphire Substrate 1 is provided.
As shown in Figure 2, form light emitting semiconductor layer 2 by MOCVD technique or molecular beam epitaxy technique in described Sapphire Substrate 1, described light emitting semiconductor layer 2 at least comprises the n type semiconductor layer 21, active layer 22 and the p type semiconductor layer 23 that stack gradually.
At this, after forming light emitting semiconductor layer 2 by MOCVD technique or molecular beam epitaxy technique in described Sapphire Substrate 1, described light emitting semiconductor layer 2 forms mask layer, and block with described mask layer and carry out ion implantation, thus form some high-impedance state ion implanted layers 3 in the precalculated position of described light emitting semiconductor layer 2.Or, formed in the process of described light emitting semiconductor layer 2 by MOCVD technique or molecular beam epitaxy technique, form some high-impedance state ion implanted layers 3 by ion implantation technique in the precalculated position of described light emitting semiconductor layer 2, described light emitting semiconductor layer 2 is divided into the independent light emitting semiconductor layer of some insulated separation by described high-impedance state ion implanted layer 3 simultaneously.
In the present embodiment, in described light emitting semiconductor layer 2, inject oxonium ion form high-impedance state ion implanted layer 3.Be understandable that, also can inject other ions in other embodiments of the present invention, as long as realize forming the object of high-impedance state ion implanted layer and then described light emitting semiconductor layer 2 being divided into the independent light emitting semiconductor layer of some insulated separation.
As shown in Figure 3, some grooves 2 ' are formed in the presumptive area of described light emitting semiconductor layer 2 by lithographic etch process, namely in each independent light emitting semiconductor layer, a groove 2 ' is all formed, described groove 2 ' runs through described p type semiconductor layer 23, active layer 22 and at least part of n type semiconductor layer 21, and a sidewall of described high-impedance state ion implanted layer 3 is come out by described groove 2 ', in other words, p type semiconductor layer 23 in groove 2 ' and active layer 22 are removed completely, and n type semiconductor layer 21 is removed a part, and each high-impedance state ion implanted layer 3 is close to a groove 2 '.
As shown in Figure 4, form barrier layer 4 by deposition, photoetching, etching technics on the subregion of described p type semiconductor layer 23, the material on described barrier layer 4 is such as silicon dioxide.
As shown in Figure 5, form contact layer 5 by evaporation technology on described p type semiconductor layer 23 and barrier layer 4, the material of described contact layer 5 is such as ITO.
As shown in Figure 6, pass through evaporation technology, the contact layer 5 of each independent light emitting semiconductor layer is formed the first electrode 61, the second electrode 62 is formed in the groove 2 ' of each independent light emitting semiconductor layer, and selectively and be synchronously connected with the first electrode 61 metal by the second electrode 62 in light emitting semiconductor layer adjacent for part, form cascaded structure.
As shown in Figure 7, on the sidewall of all exposures of described independent light emitting semiconductor layer, passivation protection layer 7 is formed by pecvd process; And form fairlead by lithographic etch process to the first electrode 61 in the independent light emitting semiconductor layer headed by cascaded structure with for the passivation protection layer 7 on the second electrode 62 in the independent light emitting semiconductor layer of tail carries out hole opening technology; the subregion of the first electrode 61 and the subregion for the second electrode 62 in the independent light emitting semiconductor layer 2 of tail in independent light emitting semiconductor layer headed by exposing, so that lead-in wire.The material of described passivation protection layer 7 is such as silicon dioxide.
Preferably; as shown in Figure 8; in order to form the smooth passivation protection layer 7 in surface on the upper surface and each sidewall thereof of independent light emitting semiconductor layer; formed in the process of passivation protection layer by pecvd process; while described Sapphire Substrate revolves round the sun under the drive of carrier, described Sapphire Substrate is also carrying out high speed rotation (namely light emitting semiconductor layer is doing the revolution of two kinds of forms).
Accordingly, the present invention also provides a kind of LED structure, as shown in figs. 1-7, comprising:
Sapphire Substrate 1;
Be formed at the light emitting semiconductor layer 2 in described Sapphire Substrate 1;
Be formed at the some high-impedance state ion implanted layers 3 in described light emitting semiconductor layer 2, described light emitting semiconductor layer 2 is divided into the independent light emitting semiconductor layer of some insulated separation by described some high-impedance state ion implanted layers 3, and each independent light emitting semiconductor layer includes the n type semiconductor layer 21, active layer 22 and the p type semiconductor layer 23 that stack gradually;
Run through the groove 2 ' of described p type semiconductor layer 23, active layer 22 and at least part of n type semiconductor layer 21, described groove 2 ' exposes a sidewall of described high-impedance state ion implanted layer 3;
The second electrode 62 being formed at the first electrode 61 on the p type semiconductor layer 23 of described each independent light emitting semiconductor layer and being formed in the groove 2 ' of described each independent light emitting semiconductor layer, the second electrode 62 in the independent light emitting semiconductor layer that part is adjacent is connected with the first electrode 61 metal, forms cascaded structure; And
Be formed at the passivation protection layer 7 on the surface of all exposures of described light emitting semiconductor layer 2, described passivation protection layer 7 has the first electrode in the independent light emitting semiconductor layer headed by the described cascaded structure of exposure and the fairlead for the second electrode in the independent light emitting semiconductor layer of tail.
Wherein, described high-impedance state ion implanted layer 3 runs through described p type semiconductor layer 23, active layer 22, n type semiconductor layer 21, is connected with Sapphire Substrate 1 seamless surface, and it is formed by injecting oxonium ion in light emitting semiconductor layer.
Preferably, described LED structure also comprises the barrier layer 4 on the subregion being formed at described p type semiconductor layer 23, and the material on described barrier layer 4 is silicon dioxide.On described barrier layer 4 and on described P semiconductor layer 23, be also formed with contact layer 5, the material of described contact layer 5 is ITO, and described first electrode 61 is positioned on contact layer 5.
In sum, LED structure manufacture method of the present invention utilizes ion implantation technique, in the process that light emitting semiconductor layer is formed or after its formation, form high-impedance state ion implanted layer over a predetermined area, described light emitting semiconductor layer is divided into the independent light emitting semiconductor layer of some insulated separation by described some high-impedance state ion implanted layers, follow-up chip manufacturing end is without the need to carrying out the making of isolation channel again by lithographic etch process, more need not use filling insulating material isolation channel again, and the processing step of these chip manufacturing end cost intensive just, also be that it improves the technical bottleneck of reliability and yield.
In addition, first electrode of each independent emitting semiconductor can form metal according to demand with the second electrode and be connected while independent emitting semiconductor first electrode of formation with the second electrode, namely the cascaded structure of any number is formed, the light emitting semiconductor layer forming cascaded structure, without the need to testing separately, cutting, encapsulate, has saved test, cutting, packaging cost.
In addition, because each light emitting semiconductor layer described can form cascaded structure while formation electrode, so LED structure provided by the present invention can at larger operating at voltages, and, because cascaded structure synchronously can be formed with electrode, the tube core mediated can not by the constraint of lithographic line width, not by the constraint that routing requires, the area of luminous zone occupied by it can be less, so this further increases again the luminosity of LED.
Although by exemplary embodiment to invention has been detailed description, it should be appreciated by those skilled in the art, above exemplary embodiment is only to be described, instead of in order to limit the scope of the invention.It should be appreciated by those skilled in the art, can without departing from the scope and spirit of the present invention, above embodiment be modified.Scope of the present invention is limited by claims.
Claims (13)
1. a LED structure manufacture method, is characterized in that, comprising:
One Sapphire Substrate is provided;
Described Sapphire Substrate forms light emitting semiconductor layer, and form some high-impedance state ion implanted layers by ion implantation technology in the precalculated position of light emitting semiconductor layer, light emitting semiconductor layer is divided into the independent light emitting semiconductor layer of some insulated separation by described some high-impedance state ion implanted layers, and each independent light emitting semiconductor layer includes the n type semiconductor layer, active layer and the p type semiconductor layer that stack gradually;
In each independent light emitting semiconductor layer, form a groove, described groove runs through described p type semiconductor layer, active layer and at least part of n type semiconductor layer, and a sidewall of each high-impedance state ion implanted layer is come out by a groove;
The p type semiconductor layer of each independent light emitting semiconductor layer forms the first electrode, in the groove of each independent light emitting semiconductor layer, form the second electrode, and the second electrode of independent light emitting semiconductor layer adjacent for part and the electrical connection of the first electrode are formed cascaded structure;
The surface of all exposures of described light emitting semiconductor layer is formed passivation protection layer, and described passivation protection layer has the first electrode in the independent light emitting semiconductor layer headed by the described cascaded structure of exposure and the fairlead for the second electrode in the independent light emitting semiconductor layer of tail.
2. LED structure manufacture method as claimed in claim 1, it is characterized in that, after forming light emitting semiconductor layer by MOCVD technique or molecular beam epitaxy technique in described Sapphire Substrate, described light emitting semiconductor layer forms mask layer, and blocks with described mask layer and carry out ion implantation to form some high-impedance state ion implanted layers in the precalculated position of described light emitting semiconductor layer.
3. LED structure manufacture method as claimed in claim 1, it is characterized in that, formed in the process of light emitting semiconductor layer by MOCVD technique or molecular beam epitaxy technique in described Sapphire Substrate, form some high-impedance state ion implanted layers by ion implantation technique in the precalculated position of described light emitting semiconductor layer simultaneously.
4. LED structure manufacture method as claimed in claim 2 or claim 3, is characterized in that, inject oxonium ion and form described some high-impedance state ion implanted layers in described light emitting semiconductor layer.
5. LED structure manufacture method as claimed in claim 1, is characterized in that, after forming a groove, the subregion of described p type semiconductor layer forms barrier layer in each independent light emitting semiconductor layer.
6. LED structure manufacture method as claimed in claim 5, is characterized in that, after the subregion of described p type semiconductor layer forms barrier layer, described p type semiconductor layer and barrier layer form contact layer.
7. LED structure manufacture method as claimed in claim 6, it is characterized in that, the material on described barrier layer is silicon dioxide, and the material of described contact layer is ITO.
8. LED structure manufacture method as claimed in claim 1, is characterized in that, form passivation protection layer by pecvd process on the surface of all exposures of described independent light emitting semiconductor layer.
9. LED structure manufacture method as claimed in claim 8, be is characterized in that, formed in the process of described passivation protection layer by pecvd process, described Sapphire Substrate while revolving round the sun under the drive of carrier described Sapphire Substrate also carry out rotation.
10. a LED structure, is characterized in that, comprising:
Sapphire Substrate;
Be formed at the light emitting semiconductor layer in described Sapphire Substrate;
Be formed at the some high-impedance state ion implanted layers in described light emitting semiconductor layer, described light emitting semiconductor layer is divided into the independent light emitting semiconductor layer of some insulated separation by described some high-impedance state ion implanted layers, and each independent light emitting semiconductor layer includes the n type semiconductor layer, active layer and the p type semiconductor layer that stack gradually;
Some grooves running through described p type semiconductor layer, active layer and at least part of n type semiconductor layer, each described groove exposes a sidewall of a high-impedance state ion implanted layer;
The second electrode being formed at the first electrode on the p type semiconductor layer of described each independent light emitting semiconductor layer and being formed in the groove of described each independent light emitting semiconductor layer, the second electrode in the independent light emitting semiconductor layer that part is adjacent and the electrical connection of the first electrode, form cascaded structure; And
Be formed at the passivation protection layer on the surface of all exposures of described light emitting semiconductor layer, described passivation protection layer has the first electrode in the independent light emitting semiconductor layer headed by the described cascaded structure of exposure and the fairlead for the second electrode in the independent light emitting semiconductor layer of tail.
11. LED structure as claimed in claim 10, is characterized in that, also comprise the barrier layer on the subregion being formed at described p type semiconductor layer.
12. LED structure as claimed in claim 11, is characterized in that, also comprise the contact layer be formed on described p type semiconductor layer and barrier layer.
13. LED structure as claimed in claim 12, it is characterized in that, the material on described barrier layer is silicon dioxide, the material of described contact layer is ITO.
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CN110010542A (en) * | 2019-04-18 | 2019-07-12 | 广东省半导体产业技术研究院 | Miniature LED component, Minitype LED array and manufacturing method |
CN110246937A (en) * | 2018-03-09 | 2019-09-17 | 群创光电股份有限公司 | Show equipment |
US11011677B2 (en) | 2018-03-09 | 2021-05-18 | Innolux Corporation | Display device |
CN112864290A (en) * | 2020-04-09 | 2021-05-28 | 镭昱光电科技(苏州)有限公司 | Light emitting diode structure and manufacturing method thereof |
CN114388675A (en) * | 2021-12-21 | 2022-04-22 | 南昌大学 | GaN-based micro LED chip and preparation method thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102315353A (en) * | 2011-09-30 | 2012-01-11 | 厦门市三安光电科技有限公司 | Inverted integrated LED and production method thereof |
CN102867837A (en) * | 2012-09-13 | 2013-01-09 | 中国科学院半导体研究所 | Manufacture method of array type high-voltage LED device |
CN102881707A (en) * | 2012-09-14 | 2013-01-16 | 金木子 | High-voltage direct current or alternating current chip with front fixing structure |
JP2013038193A (en) * | 2011-08-05 | 2013-02-21 | Nippon Telegr & Teleph Corp <Ntt> | Method for introducing isoelectronic center into silicon thin flim by ion implantation, and silicon light-emitting device |
CN104064640A (en) * | 2014-07-04 | 2014-09-24 | 映瑞光电科技(上海)有限公司 | Vertical type led structure and manufacturing method thereof |
CN204216044U (en) * | 2014-11-28 | 2015-03-18 | 杭州士兰明芯科技有限公司 | LED structure |
-
2014
- 2014-11-28 CN CN201410709185.3A patent/CN104409584B/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013038193A (en) * | 2011-08-05 | 2013-02-21 | Nippon Telegr & Teleph Corp <Ntt> | Method for introducing isoelectronic center into silicon thin flim by ion implantation, and silicon light-emitting device |
CN102315353A (en) * | 2011-09-30 | 2012-01-11 | 厦门市三安光电科技有限公司 | Inverted integrated LED and production method thereof |
CN102867837A (en) * | 2012-09-13 | 2013-01-09 | 中国科学院半导体研究所 | Manufacture method of array type high-voltage LED device |
CN102881707A (en) * | 2012-09-14 | 2013-01-16 | 金木子 | High-voltage direct current or alternating current chip with front fixing structure |
CN104064640A (en) * | 2014-07-04 | 2014-09-24 | 映瑞光电科技(上海)有限公司 | Vertical type led structure and manufacturing method thereof |
CN204216044U (en) * | 2014-11-28 | 2015-03-18 | 杭州士兰明芯科技有限公司 | LED structure |
Cited By (7)
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CN106981497A (en) * | 2017-02-14 | 2017-07-25 | 盐城东紫光电科技有限公司 | A kind of high pressure flip LED chips structure and its manufacture method |
CN110246937A (en) * | 2018-03-09 | 2019-09-17 | 群创光电股份有限公司 | Show equipment |
US11011677B2 (en) | 2018-03-09 | 2021-05-18 | Innolux Corporation | Display device |
CN110010542A (en) * | 2019-04-18 | 2019-07-12 | 广东省半导体产业技术研究院 | Miniature LED component, Minitype LED array and manufacturing method |
CN112864290A (en) * | 2020-04-09 | 2021-05-28 | 镭昱光电科技(苏州)有限公司 | Light emitting diode structure and manufacturing method thereof |
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CN114388675B (en) * | 2021-12-21 | 2024-04-16 | 南昌大学 | GaN-based miniature LED chip and preparation method thereof |
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