CN104409369A - Method for manufacturing packaging assembly - Google Patents
Method for manufacturing packaging assembly Download PDFInfo
- Publication number
- CN104409369A CN104409369A CN201410603661.3A CN201410603661A CN104409369A CN 104409369 A CN104409369 A CN 104409369A CN 201410603661 A CN201410603661 A CN 201410603661A CN 104409369 A CN104409369 A CN 104409369A
- Authority
- CN
- China
- Prior art keywords
- electronic component
- lead
- leads
- wire
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Disclosed in the invention is a method for manufacturing a packaging assembly. The method comprises the following steps that: a lead frame is formed at a substrate, wherein the lead frame includes a plurality of leads and first surfaces of the leads are exposed; electronic elements at a plurality of levels are installed at the lead frame, so that the electronic elements at at least one level are electrically connected with the first surfaces of at least one group of leads among the multiple leads; and at least one part of the substrate is removed, so that second surfaces, opposite to the first surface, of the multiple leads are exposed for external connection. According to the method, overturning of a semiconductor structure during the manufacturing process is not needed. The yield of the packaging assemblies can be improved; the cost can be lowered; and the packaging quality can be enhanced.
Description
Technical field
The present invention relates to semiconductor packages, relate to package assembling manufacture method particularly.
Background technology
Along with the increase of the demand of the miniaturization of electronic component, lightweight and multifunction, more and more higher to the requirement of semiconductor packaging density, to reach the effect reducing package dimension.Therefore, lead frame and the package assembling comprising multiple semiconductor element has become new focus is used.In this package assembling, configuration of multiple semiconductor element and attaching method thereof has vital impact to the size of package assembling and performance.
Proposed stacking multilayer encapsulation assembly, wherein multiple semiconductor element is stacked on same lead frame.Be positioned at undermost semiconductor element to be directly fixed on lead frame by solder.The semiconductor element being positioned at upper strata can be fixed on the top surface of the semiconductor element of one deck below by adhesive layer.Then, be electrically connected on lead frame by the semiconductor element of bonding line by upper strata.Semiconductor element integrated in a package assembling can be not only integrated circuit (IC) chip (power device chip of such as Switching Power Supply and control chip etc.), also can be discrete component (such as power plant, electric capacity and resistance etc.).
Relative to planar package assembly, stacking multilayer encapsulation assembly can reduce chip area footprints, thus reduces package dimension, has shorter time of delay and less noise simultaneously.Therefore, for the formation of the concern of the technique people day by day of multilayer encapsulation assembly.
But stacked multilayer semiconductor element causes packaging technology complicated on lead frame, such as, in packaging technology, need to overturn lead frame, thus reduce the output of package assembling, cause cost to improve.In addition, in packaging technology, a part of region etching of the substrate of carrying lead frame runs through.The thickness of substrate is sufficiently large, just can provide required mechanical support effect.As a result, the size of package assembling is difficult to miniaturization.
Therefore, expect to optimize further package assembling manufacture method to reduce process complexity.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of manufacture method of package assembling, with the complicated problem causing cost to improve of the manufacturing process solving multilayer encapsulation assembly.
According to the present invention, provide a kind of method of manufacturing and encapsulation assembly, comprising: on substrate, form lead frame, described lead frame comprises a plurality of leads that first surface exposes; Lead frame is installed the electronic component of many levels, and the first surface that the electronic component of at least one aspect and at least one group in described a plurality of leads are gone between is electrically connected; And remove substrate at least partially, the second surface relative with first surface of described a plurality of leads is exposed and connects for outside.
Preferably, in institute's method, the step forming lead frame comprises: on base plate for packaging, form a plurality of leads; And at least another group in described a plurality of leads forms table top on going between, the surface of described table top is higher than described first surface, and the apparent height of the upper table top formed of difference group lead-in wire in described at least another group lead-in wire is different, wherein, in the step of electronic component of installing many levels, at least another organizes the first surface gone between and is electrically connected the electronic component of at least another aspect with described in described a plurality of leads.
Preferably, in institute's method, separated by groove between described a plurality of leads, formed between the step of a plurality of leads and the step forming table top, also comprising and adopt encapsulating compound filling groove.
Preferably, in institute's method, the step forming a plurality of leads comprises: on substrate, form metal level; And via comprising the mask of lead pattern, by etching, metal layer pattern is changed into described a plurality of leads.
Preferably, in institute's method, the step forming a plurality of leads comprises: via the mask comprising lead-in wire complementary patterns, form described a plurality of leads by the exposed surface coating metal material at substrate.
Preferably, in institute's method, the step forming a plurality of leads comprises: on substrate, form the mask comprising lead-in wire complementary patterns; And by etching, the top layer of substrate is patterned to described a plurality of leads.
Preferably, in institute's method, the step forming a plurality of leads comprises: by punching press, the top layer of substrate is patterned to described a plurality of leads.
Preferably, in institute's method, the step that lead frame is installed the electronic component of many levels comprises: from the first level of contiguous lead frame, aspect installing electronic elements one by one; And after the electronic component installing structure at all levels, encapsulating compound is adopted to cover lead frame and electronic component at least partly, wherein, the electronic component of the first level is electrically connected with one group of first surface gone between during described at least one group goes between, and the electronic component of aspect is electrically connected with described at least another table top organizing the lead-in wire of the respective sets in going between subsequently.
Preferably, in institute's method, the step that lead frame is installed the electronic component of many levels comprises: from the first level of contiguous lead frame, aspect installing electronic elements and employing encapsulating compound cover the electronic component of corresponding aspect at least partly one by one, wherein, after the electronic component of an installation aspect and before the electronic component of the next aspect of installation, encapsulating compound is adopted to cover lead-in wire and the electronic component of a described aspect at least partly, the electronic component of the first level is electrically connected with one group of first surface gone between during described at least one group goes between, the electronic component of aspect is electrically connected with described at least another table top organizing the lead-in wire of the respective sets in going between subsequently.
Preferably, in institute's method, before the electronic component installing described next aspect, also comprise the encapsulating compound of a smooth described aspect to expose the first surface of the lead-in wire of described next aspect.
Preferably, in institute's method, in the step of electronic component of installing many levels, the described at least one group of first surface gone between in the electronic component of at least one aspect described and described a plurality of leads is formed welding flux interconnected, and the electronic component of described at least another aspect and the surface of described table top are formed welding flux interconnected.
Preferably, adopting between the step of encapsulating compound filling groove and the step forming table top, also comprise formation to reroute layer, wherein, the described layer that reroutes comprises many strip conductors line, described many strip conductors line horizontal expansion and comprise each other relative first surface and second surface, the first surface of wherein said many strip conductors line contacts the first surface of described a plurality of leads.
Preferably, in institute's method, in the step of electronic component of installing many levels, the second surface of the electronic component of at least one aspect described and at least one group of conductor lines of described many strip conductors line is formed welding flux interconnected, and the electronic component of described at least another aspect and the surface of described table top are formed welding flux interconnected.
Method according to claim, lead frame is installed between the step of the electronic component of many levels and the step removing substrate, also comprises: in the surperficial additional heat sink of encapsulating compound.
Method according to claim, before the surperficial additional heat sink of encapsulating compound, also comprises: by grinding smooth envelope encapsulating compound and reducing the thickness of the top layer of encapsulating compound.
In the above-mentioned method according to manufacture multilayer encapsulation assembly of the present invention, the first surface of lead-in wire is relative with substrate, second surface and substrate contacts.In the manufacture process of package assembling, the first surface of lead-in wire is placed all the time upward, thus without the need to overturning semiconductor structure.In addition, substrate provides mechanical support effect in almost whole packaging technology, until adopted the second encapsulating compound encapsulating lead frame and electronic component, just removes substrate.In final package assembling, the first surface of lead-in wire provides the interconnecting area with the electronic component of encapsulating structure inside, second surface to provide the contact zone with external circuit (such as printed circuit board (PCB), i.e. PCB).
Due in the above-mentioned methods without the need to overturning semiconductor structure, therefore, effectively can improve the output of encapsulation, reducing packaging cost.
In packaging technology, substrate keeps complete and does not etch and run through, and step to the last just etches removal.The mechanically supportive of substrate almost in whole encapsulation process is better, is conducive to the quality improving encapsulation.Even if because the thickness of substrate reduces, enough mechanical support effects also can be provided, is therefore conducive to the miniaturization of package assembling.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the embodiment of the present invention, above-mentioned and other objects of the present invention, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1 a to 1g illustrates the sectional view of each step manufacturing the method for multilayer encapsulation assembly according to prior art;
Fig. 2 a to 2g illustrates the sectional view of each step of the first embodiment of the method for multilayer encapsulation assembly constructed in accordance;
Fig. 3 a and 3b illustrates the sectional view of a part of step of the second embodiment of the method for multilayer encapsulation assembly constructed in accordance;
Fig. 4 a to 4d illustrates the sectional view of a part of step of method the 3rd embodiment of multilayer encapsulation assembly constructed in accordance; And
Fig. 5 a to 5e illustrates the sectional view of a part of step of method the 4th embodiment of multilayer encapsulation assembly constructed in accordance.
Embodiment
Hereinafter with reference to accompanying drawing, various embodiment of the present invention is described in more detail.In various figures, identical element adopts same or similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.For brevity, in a width figure, the encapsulating structure obtained after several step can be described.
Be to be understood that, when describing encapsulating structure, when one deck, region are called be positioned at another layer, another region " above " or " top " time, can refer to be located immediately at another layer, another over, or itself and another layer, also comprise other layer or region between another region.Further, if overturn by device, this one deck, a region will be positioned at another layer, another region " below " or " below ".If in order to describe the situation being located immediately at another layer, another over, will adopt herein " directly exist ... above " or " ... above and adjoin with it " form of presentation.
Describe hereinafter many specific details of the present invention, the structure such as encapsulated, material, size, treatment process and technology, more clearly to understand the disclosure.But just as the skilled person will understand like that, the disclosure can be realized not in accordance with these specific details.
In this application, term " semiconductor structure " refers to, in the general designation manufacturing the whole semiconductor structure formed in each step of semiconductor device, comprise all layers or region that have been formed.Term " electronic component " is not limited to semiconductor element, should be understood to the encapsulated object of broad sense, comprises semiconductor element and discrete component (such as resistor, capacitor, inductor, diode, transistor) etc.
Fig. 1 a to 1g illustrates the sectional view of each step manufacturing the method for multilayer encapsulation assembly according to prior art.The method is included in and substrate is formed lead frame and the electronic component of stacking many levels on lead frame.
The method such as start from comprising substrate 101 (such as iron-nickel alloy) and on the lamination of metal level (such as Cu), wherein substrate 101 is as supporting layer, and the most at last as sacrifice layer part remove.Such as adopt the first mask, be patterned in banded lead-in wire 102 by etch metal layers, as shown in Figure 1a.In etching, etchant optionally removes the expose portion of metal level relative to the substrate 101 of lower floor.Remove the first mask after the etching.
The first surface of the lead-in wire 102 that above-mentioned steps is formed is relative with substrate 101, and second surface contacts with substrate 101.
Then, the first encapsulating compound 103 (such as epoxy resin) is adopted to cover the exposed surface of lead-in wire 102 and substrate 101, as shown in Figure 1 b.The thickness of encapsulating compound 103 is at least enough to fill the groove between adjacent lead-in wire 102.Such as by grinding smooth encapsulating compound 103, the first surface of lead-in wire 102 is exposed again, as illustrated in figure 1 c.Such as adopt the second mask, adopt optionally etchant, in the installation region of substrate 101, remove substrate 101 relative to lead-in wire 102 and encapsulating compound 103, thus form the opening of the second surface of exposed leads 102, as shown in Figure 1 d.First surface and second surface are toward each other.The non-etching part of substrate 101 provides mechanical support effect in an etching step.After the second surface of exposed leads 102, semiconductor structure is spun upside down.Such as adopt the 3rd mask, block whole second surfaces of part lead-in wire, and block the second surface being at least partially positioned at the peripheral another part lead-in wire of this part lead-in wire.By the metal material that the Metal Phase gone between at exposed surface plating (such as plating, chemical plating etc.) and the composition of described another part lead-in wire 102 is same, form table top 104, as shown in fig. le.The described part lead-in wire 102 blocked, as first group of lead-in wire, forms described another part lead-in wire 102 of table top as second group of lead-in wire.Remove the 3rd mask after plating, thus form the lead frame 110 comprising two groups of lead-in wires 102 on the substrate 101.
In lead frame 110, the second surface of lead-in wire 102 is placed upward.The second surface of first group of lead-in wire in lead-in wire 102 directly exposes, for providing interconnecting area.The second surface of second group of lead-in wire in lead-in wire 102 forms table top 104, and this table top 104 is for providing interconnecting area.
First electronic component 120 is placed on lead frame 110.The internal circuit of the first electronic component 120 is electrically connected to conductive projection 106 via conductive channel etc.The solder ball 105 being attached to conductive projection 106 end contacts with first group of interconnecting area gone between in lead-in wire 102.Perform reflux technique, solder ball 105 is melted and forms solder 105, the first electronic component 120 is fixed on lead frame 110.Then, the second electronic component 130 is placed on lead frame 110.Again perform reflux technique, utilize solder 107 to be fixed on by second electronic component 130 on second group of lead-in wire of lead frame 110, as shown in Figure 1 g.Then, adopt the second encapsulating compound 140 (such as epoxy resin) to encapsulate lead frame 110, electronic component 120,130, thus form package assembling 100.
Manufacture in the method for multilayer encapsulation assembly according to prior art above-mentioned, the first surface of lead-in wire 102 is relative with substrate 101, and second surface contacts with substrate 101.The first surface of lead-in wire 102 is initially placed upward.In the step shown in Fig. 1 e, semiconductor structure overturns.This is because be not enough to supporting wire frame 110 in follow-up technique through the mechanical strength of overetched substrate 101.Through upset, the first surface of lead-in wire 102 is placed down, thus utilizes the first surface of lead-in wire 102 self to provide mechanical support effect in subsequent steps.
In final package assembling 100, the first surface of lead-in wire 102 is placed down, and for providing the contact zone with external circuit, second surface is placed upward, for providing the interconnecting area with the electronic component of encapsulating structure inside.
Owing to needing to overturn semiconductor structure in the above-mentioned methods, therefore operating process is comparatively complicated, and is unfavorable for the output improving packaging, thus can not effectively reduce the cost of encapsulation.
Fig. 2 a to 2g illustrates the sectional view of each step of the first embodiment of the method for multilayer encapsulation assembly constructed in accordance.The method is included in and substrate is formed lead frame and the electronic component of stacking many levels on lead frame.
The method such as start from comprising substrate 201 (such as iron-nickel alloy) and on the lamination of metal level (such as Cu), wherein substrate 201 is as supporting layer, and the most at last as sacrifice layer part remove.Such as adopt the first mask comprising lead pattern, be patterned in banded lead-in wire 202 by etch metal layers, as shown in Figure 2 a.In etching, etchant optionally removes the expose portion of metal level relative to the substrate 201 of lower floor.Remove the first mask after the etching.
The first surface of the lead-in wire 202 that above-mentioned steps is formed is relative with substrate 202, and second surface contacts with substrate 202.
Then, the first encapsulating compound 203 (such as epoxy resin) is adopted to cover the exposed surface of lead-in wire 202 and substrate 201, as shown in Figure 2 b.The thickness of encapsulating compound 203 is at least enough to fill the groove between adjacent lead-in wire 202.Such as by grinding smooth encapsulating compound 203, the first surface of lead-in wire 202 is exposed again, as shown in Figure 2 c.Such as adopt the second mask, block whole first surfaces of part lead-in wire, and block the first surface being at least partially positioned at the peripheral another part lead-in wire of this part lead-in wire.By the metal material that the Metal Phase gone between at exposed surface plating and the composition of described another part lead-in wire 202 is same, form table top 204, as shown in Figure 2 d.The described part lead-in wire 202 blocked, as first group of lead-in wire, forms described another part lead-in wire 202 of table top as second group of lead-in wire.Remove the second mask after plating, thus on substrate 201, form the lead frame 210 comprising two groups of lead-in wires 202.
In the step forming table top 204, the opening due to the second mask is difficult to accurately aim at lead-in wire 202, and therefore the area of usual second mask is slightly less than the sectional area (with the sectional area in opening parallel direction) of lead-in wire 202.As a result, the surface area of table top 204 is slightly less than the surface area of lead-in wire 202, to guarantee that table top 204 is fully formed on the surface of lead-in wire 202, and can avoid the formation of table top 204 will be connected two lead-in wire 202 be communicated with.
In lead frame 210, the first surface of lead-in wire 202 is placed upward.The first surface of first group of lead-in wire in lead-in wire 202 directly exposes, for providing interconnecting area.The first surface of second group of lead-in wire in lead-in wire 202 forms table top 204, and this table top 204 is for providing interconnecting area.
First electronic component 220 is placed on lead frame 210.The internal circuit of the first electronic component 220 is electrically connected to conductive projection 206 via conductive channel etc.The solder ball 205 being attached to conductive projection 206 end contacts with first group of interconnecting area gone between in lead-in wire 202.Perform reflux technique, solder ball 205 is melted and forms solder 205, the first electronic component 220 is fixed on lead frame 210.Then, the second electronic component 230 is placed on lead frame 210.Again perform reflux technique, utilize solder 207 to be fixed on by second electronic component 230 on the table top 204 of second group of lead-in wire of lead frame 210, as shown in Figure 2 e.Then, the second encapsulating compound 240 (such as epoxy resin) is adopted to encapsulate lead frame 210, electronic component 220,230, as shown in figure 2f.Such as when not using mask, adopting optionally etchant, removing substrate 201 relative to lead-in wire 202 and encapsulating compound 203, thus form the second surface of exposed leads 202, as shown in Figure 2 g, thus form package assembling 200.
First electronic component 220 is such as the chip comprising power device, such as, comprise the chip of the main power tube in Switching Power Supply power stage circuit, also can comprise the control circuit of Switching Power Supply in this chip, also can comprise the synchronous rectifier of Switching Power Supply.Second electronic component 230 such as comprises the inductance in Switching Power Supply, also can be the discrete component such as electric capacity or resistance.
In a preferred embodiment, after the step shown in Fig. 2 f forms the second encapsulating compound 240, can on the surface of the second encapsulating compound 240 additional heat sink.Such as by grinding smooth envelope second encapsulating compound 240, and reduce the thickness of the top layer of the second encapsulating compound 240, to reduce encapsulation volume and to improve heat dissipation efficiency.Then continue the step shown in Fig. 2 g, remove substrate 210.
In an alternative embodiment, the step that substrate 201 is formed lead-in wire 202 starts from substrate 201 (such as iron-nickel alloy), and wherein substrate 201 is as supporting layer, and the most at last as sacrifice layer part remove.Such as adopt the first mask, this first mask comprises lead-in wire complementary patterns, and namely the opening of mask corresponds to the pattern of lead-in wire.First mask blocks the part surface of substrate 201.By the exposed surface coating metal material (such as Cu) at described substrate 201, formed in banded lead-in wire 202, as shown in Figure 2 a.Remove the first mask after plating.Then, the step performing Fig. 2 b to Fig. 2 g is continued, to form package assembling 200.
In the embodiment that another substitutes, the step that substrate 201 is formed lead-in wire 202 starts from substrate 201 (such as iron-nickel alloy).Such as by half-etching and/or Sheet Metal Forming Technology, the surface of substrate 201 forms lead-in wire 202, as shown in Figure 2 a.Alternatively, encapsulating compound 203 is filled in the groove between adjacent lead-in wire 202.Then, the step performing Fig. 2 d to Fig. 2 g is continued, to form package assembling 200.
Fig. 3 a and 3b illustrates the sectional view of a part of step of the second embodiment of the method for multilayer encapsulation assembly constructed in accordance.According in the method for the second embodiment, first form lead frame 310 according to the step shown in Fig. 2 a to 2d.Lead frame 310 is positioned on substrate 301, comprises the first group of lead-in wire not forming table top and the second group of lead-in wire forming table top 304.The surface of first group of lead-in wire directly provides interconnecting area, and the table top 304 of second group of lead-in wire provides interconnecting area.
Be with the first embodiment difference, continue to perform the step shown in Fig. 3 a and 3b according to the method for the second embodiment.
First electronic component 320 is placed on lead frame 310.The internal circuit of the first electronic component 320 is electrically connected to conductive projection 306 via conductive channel etc.The solder ball 305 being attached to conductive projection 306 end contacts with first group of interconnecting area gone between in lead-in wire 302.Perform reflux technique, solder ball 305 is melted and forms solder 305, the first electronic component 320 is fixed on lead frame 310.Then, the second encapsulating compound 340 (such as epoxy resin) is adopted to encapsulate lead frame 310, electronic component 320.Such as by grinding smooth envelope second encapsulating compound 340, to expose the table top 304 of second group of lead-in wire 302.Then, the second electronic component 330 is placed on the second encapsulating compound 340.Again perform reflux technique, utilize solder 307 to be fixed on by second electronic component 330 on the table top 304 of second group of lead-in wire of lead frame 310.Then, the 3rd encapsulating compound 350 (such as epoxy resin) is adopted to encapsulate lead frame 310, electronic component 320,330, as shown in Figure 3 a.Such as when not using mask, adopting optionally etchant, removing substrate 301 relative to lead-in wire 302 and encapsulating compound 303, thus form the second surface of exposed leads 302, as shown in Figure 3 b, thus form package assembling 300.
Fig. 4 a to 4d illustrates the sectional view of a part of step of the 3rd embodiment of the method for multilayer encapsulation assembly constructed in accordance.According in the method for the 3rd embodiment, first on substrate 401, form lead-in wire 402 according to the step shown in Fig. 2 a.The first surface of lead-in wire 402 is relative with substrate 401, and second surface contacts with substrate 401.
Be with the first embodiment difference, continue to perform the step shown in Fig. 4 a to 4d according to the method for the 3rd embodiment.
Then, such as, adopt the first mask, block whole first surfaces of part lead-in wire, and block the first surface being at least partially positioned at the peripheral another part lead-in wire of this part lead-in wire.By the metal material that the Metal Phase gone between at exposed surface plating and the composition of described another part lead-in wire 402 is same, form table top 404, as shown in fig. 4 a.The described part lead-in wire 402 blocked, as first group of lead-in wire, forms described another part lead-in wire 402 of table top as second group of lead-in wire.Remove the first mask after plating, thus on substrate 401, form the lead frame 410 comprising two groups of lead-in wires 402.
In lead frame 410, the first surface of lead-in wire 402 is placed upward.The first surface of first group of lead-in wire in lead-in wire 402 directly exposes, for providing interconnecting area.The first surface of second group of lead-in wire in lead-in wire 402 forms table top 404, and this table top 404 is for providing interconnecting area.
First electronic component 420 is placed on lead frame 410.The internal circuit of the first electronic component 420 is electrically connected to conductive projection 406 via conductive channel etc.The solder ball 405 being attached to conductive projection 406 end contacts with first group of interconnecting area gone between in lead-in wire 402.Perform reflux technique, solder ball 405 is melted and forms solder 405, the first electronic component 420 is fixed on lead frame 410.Then, the second electronic component 430 is placed on lead frame 410.Again perform reflux technique, utilize solder 407 to be fixed on by second electronic component 430 on the table top 404 of second group of lead-in wire of lead frame 410, as shown in Figure 4 b.Then, encapsulating compound 440 (such as epoxy resin) is adopted to encapsulate lead frame 410, electronic component 420,430, as illustrated in fig. 4 c.Such as when not using mask, adopting optionally etchant, removing substrate 401 relative to lead-in wire 402 and encapsulating compound 403, thus form the second surface of exposed leads 402, as shown in figure 4d, thus form package assembling 400.
Compared with the method for the first embodiment, according to the step of filling encapsulating compound in the groove that the method for the 3rd embodiment eliminates between lead-in wire 402, while encapsulating compound 440 encapsulates lead frame and electronic component, be filled with the groove between lead-in wire 402, further simplify packaging technology.And because disposable encapsulating compound is shaping, there is the reliability of improvement.
Fig. 5 a to 5e illustrates the sectional view of a part of step of the 4th embodiment of the method for multilayer encapsulation assembly constructed in accordance.According in the method for the 4th embodiment, first on substrate 501, form lead-in wire 502 according to the step shown in Fig. 2 a to 2c.The first surface of lead-in wire 502 is relative with substrate 501, and second surface contacts with substrate 501.The first encapsulating compound 503 (such as epoxy resin) is filled with in groove between lead-in wire 502.
Be with the first embodiment difference, continue to perform the step shown in Fig. 5 a to 5e according to the method for the 4th embodiment.
By known plating or depositing operation, the surface of semiconductor structure is forming conductor layer.Shikishima plating process is such as be selected from the one in plating and chemical plating.Depositing operation is such as be selected from the one in electron beam evaporation (EBM), chemical vapour deposition (CVD) (CVD), ald (ALD), sputtering.
Such as adopt the first mask comprising the pattern that reroutes, be patterned into the layer that reroutes (RDL) 508 by etched conductors layer, as shown in Figure 5 a.In etching, etchant optionally removes the expose portion of conductor layer relative to the lead-in wire 502 of lower floor and the first encapsulating compound 503.Remove the first mask after the etching.The layer 508 that reroutes comprises many strip conductors line of the top surface of contact lead-wire 502, makes conductive path can horizontal expansion.
Then, such as, adopt the second mask, block whole first surfaces of a part of conductor lines of the layer 508 that reroutes, and block the first surface at least partially of another part conductor lines being positioned at the peripheral layer 508 that reroutes of this part lead-in wire.The metal material that the Metal Phase gone between by exposed surface plating and the composition of another part conductor lines at the described layer 508 that reroutes is same, forms table top 504, as shown in Figure 5 b.As a result, the layer 508 that reroutes of first group of wire contacts in lead-in wire 502 does not form table top, the layer 508 that reroutes of second group of wire contacts forms table top.Remove the second mask after plating, thus on substrate 501, form the lead frame 510 comprising two groups of lead-in wires 502.
In lead frame 510, the first surface of lead-in wire 502 is placed upward.The first surface of first group of lead-in wire in lead-in wire 502 directly exposes, for providing interconnecting area.The first surface of second group of lead-in wire in lead-in wire 502 forms table top 504, and this table top 504 is for providing interconnecting area.
First electronic component 520 is placed on lead frame 510.The internal circuit of the first electronic component 520 is electrically connected to conductive projection 506 via conductive channel etc.The solder ball 505 being attached to conductive projection 506 end contacts with a part of conductor lines rerouted in layer 508, thus with in lead-in wire 502 first group go between and be electrically connected.Perform reflux technique, solder ball 505 is melted and forms solder 505, the first electronic component 520 is fixed on lead frame 510.Then, the second electronic component 530 is placed on lead frame 510.Again perform reflux technique, utilize solder 507 to be fixed on table top 504 by the second electronic component 530, as shown in Figure 5 c.Then, encapsulating compound 540 (such as epoxy resin) is adopted to encapsulate lead frame 510, electronic component 520,530, as shown in Figure 5 c.Such as when not using mask, adopting optionally etchant, removing substrate 501 relative to lead-in wire 502 and encapsulating compound 503, thus form the second surface of exposed leads 502, as fig 5d, thus form package assembling 500.
Compared with the method for the first embodiment, the method according to the 4th embodiment is provided with the layer 508 that reroutes above lead frame 510.The layer 508 that reroutes can to allow on chip relatively far apart and need again the electrode terminal be connected to couple together, thus without the need to being connected in chip exterior, reduces external disturbance.And when last layer electronic component needs to be connected with lower one deck chip, also realize by the layer 508 that reroutes.One end of such as, inductance in Switching Power Supply needs to hold with LX to be connected, then by 508 layers, layer realization of rerouting.
In each embodiment of the above-mentioned method according to manufacture multilayer encapsulation assembly of the present invention, the first surface of lead-in wire is relative with substrate, second surface and substrate contacts.In the manufacture process of package assembling, the first surface of lead-in wire is placed all the time upward, thus without the need to overturning semiconductor structure.
In packaging technology, substrate keeps complete and does not etch and run through, and step to the last just etches removal.The mechanically supportive of substrate almost in whole encapsulation process is better, is conducive to the quality improving encapsulation.Even if because the thickness of substrate reduces, enough mechanical support effects also can be provided, is therefore conducive to the miniaturization of package assembling.
In final package assembling, the first surface of lead-in wire provides the interconnecting area with the electronic component of encapsulating structure inside, second surface to provide the contact zone with external circuit (such as printed circuit board (PCB), i.e. PCB).
Due in the above-mentioned methods without the need to overturning semiconductor structure, therefore, effectively can improve the output of encapsulation, reducing packaging cost.Further, the mechanically supportive of substrate almost in whole encapsulation process is better, is conducive to the quality improving encapsulation.
Should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
According to embodiments of the invention as described above, these embodiments do not have all details of detailed descriptionthe, do not limit the specific embodiment that this invention is only described yet.Obviously, according to above description, can make many modifications and variations.This specification is chosen and is specifically described these embodiments, is to explain principle of the present invention and practical application better, thus makes art technical staff that the present invention and the amendment on basis of the present invention can be utilized well to use.The present invention is only subject to the restriction of claims and four corner and equivalent.
Claims (15)
1. a method for manufacturing and encapsulation assembly, comprising:
Substrate forms lead frame, and described lead frame comprises a plurality of leads that first surface exposes;
Lead frame is installed the electronic component of many levels, and the first surface that the electronic component of at least one aspect and at least one group in described a plurality of leads are gone between is electrically connected; And
Remove substrate at least partially, the second surface relative with first surface of described a plurality of leads is exposed and connects for outside.
2. method according to claim 1, the step wherein forming lead frame comprises:
Base plate for packaging forms a plurality of leads; And
At least another group lead-in wire in described a plurality of leads forms table top, and the surface of described table top is higher than described first surface, and the difference group in described at least another group lead-in wire goes between, the apparent height of the upper table top formed is different,
Wherein, in the step of electronic component of installing many levels, at least another organizes the first surface gone between and is electrically connected the electronic component of at least another aspect with described in described a plurality of leads.
3. method according to claim 2, is separated by groove between wherein said a plurality of leads, is being formed between the step of a plurality of leads and the step forming table top, is also comprising and adopt encapsulating compound filling groove.
4. method according to claim 2, the step wherein forming a plurality of leads comprises:
Substrate forms metal level; And
Via the mask comprising lead pattern, by etching, metal layer pattern is changed into described a plurality of leads.
5. method according to claim 2, the step wherein forming a plurality of leads comprises:
Via the mask comprising lead-in wire complementary patterns, form described a plurality of leads by the exposed surface coating metal material at substrate.
6. method according to claim 2, the step wherein forming a plurality of leads comprises:
Substrate is formed the mask comprising lead-in wire complementary patterns; And
By etching, the top layer of substrate is patterned to described a plurality of leads.
7. method according to claim 2, the step wherein forming a plurality of leads comprises:
By punching press, the top layer of substrate is patterned to described a plurality of leads.
8. method according to claim 2, the step of wherein installing the electronic component of many levels on lead frame comprises:
From the first level of contiguous lead frame, aspect installing electronic elements one by one; And
After the electronic component installing structure at all levels, encapsulating compound is adopted to cover lead frame and electronic component at least partly,
Wherein, the electronic component of the first level is electrically connected with one group of first surface gone between during described at least one group goes between, and the electronic component of aspect is electrically connected with described at least another table top organizing the lead-in wire of the respective sets in going between subsequently.
9. method according to claim 2, the step of wherein installing the electronic component of many levels on lead frame comprises:
From the first level of contiguous lead frame, aspect installing electronic elements and employing encapsulating compound cover the electronic component of corresponding aspect at least partly one by one,
Wherein, after the electronic component of an installation aspect and before the electronic component of the next aspect of installation, encapsulating compound is adopted to cover lead-in wire and the electronic component of a described aspect at least partly,
The electronic component of the first level is electrically connected with one group of first surface gone between during described at least one group goes between, and the electronic component of aspect is electrically connected with described at least another table top organizing the lead-in wire of the respective sets in going between subsequently.
10. method according to claim 9, wherein before the electronic component installing described next aspect, also comprises the encapsulating compound of a smooth described aspect to expose the first surface of the lead-in wire of described next aspect.
11. methods according to claim 2, wherein, in the step of electronic component of installing many levels, the described at least one group of first surface gone between in the electronic component of at least one aspect described and described a plurality of leads is formed welding flux interconnected, and the electronic component of described at least another aspect and the surface of described table top are formed welding flux interconnected.
12. methods according to claim 3, adopting between the step of encapsulating compound filling groove and the step forming table top, also comprise formation to reroute layer, wherein, the described layer that reroutes comprises many strip conductors line, described many strip conductors line horizontal expansion and comprise each other relative first surface and second surface, the first surface of wherein said many strip conductors line contacts the first surface of described a plurality of leads.
13. methods according to claim 12, wherein, in the step of electronic component of installing many levels, the second surface of the electronic component of at least one aspect described and at least one group of conductor lines of described many strip conductors line is formed welding flux interconnected, and the electronic component of described at least another aspect and the surface of described table top are formed welding flux interconnected.
14. methods according to claim 1, lead frame are installed between the step of the electronic component of many levels and the step removing substrate, also comprise: in the surperficial additional heat sink of encapsulating compound.
15. methods according to claim 14, before the surperficial additional heat sink of encapsulating compound, also comprise: by grinding smooth envelope encapsulating compound and reducing the thickness of the top layer of encapsulating compound.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410603661.3A CN104409369B (en) | 2014-10-31 | 2014-10-31 | Package assembling manufacturing method |
| CN201910107499.9A CN109817530B (en) | 2014-10-31 | 2014-10-31 | Packaging assembly manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410603661.3A CN104409369B (en) | 2014-10-31 | 2014-10-31 | Package assembling manufacturing method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910107499.9A Division CN109817530B (en) | 2014-10-31 | 2014-10-31 | Packaging assembly manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104409369A true CN104409369A (en) | 2015-03-11 |
| CN104409369B CN104409369B (en) | 2019-05-07 |
Family
ID=52646985
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910107499.9A Active CN109817530B (en) | 2014-10-31 | 2014-10-31 | Packaging assembly manufacturing method |
| CN201410603661.3A Active CN104409369B (en) | 2014-10-31 | 2014-10-31 | Package assembling manufacturing method |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910107499.9A Active CN109817530B (en) | 2014-10-31 | 2014-10-31 | Packaging assembly manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN109817530B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9595453B2 (en) | 2015-06-11 | 2017-03-14 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Chip package method and package assembly |
| US10333019B2 (en) | 2016-05-27 | 2019-06-25 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Package structure of light emitter and light sensor with light-blocking layer and method for manufacturing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725096B (en) * | 2020-03-27 | 2024-06-25 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100033247A (en) * | 2008-09-19 | 2010-03-29 | 엘지이노텍 주식회사 | Structure for multi-row leadless lead frame and semiconductor package thereof and manufacture method thereof |
| KR20100034157A (en) * | 2008-09-23 | 2010-04-01 | 엘지이노텍 주식회사 | Structure for multi-row leadless lead frame and semiconductor package thereof and manufacture method thereof |
| CN103633058A (en) * | 2013-12-12 | 2014-03-12 | 矽力杰半导体技术(杭州)有限公司 | Packaging assembly and manufacturing method thereof |
| CN103633056A (en) * | 2013-12-06 | 2014-03-12 | 矽力杰半导体技术(杭州)有限公司 | Lead frame, packaging subassembly and manufacturing method for lead frame and packaging subassembly |
| CN103730444A (en) * | 2014-01-20 | 2014-04-16 | 矽力杰半导体技术(杭州)有限公司 | Packaging assembly and manufacture method thereof |
-
2014
- 2014-10-31 CN CN201910107499.9A patent/CN109817530B/en active Active
- 2014-10-31 CN CN201410603661.3A patent/CN104409369B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100033247A (en) * | 2008-09-19 | 2010-03-29 | 엘지이노텍 주식회사 | Structure for multi-row leadless lead frame and semiconductor package thereof and manufacture method thereof |
| KR20100034157A (en) * | 2008-09-23 | 2010-04-01 | 엘지이노텍 주식회사 | Structure for multi-row leadless lead frame and semiconductor package thereof and manufacture method thereof |
| CN103633056A (en) * | 2013-12-06 | 2014-03-12 | 矽力杰半导体技术(杭州)有限公司 | Lead frame, packaging subassembly and manufacturing method for lead frame and packaging subassembly |
| CN103633058A (en) * | 2013-12-12 | 2014-03-12 | 矽力杰半导体技术(杭州)有限公司 | Packaging assembly and manufacturing method thereof |
| CN103730444A (en) * | 2014-01-20 | 2014-04-16 | 矽力杰半导体技术(杭州)有限公司 | Packaging assembly and manufacture method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9595453B2 (en) | 2015-06-11 | 2017-03-14 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Chip package method and package assembly |
| US10333019B2 (en) | 2016-05-27 | 2019-06-25 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Package structure of light emitter and light sensor with light-blocking layer and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109817530B (en) | 2020-10-30 |
| CN104409369B (en) | 2019-05-07 |
| CN109817530A (en) | 2019-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100914977B1 (en) | Method for fabricating stack package | |
| KR101653856B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN103633056B (en) | Lead frame, package assembling and its manufacture method | |
| CN103730444B (en) | Package assembling and its manufacture method | |
| US7834469B2 (en) | Stacked type chip package structure including a chip package and a chip that are stacked on a lead frame | |
| JP2009010311A (en) | Through-silicon via stack package and manufacturing method therefor | |
| CN104269385B (en) | Package assembling and its manufacture method | |
| TWI643303B (en) | Electronic device and manufacturing method of electronic device | |
| CN103700639A (en) | Packaging assembly and manufacturing method thereof | |
| JP5358089B2 (en) | Semiconductor device | |
| US9053968B2 (en) | Semiconductor package structure and manufacturing method thereof | |
| US9508677B2 (en) | Chip package assembly and manufacturing method thereof | |
| KR100914987B1 (en) | Molded reconfigured wafer and stack package using the same | |
| CN104409369A (en) | Method for manufacturing packaging assembly | |
| KR101538540B1 (en) | Semiconductor device and fabricating method thereof | |
| JP2010087403A (en) | Semiconductor device | |
| KR100772103B1 (en) | Stack type package and manufacture method thereof | |
| CN105118817B (en) | A kind of encapsulating structure and its method for packing of inexpensive silicon substrate module | |
| US20110006412A1 (en) | Semiconductor chip package and method for manufacturing thereof and stack package using the same | |
| US9589878B2 (en) | Semiconductor package | |
| KR20110012670A (en) | Semiconductor package and method for fabricating thereof | |
| KR20150098936A (en) | Semiconductor package structure and method therefor | |
| KR102091619B1 (en) | Semiconductor package | |
| KR20100020769A (en) | Semiconductor package | |
| KR20090097725A (en) | Substrate of semiconductor package and semiconductor package using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |