CN109817530B

CN109817530B - Packaging assembly manufacturing method

Info

Publication number: CN109817530B
Application number: CN201910107499.9A
Authority: CN
Inventors: 谭小春; 申屠军立; 叶佳明
Original assignee: Hangzhou Silergy Semiconductor Technology Ltd
Current assignee: Hangzhou Silergy Semiconductor Technology Ltd
Priority date: 2014-10-31
Filing date: 2014-10-31
Publication date: 2020-10-30
Anticipated expiration: 2034-10-31
Also published as: CN104409369B; CN109817530A; CN104409369A

Abstract

Disclosed is a method of manufacturing a package assembly, comprising: forming a lead frame on a substrate, the lead frame including a plurality of leads with a first surface exposed; mounting a plurality of levels of electronic components on a lead frame such that at least one level of electronic components is electrically connected to a first surface of at least one set of leads of the plurality of leads; and removing at least a portion of the substrate such that a second surface of the plurality of leads opposite the first surface is exposed for external connection. The method does not need to turn over the semiconductor structure in the manufacturing process, and can improve the yield of the packaging assembly, reduce the cost and improve the packaging quality.

Description

Packaging assembly manufacturing method

Technical Field

The present invention relates to semiconductor packages, and in particular to package assembly manufacturing methods.

Background

With the increasing demand for miniaturization, weight reduction and multi-functionalization of electronic components, the demand for semiconductor packaging density is increasing to achieve the effect of reducing the package size. Therefore, package assemblies using a leadframe and containing a plurality of semiconductor dies have become a new hotspot. In such package assemblies, the configuration of the plurality of semiconductor dies and the method of connecting them has a critical impact on the size and performance of the package assembly.

Stacked multi-layer package assemblies have been proposed in which multiple semiconductor dies are stacked on the same leadframe. The semiconductor die located at the lowermost layer may be directly fixed to the lead frame by solder. The semiconductor die on the upper layer may be secured to the top surface of the semiconductor die on the lower layer by an adhesive layer. Then, the semiconductor die of the upper layer is electrically connected to the lead frame through bonding wires. The semiconductor die integrated in a package assembly may be not only integrated circuit chips (e.g., power device chips and control chips for switching power supplies, etc.) but also discrete components (e.g., power plants, capacitors, resistors, etc.).

The stacked multi-layer package assembly can reduce the chip footprint relative to the planar package assembly, thereby reducing package size while having shorter delay times and less noise. Accordingly, processes for forming multi-layer package assemblies are of increasing interest.

However, stacking multiple layers of semiconductor dies on a lead frame complicates the packaging process, such as requiring the lead frame to be flipped during the packaging process, thereby reducing the yield of the package assembly, resulting in increased costs. Furthermore, in the packaging process, a partial area of the substrate carrying the lead frame is etched through. The thickness of the substrate must be large enough to provide the required mechanical support. As a result, the size of the package assembly is difficult to miniaturize.

Therefore, it is desirable to further optimize the manufacturing method of the package assembly to reduce process complexity.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a method for manufacturing a package assembly, so as to solve the problem of cost increase due to complicated manufacturing process of a multi-layer package assembly.

According to the present invention, there is provided a method of manufacturing a package assembly, comprising: forming a lead frame on a substrate, the lead frame including a plurality of leads with a first surface exposed; mounting a plurality of levels of electronic components on a lead frame such that at least one level of electronic components is electrically connected to a first surface of at least one set of leads of the plurality of leads; and removing at least a portion of the substrate such that a second surface of the plurality of leads opposite the first surface is exposed for external connection.

Preferably, in the method, the step of forming the lead frame comprises: forming a plurality of leads on a package substrate; and forming a mesa on at least another group of the plurality of leads, a surface of the mesa being higher than the first surface, and surfaces of mesas formed on different groups of the at least another group of leads being different in height, wherein in the step of mounting the electronic components of the plurality of layers, the electronic components of at least another layer are electrically connected to the first surface of the at least another group of the plurality of leads.

Preferably, in the method, the plurality of leads are separated by a trench, and the step of filling the trench with an encapsulant is further included between the step of forming the plurality of leads and the step of forming the mesa.

Preferably, in the method, the step of forming the plurality of leads includes: forming a metal layer on a substrate; and patterning the metal layer into the plurality of leads by etching through a mask including a lead pattern.

Preferably, in the method, the step of forming the plurality of leads includes: the plurality of leads are formed by plating a metal material on the exposed surface of the substrate via a mask including a complementary pattern of leads.

Preferably, in the method, the step of forming the plurality of leads includes: forming a mask including a lead complementary pattern on a substrate; and patterning a surface layer of the substrate into the plurality of leads by etching.

Preferably, in the method, the step of forming the plurality of leads includes: the surface layer of the substrate is patterned into the plurality of leads by stamping.

Preferably, in the method, the step of mounting the electronic components of the plurality of layers on the lead frame includes: mounting electronic components layer by layer starting from a first layer adjacent to the lead frame; and after mounting all the layers of electronic components, at least partially covering the lead frame and the electronic components with an encapsulant, wherein the electronic components of a first layer are electrically connected with the first surface of one group of leads in the at least one group of leads, and the electronic components of a subsequent layer are electrically connected with the mesas of the corresponding group of leads in the at least one other group of leads.

Preferably, in the method, the step of mounting the electronic components of the plurality of layers on the lead frame includes: and mounting electronic components layer by layer starting from a first layer adjacent to the lead frame and at least partially covering the electronic components of the corresponding layer with an encapsulant, wherein after mounting the electronic components of one layer and before mounting the electronic components of the next layer, the leads and the electronic components of the one layer are at least partially covered with the encapsulant, the electronic components of the first layer are electrically connected with the first surface of one group of leads in the at least one group of leads, and the electronic components of the subsequent layer are electrically connected with the mesas of the corresponding group of leads in the at least one other group of leads.

Preferably, in the method, before mounting the electronic component of the next layer, the step of flattening the encapsulant of the one layer to expose the first surface of the lead of the next layer is further included.

Preferably, in the method, in the step of mounting a plurality of levels of electronic components, the at least one level of electronic components forms solder interconnections with the first surface of the at least one set of leads of the plurality of leads, and the at least another level of electronic components forms solder interconnections with the surface of the mesa.

Preferably, between the step of filling the trench with the encapsulant and the step of forming the mesa, a redistribution layer is further formed, wherein the redistribution layer includes a plurality of conductor lines extending laterally and including a first surface and a second surface opposite to each other, wherein the first surfaces of the plurality of conductor lines contact the first surfaces of the plurality of leads.

Preferably, in the method, in the step of mounting the electronic components of the plurality of levels, the electronic component of the at least one level forms a solder interconnection with the second surface of at least one set of conductor lines of the plurality of conductor lines, and the electronic component of the at least another level forms a solder interconnection with the surface of the mesa.

The method of claim, further comprising, between the step of mounting multiple levels of electronic components on the lead frame and the step of removing the substrate: a heat sink is attached to the surface of the encapsulant.

The method of claim, further comprising, prior to attaching a heat sink to the surface of the encapsulant: the encapsulant is smoothed by grinding and the thickness of the top layer of the encapsulant is reduced.

In the above method of manufacturing a multi-layered package assembly according to the present invention, the first surface of the lead is opposed to the substrate, and the second surface is in contact with the substrate. In the manufacturing process of the packaging assembly, the first surfaces of the leads are always placed upwards, so that the semiconductor structure does not need to be turned over. Furthermore, the substrate provides mechanical support throughout almost the entire packaging process, and is not removed until the lead frame and the electronic component have been encapsulated with the second encapsulant. In the final package assembly, the first surfaces of the leads provide interconnection areas with electronic components inside the package structure, and the second surfaces provide contact areas with external circuitry (e.g., a printed circuit board, i.e., PCB).

Because the semiconductor structure does not need to be turned over in the method, the packaging yield can be effectively improved, and the packaging cost is reduced.

In the packaging process, the substrate remains intact without etching through until the last step. The substrate has better mechanical support in almost the whole packaging process, and is beneficial to improving the packaging quality. Since a sufficient mechanical supporting function can be provided even if the thickness of the substrate is reduced, miniaturization of the package assembly is facilitated.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1a to 1g show cross-sectional views of various steps of a method of manufacturing a multi-layer package assembly according to the prior art;

fig. 2a to 2g show cross-sectional views of various steps of a first embodiment of a method of manufacturing a multi-layer package assembly according to the present invention;

fig. 3a and 3b show cross-sectional views of a part of a step of a second embodiment of a method of manufacturing a multi-layer package assembly according to the present invention;

fig. 4a to 4d show cross-sectional views of a part of a step of a third embodiment of a method of manufacturing a multi-layer package assembly according to the present invention; and

fig. 5a to 5e show cross-sectional views of a part of a step of a fourth embodiment of a method of manufacturing a multi-layer package assembly according to the invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. For simplicity, the package structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing an encapsulation structure, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions. If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

Numerous specific details of the invention, such as package structures, materials, dimensions, processing techniques and techniques, are set forth in the following description in order to provide a more thorough understanding of the disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "electronic component" is not limited to semiconductor dies, but should be understood to refer broadly to packaged objects including semiconductor dies and discrete components (e.g., resistors, capacitors, inductors, diodes, transistors), and the like.

Fig. 1a to 1g show cross-sectional views of various steps of a method of manufacturing a multi-layer package assembly according to the prior art. The method includes forming a lead frame on a substrate and stacking a plurality of levels of electronic components on the lead frame.

The method starts, for example, with a stack comprising a substrate 101 (e.g. an iron-nickel alloy) and a metal layer (e.g. Cu) thereon, wherein the substrate 101 acts as a support layer and will eventually be partially removed as a sacrificial layer. The metal layer is patterned into strip-shaped leads 102, for example by etching it, using a first mask, as shown in fig. 1 a. In the etching, the etchant selectively removes the exposed portion of the metal layer with respect to the underlying substrate 101. The first mask is removed after etching.

The first surface of the lead 102 formed in the above step is opposite to the substrate 101, and the second surface is in contact with the substrate 101.

The leads 102 and the exposed surface of the substrate 101 are then covered with a first encapsulant 103, e.g. epoxy, as shown in fig. 1 b. The encapsulant 103 has a thickness at least sufficient to fill the trenches between adjacent leads 102. The encapsulant 103 is planarized, for example by grinding, so that the first surface of the leads 102 is again exposed, as shown in fig. 1 c. The substrate 101 is removed in the mounting area of the substrate 101 with respect to the leads 102 and the encapsulant 103, for example using a second mask using a selective etchant, thereby forming openings exposing a second surface of the leads 102, as shown in fig. 1 d. The first surface and the second surface are opposite to each other. The unetched portions of the substrate 101 provide mechanical support during the etching step. After exposing the second surfaces of the leads 102, the semiconductor structure is flipped upside down. For example, a third mask is used to block all of the second surface of a portion of the leads and to block at least a portion of the second surface of another portion of the leads that is located at the periphery of the portion of the leads. The mesas 104 are formed by plating (e.g., electroplating, electroless plating, etc.) the same metal material as the metal making up the leads on the exposed surfaces of the other portions of the leads 102, as shown in fig. 1 e. The portion of the leads 102 that is shielded serves as a first set of leads and the other portion of the leads 102 that forms the mesa serves as a second set of leads. The third mask is removed after plating, thereby forming a lead frame 110 including two sets of leads 102 on the substrate 101.

In the lead frame 110, the second surface of the lead 102 is placed upward. The second surface of the first group of leads in leads 102 is directly exposed for providing an interconnect region. Mesas 104 are formed on a second surface of a second set of the leads 102, the mesas 104 for providing interconnect regions.

A first electronic component 120 is placed on the lead frame 110. The internal circuit of the first electronic component 120 is electrically connected to the conductive bump 106 via a conductive via or the like. Solder balls 105 attached to the ends of conductive bumps 106 contact the interconnect regions of a first set of leads in leads 102. A reflow process is performed such that the solder balls 105 melt to form the solder 105, securing the first electronic component 120 to the leadframe 110. Then, the second electronic component 130 is placed on the lead frame 110. The reflow process is again performed and the second electronic component 130 is secured to the second set of leads of the lead frame 110 using solder 107, as shown in fig. 1 g. The lead frame 110, the

electronic components

120, 130 are then encapsulated with a second encapsulant 140 (e.g., epoxy) to form the package assembly 100.

In the above-described method of manufacturing a multi-layered package assembly according to the related art, the first surface of the lead 102 is opposed to the substrate 101, and the second surface is in contact with the substrate 101. The first surface of the leads 102 is initially placed facing upward. In the step shown in fig. 1e, the semiconductor structure is flipped. This is because the etched substrate 101 has insufficient mechanical strength to support the lead frame 110 in a subsequent process. The leads 102 are flipped over with their first surfaces facing down, thereby providing mechanical support with the first surfaces of the leads 102 themselves in a subsequent step.

In the final package assembly 100, the leads 102 are placed with their first surfaces facing down for providing contact areas with external circuitry and with their second surfaces facing up for providing interconnection areas with electronic components inside the package structure.

Since the semiconductor structure needs to be flipped in the above method, the operation process is complicated, and the yield of packaged devices is not improved, so that the packaging cost cannot be effectively reduced.

Fig. 2a to 2g show cross-sectional views of various steps of a first embodiment of a method of manufacturing a multi-layer package assembly according to the present invention. The method includes forming a lead frame on a substrate and stacking a plurality of levels of electronic components on the lead frame.

The method starts, for example, with a stack comprising a substrate 201 (e.g. an iron-nickel alloy) and a metal layer (e.g. Cu) thereon, wherein the substrate 201 acts as a support layer and will eventually be partially removed as a sacrificial layer. The metal layer is patterned into strip-shaped leads 202 by etching it, for example using a first mask comprising a pattern of leads, as shown in fig. 2 a. In the etching, the etchant selectively removes the exposed portions of the metal layer with respect to the underlying substrate 201. The first mask is removed after etching.

The first surface of the lead 202 formed in the above steps is opposite to the substrate 202, and the second surface is in contact with the substrate 202.

The exposed surfaces of the leads 202 and substrate 201 are then covered with a first encapsulant 203 (e.g., epoxy), as shown in fig. 2 b. The encapsulant 203 has a thickness at least sufficient to fill the trenches between adjacent leads 202. The encapsulant 203 is planarized, for example by grinding, so that the first surface of the leads 202 is again exposed, as shown in fig. 2 c. For example, a second mask is used to block all of the first surface of a portion of the leads and to block at least a portion of the first surface of another portion of the leads that is located at the periphery of the portion of the leads. The mesas 204 are formed by plating the exposed surfaces of the other portion of the leads 202 with the same metallic material as the metal making up the leads, as shown in fig. 2 d. The portion of the leads 202 that is masked serves as a first set of leads and the other portion of the leads 202 that forms the mesa serves as a second set of leads. The second mask is removed after plating, thereby forming a lead frame 210 including two sets of leads 202 on the substrate 201.

In the step of forming the mesa 204, since it is difficult to precisely align the opening of the second mask with the wire 202, the area of the second mask is generally slightly smaller than the cross-sectional area (cross-sectional area in a direction parallel to the opening) of the wire 202. As a result, the surface area of mesa 204 is slightly smaller than the surface area of wire 202 to ensure that mesa 204 is formed completely on the surface of wire 202 and to avoid forming mesa 204 to connect the two connected wires 202.

In the lead frame 210, the first surface of the lead 202 is placed upward. A first surface of a first set of the leads 202 is directly exposed for providing an interconnect region. Mesas 204 are formed on a first surface of a second set of the leads 202, the mesas 204 providing an interconnect region.

A first electronic component 220 is placed on the lead frame 210. The internal circuit of the first electronic component 220 is electrically connected to the conductive bump 206 via a conductive via or the like. Solder balls 205 attached to the ends of conductive bumps 206 contact the interconnect regions of a first set of leads in leads 202. A reflow process is performed such that the solder balls 205 melt to form the solder 205, securing the first electronic component 220 to the lead frame 210. Then, the second electronic component 230 is placed on the lead frame 210. The reflow process is again performed and the second electronic component 230 is secured to the mesas 204 of the second set of leads of the leadframe 210 using solder 207, as shown in fig. 2 e. The lead frame 210, the

electronic components

220, 230 are then encapsulated with a second encapsulant 240, such as epoxy, as shown in fig. 2 f. The substrate 201 is removed with respect to the leads 202 and the encapsulant 203 using a selective etchant, for example, without the use of a mask, to form a second surface exposing the leads 202, as shown in fig. 2g, to form the package assembly 200.

The first electronic component 220 is, for example, a chip including a power device, such as a chip including a main power transistor in a power stage circuit of a switching power supply, and the chip may further include a control circuit of the switching power supply and may also include a synchronous rectifier of the switching power supply. The second electronic component 230 may be a discrete component such as a capacitor or a resistor, for example, including an inductor in the switching power supply.

In a preferred embodiment, after the second encapsulant 240 is formed in the step shown in fig. 2f, a heat sink may be attached to the surface of the second encapsulant 240. The second encapsulant 240 is planarized, for example, by grinding, and the thickness of the top layer of the second encapsulant 240 is reduced to reduce the package volume and improve heat dissipation efficiency. The process shown in fig. 2g then continues with the removal of the substrate 210.

In an alternative embodiment, the step of forming the leads 202 on the substrate 201 begins with the substrate 201 (e.g., an iron-nickel alloy) with the substrate 201 acting as a support layer and eventually being partially removed as a sacrificial layer. For example, a first mask is used which contains a pattern complementary to the leads, i.e. the openings of the mask correspond to the pattern of the leads. The first mask shields a portion of the surface of the substrate 201. Leads 202 are formed in a strip shape by plating a metal material (e.g., Cu) on the exposed surface of the substrate 201, as shown in fig. 2 a. The first mask is removed after plating. Then, the steps of fig. 2b to 2g are continued to form the package assembly 200.

In another alternative embodiment, the step of forming the leads 202 on the substrate 201 begins with the substrate 201 (e.g., an iron-nickel alloy). The leads 202 are formed on the surface of the substrate 201, for example by a half-etching and/or stamping process, as shown in fig. 2 a. Optionally, a trench between adjacent leads 202 is filled with encapsulant 203. Then, the steps of fig. 2d to 2g are continued to form the package assembly 200.

Fig. 3a and 3b show cross-sectional views of a part of a step of a second embodiment of a method of manufacturing a multi-layer package assembly according to the present invention. In the method according to the second embodiment, the lead frame 310 is first formed in accordance with the steps shown in fig. 2a to 2 d. A lead frame 310 is positioned on the substrate 301 and includes a first set of leads that do not form a mesa and a second set of leads that form the mesa 304. The surface of the first set of leads directly provides the interconnect region and the mesa 304 of the second set of leads provides the interconnect region.

The difference with the first embodiment is that the method according to the second embodiment continues with the steps shown in fig. 3a and 3 b.

A first electronic component 320 is placed on the lead frame 310. The internal circuit of the first electronic component 320 is electrically connected to the conductive bump 306 via a conductive via or the like. Solder balls 305 attached to the ends of the conductive bumps 306 contact the interconnect regions of a first set of the leads 302. A reflow process is performed such that the solder balls 305 melt to form solder 305, securing the first electronic component 320 to the lead frame 310. The lead frame 310 and the electronic component 320 are then encapsulated with a second encapsulant 340 (e.g., epoxy). The second encapsulant 340 is planarized, such as by grinding, to expose mesas 304 of the second set of leads 302. Then, the second electronic component 330 is placed on the second encapsulant 340. The reflow process is again performed and the second electronic component 330 is secured to the mesas 304 of the second set of leads of the leadframe 310 using solder 307. The lead frame 310, the

electronic components

320, 330 are then encapsulated with a third encapsulant material 350, such as epoxy, as shown in fig. 3 a. The substrate 301 is removed with respect to the leads 302 and the encapsulant 303 using a selective etchant, for example without using a mask, to form a second surface exposing the leads 302, as shown in fig. 3b, to form the package assembly 300.

Fig. 4a to 4d show cross-sectional views of a part of steps of a third embodiment of a method of manufacturing a multi-layer package assembly according to the present invention. In the method according to the third embodiment, the leads 402 are first formed on the substrate 401 according to the steps shown in fig. 2 a. The first surface of the lead 402 is opposite to the substrate 401, and the second surface is in contact with the substrate 401.

The difference from the first embodiment is that the method according to the third embodiment continues with the steps shown in fig. 4a to 4 d.

Then, for example, a first mask is used to block all of the first surface of a portion of the leads and to block at least a portion of the first surface of another portion of the leads that is located at the periphery of the portion of the leads. The mesa 404 is formed by plating the exposed surface of the other portion of the lead 402 with the same metallic material as the metal making up the lead, as shown in fig. 4 a. The portion of the leads 402 that is masked serves as a first set of leads and the other portion of the leads 402 that forms the mesa serves as a second set of leads. The first mask is removed after plating, thereby forming a lead frame 410 including two sets of leads 402 on the substrate 401.

In the lead frame 410, the first surface of the lead 402 is placed upward. A first surface of a first set of the leads 402 is directly exposed for providing an interconnect region. A mesa 404 is formed on a first surface of a second set of the leads 402, the mesa 404 for providing an interconnect region.

A first electronic component 420 is placed on the lead frame 410. The internal circuit of the first electronic component 420 is electrically connected to the conductive bump 406 via a conductive via or the like. Solder balls 405 attached to the ends of conductive bumps 406 contact the interconnect regions of a first set of leads in leads 402. A reflow process is performed such that the solder balls 405 melt to form solder 405, securing the first electronic component 420 to the leadframe 410. Then, the second electronic component 430 is placed on the lead frame 410. The reflow process is again performed and the second electronic component 430 is secured to the mesas 404 of the second set of leads of the leadframe 410 using solder 407, as shown in fig. 4 b. The lead frame 410, the

electronic components

420, 430 are then encapsulated with an encapsulant 440 (e.g., epoxy), as shown in fig. 4 c. The substrate 401 is removed with respect to the leads 402 and the encapsulant 403 using a selective etchant, for example without using a mask, to form a second surface exposing the leads 402, as shown in fig. 4d, to form the package assembly 400.

Compared to the method of the first embodiment, the method according to the third embodiment eliminates the step of filling the encapsulant in the grooves between the leads 402, fills the grooves between the leads 402 while the encapsulant 440 encapsulates the lead frame and the electronic component, and further simplifies the encapsulation process. And has improved reliability due to the molding of the disposable encapsulating material.

Fig. 5a to 5e show cross-sectional views of a part of steps of a fourth embodiment of a method of manufacturing a multi-layer package assembly according to the invention. In the method according to the fourth embodiment, the leads 502 are first formed on the substrate 501 in accordance with the steps shown in fig. 2a to 2 c. The first surface of the lead 502 is opposite to the substrate 501, and the second surface is in contact with the substrate 501. The trenches between the leads 502 are filled with a first encapsulant 503 (e.g., epoxy).

The difference from the first embodiment is that the method according to the fourth embodiment continues with the steps shown in fig. 5a to 5 e.

A conductor layer is formed on the surface of the semiconductor structure by known plating or deposition processes. The plating process is, for example, one selected from electroplating and electroless plating. The deposition process is, for example, one selected from electron beam Evaporation (EBM), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), sputtering.

The conductor layer is patterned into a redistribution layer (RDL)508 by etching it, for example using a first mask containing a redistribution pattern, as shown in fig. 5 a. In the etching, the etchant selectively removes the exposed portion of the conductor layer with respect to the underlying lead 502 and the first encapsulant 503. The first mask is removed after etching. The redistribution layer 508 includes a plurality of conductor lines that contact the top surface of the leads 502 so that the conductive paths may extend laterally.

Then, for example, a second mask is used to block all of the first surface of a part of the conductor lines of the redistribution layer 508, and to block at least a part of the first surface of another part of the conductor lines of the redistribution layer 508 located at the periphery of the part of the leads. The mesas 504 are formed by plating the exposed surfaces of the other portions of the conductor lines of the redistribution layer 508 with the same metal material as the metal constituting the leads, as shown in fig. 5 b. As a result, no mesa is formed on the redistribution layer 508 of the first set of lead contacts in the leads 502, and a mesa is formed on the redistribution layer 508 of the second set of lead contacts. The second mask is removed after plating, thereby forming a lead frame 510 including two sets of leads 502 on the substrate 501.

In the lead frame 510, the first surface of the lead 502 is placed facing upward. A first surface of a first set of the leads 502 is directly exposed for providing an interconnect region. A mesa 504 is formed on a first surface of a second set of the leads 502, the mesa 504 for providing an interconnect region.

A first electronic component 520 is placed on the lead frame 510. The internal circuit of the first electronic component 520 is electrically connected to the conductive bump 506 via a conductive via or the like. Solder balls 505 attached to the ends of conductive bumps 506 contact a portion of the conductor lines in redistribution layer 508 and are thus electrically connected to a first set of leads in leads 502. A reflow process is performed such that the solder balls 505 melt to form solder 505, securing the first electronic component 520 to the lead frame 510. Then, a second electronic component 530 is placed on the lead frame 510. The reflow process is again performed and the second electronic component 530 is fixed on the mesa 504 with solder 507, as shown in fig. 5 c. The lead frame 510, the

electronic components

520, 530 are then encapsulated with an encapsulant 540 (e.g., epoxy), as shown in fig. 5 c. The substrate 501 is removed with respect to the leads 502 and the encapsulant 503 using a selective etchant, for example, without using a mask, to form a second surface exposing the leads 502, as shown in fig. 5d, to form the package assembly 500.

In contrast to the method of the first embodiment, the method according to the fourth embodiment provides a rewiring layer 508 above the lead frame 510. The redistribution layer 508 may allow the electrode terminals that are spaced apart and need to be connected on the chip to be connected, thereby eliminating the need for external connections on the chip and reducing external interference. And the upper layer of electronic components need to be connected to the lower layer of chips, it can also be implemented by the redistribution layer 508. For example, if one end of the inductor in the switching power supply needs to be connected to the LX terminal, it can be realized by the redistribution layer 508 layer.

In the above-described embodiments of the method of manufacturing a multi-layered package assembly according to the present invention, the first surface of the lead is opposite to the substrate, and the second surface is in contact with the substrate. In the manufacturing process of the packaging assembly, the first surfaces of the leads are always placed upwards, so that the semiconductor structure does not need to be turned over.

In the final package assembly, the first surfaces of the leads provide interconnection areas with electronic components inside the package structure, and the second surfaces provide contact areas with external circuitry (e.g., a printed circuit board, i.e., PCB).

Because the semiconductor structure does not need to be turned over in the method, the packaging yield can be effectively improved, and the packaging cost is reduced. In addition, the substrate has better mechanical support property in almost the whole packaging process, and the packaging quality is favorably improved.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method of fabricating a package assembly, comprising:

forming a lead frame on an upper surface of a substrate, the lead frame including a plurality of leads exposed at a first surface;

the leads have at least two different heights to form layers with different heights relative to the upper surface of the substrate;

mounting a plurality of levels of electronic components on a first surface of the leads;

a primary plastic package process step, namely packaging a lead frame and an electronic element by using a packaging material, and filling grooves among all the leads and gaps among the leads and the electronic element to form a sealed package body positioned on the substrate; and

after the step of the plastic packaging process is completed, removing at least a part of the substrate, so that a second surface of the lead opposite to the first surface is exposed for external connection.

2. The method of claim 1, wherein the step of forming a leadframe comprises:

forming a plurality of first-type leads on a first surface of a substrate; and

a mesa is selectively formed on a portion of the first type of lead and the mesa has a different height to form a different level.

3. The method of claim 2, wherein the step of forming a plurality of leads comprises:

forming a metal layer on a substrate; and

the metal layer is patterned into the plurality of leads by etching through a mask including a lead pattern.

4. The method of claim 2, wherein the step of forming a plurality of leads comprises:

the plurality of leads are formed by plating a metal material on the exposed surface of the substrate via a mask including a complementary pattern of leads.

5. The method of claim 2, further comprising the step of:

the substrate provides a mechanical supporting function, and a first type lead is formed on a preset area of the upper surface of the substrate through a plating process;

selectively forming a mesa with a predetermined height in a partial region of the first type lead by a plating process;

mounting electronic components layer by layer starting from a first layer adjacent to the lead frame; and

after the electronic elements on all layers are mounted, a plastic package process is carried out for one time, a lead frame and the electronic elements are coated by adopting a package material, and all grooves formed on the surface of the substrate by the leads and gaps between the leads and the electronic elements are filled to form a sealed package body positioned on the substrate; wherein, in the step of mounting the electronic components of the plurality of layers, the substrate provides a mechanical support function; in the plastic packaging step, the substrate provides a mechanical supporting function and a function of defining a plastic packaging area;

and removing the substrate to expose the second surfaces of the leads outside the packaging body.

6. The method of claim 2, wherein the surface area of the upper surface of the mesa is no greater than the surface area of the lower surface.

7. The method of claim 2, wherein a surface area of a first surface of the first type of leads is no less than a surface area of a lower surface of the mesa on the first type of leads.

8. The method of claim 2, wherein the step of mounting multiple levels of electronic components on the lead frame comprises:

after mounting all layers of electronic elements, covering the lead frame and the electronic elements by using an encapsulating material to fill all grooves formed on the surface of the substrate by the leads to form a sealed packaging body positioned above the substrate, wherein the substrate provides a mechanical supporting function in the step of mounting the electronic elements of the multiple layers; in the plastic packaging step, the substrate provides a mechanical supporting function and a function of defining a plastic packaging area.

9. The method of claim 2, wherein in the step of mounting a plurality of levels of electronic components, the electronic components form solder interconnects with the first surfaces of the first type of leads and with the upper surface of the mesa.

10. The method of claim 1, further comprising, between the step of mounting multiple levels of electronic components on the lead frame and the step of removing the substrate: a heat sink is attached to the surface of the encapsulant.

11. The method of claim 10, further comprising, prior to attaching a heat sink to the surface of the encapsulant: the encapsulant is smoothed by grinding and the thickness of the top layer of the encapsulant is reduced.

12. A package assembly formed according to the method of claim 1, comprising:

a lead frame composed of a plurality of leads; the second surfaces of the leads are in the same plane;

the leads have at least two different heights to form levels with different heights;

the first surfaces of the leads are electrically connected with an electronic element; and

a package body formed by a plastic encapsulating the lead frame and the electronic element and filling the gaps among all the leads and between the leads and the electronic element;

the second surface of the lead is exposed outside the packaging body and is used for external connection.