CN104407229A

CN104407229A - Method for testing capacitance of double-grid field effect transistor

Info

Publication number: CN104407229A
Application number: CN201410576896.8A
Authority: CN
Inventors: 李建成; 徐顺强; 李聪; 尚靖; 李文晓; 吴建飞; 曾祥华; 郑黎明
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2014-10-24
Filing date: 2014-10-24
Publication date: 2015-03-11

Abstract

The invention belongs to a semiconductor device simulation and test technology in the technical field of a semiconductor, and discloses a method for testing the capacitance of a double-grid field effect transistor. The method comprises the following steps: step one, grounding a source, a drain and a second grid by use of a test method for the capacitance of a single-grid field effect transistor, applying bias and AC signals to a first grid, and testing the capacitance Cg1_g1 of the first grid to the first grid and the capacitance Cg1_g2 of the first grid to the second grid; step two, grounding the source, the drain and the first grid, applying bias and AC small signals to the second grid, and testing the capacitance Cg2_g2 of the second grid to the second grid and the capacitance Cg2_g1 of the second grid to the first grid; and step three, calculating the total grid capacitance Cg of the structure of the double-grid field effect transistor, wherein Cg= Cg1_g1+ Cg1_g2+ Cg2_g2+ Cg2_g1.

Description

A kind of method of testing of FET dual gate electric capacity

Technical field

The invention belongs to simulation and the test of the field effect transistor electric capacity of semiconductor device analog and the measuring technology, particularly double-grid structure of technical field of semiconductors.

Background technology

Along with the development of integrated circuit technique, the integrated level of integrated circuit is more and more higher, and size is more and more less.But, when device size close to or when being less than 32 nanometer, due to the short-channel effect of device, the threshold voltage of device is with the channel length generation acute variation of device, and therefore, traditional planar CMOS process technical development runs into extreme difficulties to 32 nanometers and following process node, at this moment, there is three-dimensional technology, the technology of these solids, include the field effect transistor of bigrid or three grid structures.

Adopt the method for testing of single gate FET, by two of FET dual gate grid short circuits, the electric capacity of FET dual gate can be tested, but, when two grids of the transistor of double-grid structure separate, when two grids of FET dual gate add identical signal respectively, at this moment, the electric capacity accurately testing double gate transistor by the method for testing of unipolar transistor is needed.

Summary of the invention

The invention provides a kind of accurate method of testing of the field effect transistor electric capacity for double-grid structure, the method is applicable to two grids of double-grid structure field effect transistor separately, or when two grids independently add identical signal simultaneously, the accurate test of the electric capacity of FET dual gate.

Concrete technical scheme is as follows:

A method of testing for FET dual gate electric capacity, comprises the following steps:

Step 1: the method for testing adopting single gate FET electric capacity, by source electrode 3, drain electrode 4, second grid 6 ground connection, first grid 5 is biased and AC signal, measures the electric capacity C of first grid 5 pairs of first grids 5 _{g1_g1}, the electric capacity C of first grid 5 pairs of source electrodes 3 _{g1_s}, first grid 5 is C to the electric capacity of drain electrode 4 _{g1_d}, first grid 5 pairs of second grids 6 electric capacity C _{g1_g2};

Step 2: by source electrode 3, drain electrode 4, first grid 5 ground connection, second grid 6 is biased and AC signal, measures the electric capacity C of second grid 6 pairs of second grids 6 _{g2_g2}, second grid 6 pairs of source electrodes 3 electric capacity C _{g2_s}, second grid 6 is to the electric capacity C of drain electrode 4 _{g2_d}, second grid 6 pairs of first grids 5 electric capacity C _{g2_g1};

Step 3: the measurement result of essential step 1 and step 2, calculates total gate capacitance C of FET dual gate structure _g, the formula of calculating is as follows:

C _g＝C _{g1_g1}+C _{g1_g2}+C _{g2_g2}+C _{g2_g1}

Preferably, the AC signal in described step 1 and step 2 is voltage is 0.1 millivolt, and frequency is 1 megahertz signal.

Preferably, be biased to voltage described in described step 1 and step 2 and sweep to 1 volt from-1 volt, step-length is 0.05 volt.

Below, to the demonstration of above-mentioned computing formula, the field effect transistor of the double-grid structure of Fig. 1 is considered as two-port network, as shown in Figure 2.

Two port ones and the port 2 of two-port network are connected first grid 5 and second grid 6 respectively, source electrode 3 and drain electrode 4 ground connection.Remember that the admittance parameter of two-port network, capacitance parameter and electric current and voltage are respectively Y, C, I, V, the port that inferior numeral is corresponding.

Calculate total current I:

I＝I ₁+I ₂＝(Y ₁₁+Y ₂₁)V ₁+(Y ₁₂+Y ₂₂)V ₂

When two-port adds same signal voltage V, i.e. V=V ₁=V ₂, now,

I＝(Y ₁₁+Y ₂₁+Y ₁₂+Y ₂₂)V。

Calculate total capacitance C _g:

C _g=(I/V) _{get imaginary part}/ ω=(Y ₁₁+ Y ₂₁+ Y ₁₂+ Y ₂₂) _{get imaginary part}/ ω=(Y ₁₁) _{get imaginary part}/ ω+(Y ₁₂) _{get imaginary part}/ ω+(Y ₂₂) _{get imaginary part}/ ω+(Y ₂₁) _{get imaginary part}/ ω=C ₁₁+ C ₁₂+ C ₂₂+ C ₂₁

Wherein ω is signal angular frequency.To computing formula subscript correspondence change above, i.e. equivalent following computing formula:

C _g＝C _{g1_g1}+C _{g1_g2}+C _{g2_g2}+C _{g2_g1}

In the above formula process of argumentation, each symbol is expressed as:

I ₁for the electric current of port one, I ₂for the electric current of port 2;

V ₁for the voltage of port one, V ₂for the voltage of port 2;

Y ₁₁for port one is to the admittance parameter of port one, Y ₁₂for port one is to the admittance parameter of port 2, Y ₂₁for the admittance parameter of port 2 pairs of port ones, Y ₂₂for the admittance parameter of port 2 pairs of ports 2;

C ₁₁for port one is to the electric capacity of port one, C ₁₂for port one is to the electric capacity of port 2, C ₂₁for the electric capacity of port 2 pairs of port ones, C ₂₂for the electric capacity of port 2 pairs of ports 2;

() _{get imaginary part}represent the computing of the value inside bracket being got to imaginary part.

Adopt the following technique effect of acquisition of the present invention:

First, the present invention tests out one of them grid of the field effect transistor of double-grid structure in two steps respectively to the electric capacity of other electrode, then by total grid capacitance of the field effect transistor that calculates double-grid structure accurately.Secondly, the field effect transistor of double-grid structure is considered as a two-port network by the present invention, is demonstrated the correctness of this method of testing by theory calculate.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of double gate transistor structure;

The field effect transistor of the double-grid structure of Fig. 1 is considered as two-port network schematic diagram by Fig. 2.

Embodiment

Below, in conjunction with concrete the drawings and specific embodiments, the invention will be further described.

Refer to Fig. 2, it is the structural representation of the field effect transistor of double-grid structure.Four electrodes of transistor are marked as shown in the figure: source electrode 3, drain electrode 4, first grid 5, second grid 6.

Total grid capacitance test process of the field effect transistor of this double-grid structure is as follows:

Measure first grid to self and the capacitive process to second grid:

Second grid, source electrode, grounded drain (voltage is 0 volt).

First grid is biased (voltage sweeps to 1 volt from-1 volt, and step-length is 0.05 volt) and AC signal (voltage is 0.1 millivolt, and frequency is 1 megahertz).Measure first grid to the electric capacity of first grid and first grid to the electric capacity of second grid.

Measure second grid to self and the capacitive process to first grid:

First grid, source electrode, grounded drain (voltage is 0 volt).

Second grid is biased (voltage sweeps to 1 volt from-1 volt, and step-length is 0.05 volt) and AC signal (voltage is 0.1 millivolt, and frequency is 1 megahertz).Measure second grid to the electric capacity of second grid and second grid to the electric capacity of first grid.

Solve total grid capacitance:

The above-mentioned first grid measured to the capacitance of first grid, is namely obtained total gate capacitance to the electric capacity of second grid and second grid to the electric capacity of second grid, second grid to the electric capacity of first grid, first grid.

Embodiment and accompanying drawing are to invention has been exemplary description above; obvious realization of the present invention is not subject to the restrictions described above; as long as have employed the various improvement that method of the present invention is conceived and technical scheme is carried out; or design of the present invention and technical scheme directly applied to other occasion, all in protection scope of the present invention without to improve.

Claims

1. a method of testing for FET dual gate electric capacity, is characterized in that, comprises the following steps:

Step 1: the method for testing adopting single gate FET electric capacity, by source electrode (3), drain electrode (4), second grid (6) ground connection, first grid (5) is biased and AC signal, measures the electric capacity C of first grid (5) to first grid (5) _{g1_g1}, first grid (5) is to the electric capacity C of second grid (6) _{g1_g2};

Step 2: by source electrode 3, drain electrode 4, first grid 5 ground connection, second grid is biased and AC signal, measures the electric capacity C of second grid (6) to second grid (6) _{g2_g2}, second grid (6) is to the electric capacity C of first grid (5) _{g2_g1};

C _g＝C _{g1_g1}+C _{g1_g2}+C _{g2_g2}+C _{g2_g1}。

2. the method for testing of FET dual gate electric capacity as claimed in claim 1, is characterized in that: described in described step 1 and step 2, AC signal is voltage is 0.1 millivolt, and frequency is 1 megahertz signal.

3. the method for testing of FET dual gate electric capacity as claimed in claim 1, is characterized in that: be biased to voltage described in described step 1 and step 2 and sweep to 1 volt from-1 volt, step-length is 0.05 volt.