CN104393979A - Discrete compensation adjustment method used for clock recovery - Google Patents
Discrete compensation adjustment method used for clock recovery Download PDFInfo
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Abstract
The invention relates to the field of network communication, in particular to a network clock recovery method based on TDM (time division multiplex). The method comprises the steps that in each single calculation cycle, received network data are sampled and counted at current recovery clock frequency in a specified sampling cycle tsam; an average clock count is calculated; an average clock count Sn in the current calculation cycle is compared with an average clock count Sn-1 in the last calculation cycle; the number of reference pulses in each adjustment section of a current recovery clock in the next calculation cycle is adjusted to increase or decrease based on a comparison result. By means of the discrete compensation adjustment method used for clock recovery, clock self-adaption recovery of data is achieved in the mode aimed at sampling and counting serial numbers of the data, required recovery time is short, and recovery precision is high; the mode of discrete insertion of the pulses is adopted in the adjustment process of the clock, the clock can be adjusted more stably, the clock pulse jitter is small, the clock recovery precision at 2.048 MHz reaches as high as 10 ppb by means of a system, and the aim of synchronous reception and transmission of the network data is well achieved.
Description
Technical field
The present invention relates to a kind of network communication field, particularly a kind of discrete compensation adjustment method for clock recovery.
Background technology
As shown in Figure 1, CES(Circuit Emulation Service) circuit simulation provides a kind of smooth transition scheme from Circuit Switching Network to the packet switching network, tdm data is encapsulated by real-time by transmitting terminal PE equipment, receiving terminal is reached through packet network transmission, synchronised clock is recovered in the queue of receiving terminal PE equipment receiving terminal data buffer storage, synchronised clock decapsulation Frame, is reassembled as tdm traffic; But because TDM net is a kind of Synchronization Network, Packet Based Network is typical asynchronous network, tdm data can cause the clock information of self to lose when being sent to receiving terminal by Packet Based Network, therefore the clock recovery techniques when receiving terminal recovers tdm data is most important, the recovery of data clock information directly affects the quality of transfer of data, and current clock recovery techniques also exists problems such as recovering required time is long, recovery low precision.
Summary of the invention
The invention provides a kind of recover precision high, recover the short network clocking recovery system based on TDM of required time; Comprise data clock point footpath module, data cache module, discrete compensation adjustment system string manipulation module; Described data clock divides footpath module to be connected with described data cache module, discrete compensation adjustment system respectively; Described data cache module, described discrete compensation adjustment system all with described and string manipulation model calling.
Described data clock point footpath module is for sending the control word part in the network data received from packet network into discrete compensation adjustment system.
Described data cache module be used for described network data is sorted, packet loss process.
Described discrete compensation adjustment system for receiving the control word part of described network data, and calculates, adjusts the recovered clock of described network data.
The recovered clock frequency that described and string manipulation module is used for the described network data through sequence, packet loss process and calculating adjust is carried out and string manipulation.
A kind of discrete compensation adjustment system for clock recovery that the present invention provides simultaneously comprises control module, counter module, deviation computing module and clock adjusting module; Described control module calculates model calling with described counter module and deviation respectively; Described deviation computing module is connected with described clock adjusting module; The output of described clock adjusting module is connected with described counter module.
Described control module is for controlling the operation of modules; The current recovery clock frequency that described counter module is used for exporting according to described clock adjusting module counts the data received; Described deviation computing module is for calculating the clock jitter of current recovery clock frequency; Described clock adjusting module is used for the recovered clock of the result of calculation adjustment data according to described deviation computing module, and current recovery clock is exported.
Further, described deviation computing module comprises clock count value accumulator module, clock sampling number of times accumulator module, average clock counting computing module and average clock count contrast module.
Described clock count value accumulator module is used for the clock count accumulated value in cumulative single computing cycle.
Described clock sampling number of times module is used for recording actual samples number of times in single computing cycle.
Average clock counting computing module is for calculating and storing the average clock counting in single computing cycle, actual samples number of times in the clock count accumulated value/computing cycle in the average clock counting=computing cycle in computing cycle.
Described average clock counting contrast module is for contrasting the size that in present clock period, average clock counting counted with the average clock in the upper clock cycle.
Further, described clock adjusting module comprises reference pulse generation module, recovered clock generation module and pulse swap modules.
Described reference pulse generation module is for generation of reference pulse.
Described recovered clock generation module is used for producing current recovery clock according to described reference pulse.
Described pulse swap modules is used for carrying out increase and decrease operation according to the result of calculation of described deviation computing module to the reference pulse that current recovery clock comprises.
Preferably, described reference pulse frequency is 327.68MHz.
Preferably, the mode of successively decreasing is adopted to realize receiving the counting of data in described counter module.
Further, described data cache module comprises write control module, reads control module, dithering cache module, the input of said write control module is connected with data receiver port, the output of said write control module and described dithering cache model calling, described dithering cache module is also connected with described reading control module; Said write control module is used for the write of net control data; Described dithering cache module is for storing described network data; Described reading control module is for controlling the reading of network data in described dithering cache module.
Further, described dithering cache module comprises mark memory module and data memory module, and described mark memory module comprises write-read mark memory module and sequence number memory module; Described data memory module is for storing the payload part of described network data; Described read-write mark memory module is used for storing and payload part write-read mark one to one; Described sequence number memory module is used for the sequence number portion of store network data.
Further, said write control module is also connected with writes reference clock generation module, and described reading control module is also connected with reads recovered clock generation module, described in write reference clock generation module for generation of the reference clock controlling said write control module; Described recovered clock generation module of reading is for generation of the recovered clock controlling described reading control module.
Preferably, said write data step works under 81.92MHz reference clock, and described sense data step works under 81.92MHz recovered clock.
Further, described data cache module also comprises data packet count module, described data packet count module is connected with said write control module and described reading control module simultaneously, its normal bag received for register system, duplicate packages, delay package, packet loss quantity.
The present invention provides a kind of simultaneously and recovers the network clocking restoration methods based on TDM that precision is high, recovery required time is short, comprises following steps:
Comprise and SCN Space Cable Network data to be passed are carried out according to specifying frame number the step encapsulated.
Comprise and control word part in the network data received separated, and calculate, the step of adjustment and recovery clock.
Comprise the network data received carried out sort, the step of packet loss process.
Comprise and the recovered clock frequency that the described network data through sequence, packet loss process and calculating adjust is carried out and the step of string manipulation.
Further, described is discrete compensation adjustment method for clock recovery from control word extracting section time series number according to the step that current recovery clock carries out counting, and it comprises following steps:
Be included in single computing cycle, according to specified sample period t
samthe step of sample count is carried out for control word part; The sampling period t of more than 1 is included in described single computing cycle
sam.
Comprise the step calculating average clock counting in single computing cycle, sampling number in average clock counting Sn=computing cycle internal clock counting accumulated value/computing cycle in described computing cycle.
Comprise average clock counting S in current calculation cycle
ns is counted with average clock in last computing cycle
n-1the step compared.
Comprise the step next computing cycle being equally divided into N number of adjustment section, N is the natural number of more than 1.
Comprise the step carrying out increasing and decreasing adjustment according to comparative result to the reference pulse number that each adjustment section of current recovery clock in next computing cycle comprises, each number of pulses increased or reduce is nominal pulse quantity I MP
num; IMP
numfor as required preset more than 1 natural number.
Further, carry out increasing and decreasing in the step of adjustment to the reference pulse number that each adjustment section of current recovery clock in next computing cycle comprises, as S according to comparative result
n> S
n-1, then in described next computing cycle, the reference pulse number of each adjustment section of current recovery clock reduces IMP
numindividual, otherwise in described next computing cycle, the reference pulse number of each adjustment section of current recovery clock increases IMP
numindividual.
Further, carry out at the reference pulse comprised current recovery clock increasing and decreasing in the step of adjustment, each IMP increased
numindividual pulse is discrete be inserted in former pulse train; Or, each IMP reduced
numindividual pulse is discrete removing from former pulse train.
Further, described network clocking restoration methods is divided into Fast Convergent stage, slow convergence stage and locking converged state three phases according to time order and function and clock convergence rate.
Described Fast Convergent stage, slow convergence stage, locking converged state all include more than one computing cycle.
Wherein, the computing cycle in described Fast Convergent stage is less than the computing cycle in described slow convergence stage, and the computing cycle in described slow convergence stage is less than the computing cycle of described locking converged state.
Described discrete compensation adjustment method also comprises according to the pre-conditioned step judging whether to enter next stage.
Further, the described pre-conditioned computing cycle number >1 for increasing clock pulse number of times in this stage, meanwhile, reduces the computing cycle number >1 of clock pulse number of times; As meet as described in pre-conditioned, then enter next stage.
Further, described nominal pulse quantity I MP
numconstantly reduce along with the prolongation of described computing cycle; Wherein, in the computing cycle of described locking converged state, described nominal pulse quantity I MP
numbe 1.
Further, in any converged state, S
nwith S
n-1when comparing, if | S
n-S
n-1| > convergent failure ident value Fail, then this clock recovery stops, and returns Fast Convergent stage initial condition, restarts to carry out clock recovery calculating; Described convergent failure ident value Fail be set as required be greater than 1 natural number.
Further, in the Fast Convergent stage, S
nwith S
n-1when comparing, if | S
n-S
n-1| this stage of > maximum rated number of pulses IMP
num* m, then this clock recovery stops, and returns Fast Convergent stage initial condition, restarts to carry out clock recovery calculating.
In slow convergence stage or locking converged state, S
nwith S
n-1when comparing, if | S
n-S
n-1| this stage of > maximum rated number of pulses IMP
num* m, then this phase clock recovers to stop, and returns initial condition on last stage, restarts to carry out clock recovery calculating.
Wherein, m be set as required be greater than 2 natural number.
Further, describedly the network data received carried out sort, comprise in the step of packet loss process and write data step as follows:
(1) system electrification, dithering cache module resets.
(2) according to sequence number SEQ value initialization sequence memory module and the read pointer of first packet received; That is, by the primary importance of this sequence number SEQ writing sequence number memory module, and according to the capacity of described sequence number memory module, with this sequence number SEQ for described sequence number memory module is filled up by initial value backward; By the first data packet payload data write data memory module correspondence position, corresponding write-read mark is set to writes mark.
(3) receive new data, travel through described sequence number memory module, search and whether contain new receiving data sequence SEQ, if any, enter step (5), otherwise, enter step (4).
(4) this packet is invalid bag, and invalid bag counting adds 1, and this invalid bag abandons, and returns step 3.
(5) judge whether the write-read mark corresponding with this sequence number SEQ is write mark, in this way, enters step (6); As no, enter step (7).
(6) this packet is duplicate packages, and duplicate packages counting adds 1; Return step (3).
(7) this sequence number correspondence position write payload data in data memory module, is set to the write-read mark corresponding with this sequence number and writes mark; Return step (3).
Further, describedly the network data received carried out sort, also comprise following sense data step in the step of packet loss process:
(1) from the sequence number SEQ that described read pointer points to, order reads number.
(2) judge whether the write-read mark that sequence number SEQ that read pointer points to is corresponding is write mark, in this way, enters step (3); Step (4) is entered as no.
(3) payload data is read from data memory module correspondence position; By corresponding write-read flag clear; Data memory module correspondence position resets; Normal bag counting adds 1, enters step (7).
(4) judge whether write-read mark memory module is time delay mark, enters step (5) in this way; If not being enter step (6).
(5) data corresponding for this sequence number SEQ are read with the packet mode that covers; Packet loss counting adds 1, enters step (7).
(6) correspondence is read and write traffic sign placement time delay mark; Data corresponding for this sequence number SEQ are read with the packet mode that covers; Delay package counting adds 1, enters step (7).
(7) again cover this position after this SEQ value in sequence memory module being added described sequence number memory module capability value, read-write pointer adds 1 and returns step (2).
Further, describedly the network data received is carried out sort, in the step of packet loss process, described having write is masked as 0X1234, and described time delay is masked as 0X5678.
Further, describedly the network data received is carried out sort, in the step of packet loss process, said write data step works under 81.92MHz reference clock, and described sense data step works under 81.92MHz recovered clock.
Further, describedly the network data received is carried out sort, in the step of packet loss process, refer to the packet mode reading that covers and data are set to 0 reading, 0x00 is set to by this packet corresponding data position, and these data are added in reading sequence according to data bit size, there is time delay to avoid sense data.
compared with prior art, beneficial effect of the present invention: the discrete compensation adjustment method for clock recovery provided by the invention adopts the mode for data sequence number sample count to realize the clock self-adaptive recovery of data, recovers required time short, recovers precision high; Discrete insertion pulse mode is adopted in the process that clock is adjusted, clock is adjusted more steady, clock pulse shake is little, adopts the 2.048MHz recovered clock precision of present system realization up to 10ppb, meets network data very well and receive and dispatch synchronous object.
Accompanying drawing illustrates:
Fig. 1 is tdm data grouping queries schematic diagram in background technology.
Fig. 2 is network clocking recovery system structural representation of the present invention.
Fig. 3 is the present invention's discrete compensation adjustment system configuration schematic diagram.
Fig. 4 is data cache module structural representation of the present invention.
Fig. 5 is the flow chart of network data clock recovery method of the present invention.
Fig. 6 is the discrete compensation adjustment method flow diagram of the present invention.
Fig. 7 is network data of the present invention counting flow chart.
Fig. 8 is recovered clock frequency flow chart stage by stage in the embodiment of the present invention 2.
Fig. 9 is recovered clock frequency flow chart stage by stage in the embodiment of the present invention 3.
Figure 10 is dithering cache module write data flowchart in the embodiment of the present invention.
Figure 11 shakes slow module sense data flow chart in the embodiment of the present invention.
Mark in figure: 1-data clock point footpath module, 2-data cache module, 21-writes control module, 22-dithering cache module, 23-reads control module, and 24-writes reference clock generation module, 25-reads recovered clock generation module, 26-data packet count module, the discrete compensation adjustment system of 3-, 31-control module, 32-counter module, 33-deviation computing module, 34-clock adjusting module, 4-string manipulation module.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in further detail.But this should be interpreted as that the scope of the above-mentioned theme of the present invention is only limitted to following embodiment, all technology realized based on content of the present invention all belong to scope of the present invention.
embodiment 1:as shown in Figure 2, the present embodiment provide a kind of recover precision high, recover the short network clocking recovery system based on TDM of required time; Comprise data clock point footpath module 1, data cache module 2, discrete compensation adjustment system 3 string manipulation module 4; Described data clock divides footpath module 1 to be connected 3 with described data cache module 2, discrete compensation adjustment system respectively; Described data cache module 2, described discrete compensation adjustment system 3 are all connected with described and string manipulation module 4.
Described data clock point footpath module 1 is for sending the control word part in the network data received from packet network into discrete compensation adjustment system 3.
Described data cache module 2 for sorting to described network data, packet loss process.
The control word part of described discrete compensation adjustment system 3 for receiving described network data, and calculate, adjust the recovered clock of described network data.
Described and string manipulation module 4 is carried out and string manipulation for the recovered clock frequency described network data through sequence, packet loss process and calculating adjusted, thus realizes described network data clock recovery.
Further, as shown in Figure 3, described discrete compensation adjustment system 3 comprises control module 31, counter module 32, deviation computing module 33 and clock adjusting module 34; Described control module 31 calculates model calling 33 with described counter module 32 and deviation respectively; Described deviation computing module 33 is connected with described clock adjusting module 34; The output of described clock adjusting module 34 is connected with described counter module 32, and the output of described clock adjusting module 34 is connected with described counter module 32.
Described control module 31 is for controlling the operation of modules; Described counter module 32 counts the data received for the current recovery clock frequency exported according to described clock adjusting module 34; Described deviation computing module 33 is for calculating the clock jitter of current recovery clock frequency; Current recovery clock for the recovered clock of the result of calculation adjustment data according to described deviation computing module, and exports by described clock adjusting module 34.
Further, described deviation computing module 33 comprises clock count value accumulator module, clock sampling number of times accumulator module, average clock counting computing module and average clock count contrast module.
Described clock count value accumulator module is used for the clock count accumulated value in cumulative single computing cycle.
Described clock sampling number of times module is used for recording actual samples number of times in single computing cycle.
Average clock counting computing module is for calculating and storing the average clock counting in single computing cycle, actual samples number of times in the clock count accumulated value/single computing cycle in the average clock counting=single computing cycle in described single computing cycle.
Described average clock counting contrast module is for contrasting the size that in present clock period, average clock counting counted with the average clock in the upper clock cycle.
Further, described clock adjusting module 34 comprises reference pulse generation module, recovered clock generation module and pulse swap modules; Described reference pulse generation module is for generation of reference pulse; Described recovered clock generation module is used for producing current recovery clock according to described reference pulse; Described pulse swap modules is used for carrying out increase and decrease operation according to the result of calculation of described deviation computing module to the reference pulse that current recovery clock comprises.
In the present embodiment, described reference pulse generation module for generation of 327.68MHz reference pulse, and in order to recover 2.048MHz clock frequency.
Preferably, the mode of successively decreasing is adopted to realize receiving the counting of data in described counter module 32.
Further, as shown in Figure 4, in the present embodiment, data cache module 2 comprises write control module 21, reads control module 23, dithering cache module 22, the input of said write control module 21 is connected with data receiver port (output of described data point footpath module 1), the output of said write control module 21 is connected with described dithering cache module 22, and described dithering cache module 22 is also connected with described reading control module 23; Said write control module 21 is for the write of net control data; Described dithering cache module 22 is for storing described network data; Described reading control module 23 is for controlling the reading of network data in described dithering cache module, read pointer is provided with in described reading control module 23, the network data sequence number SEQ initialization that described read pointer was received by system first time, after starting read operation, often run through a packet, described read pointer can add 1 operation and point to next packet.
Further, described dithering cache module 22 comprises mark memory module and data memory module, and described mark memory module comprises write-read mark memory module and sequence number memory module; Described data memory module is for storing the payload part of described network data; Described read-write mark memory module is used for storing and payload part write-read mark one to one; Described sequence number memory module is used for the sequence number portion of store network data.In the present embodiment, dithering cache module is pressed 512ms and is calculated, when transmitting 2.048MHz network data by (1 frame duration is 125 us), the then degree of depth=512*1000/125=4096 of described dithering cache module during 1 frame encapsulation, namely described dithering cache module can while buffer memory 4096 frame data.
Further, said write control module 21 is also connected with writes reference clock generation module 24, described reading control module 23 is also connected with reads recovered clock generation module 25, described in write reference clock generation module 24 for generation of the reference clock controlling said write control module 21; Described recovered clock generation module 25 of reading is for generation of the recovered clock controlling described reading control module 23.
Further, in order to prevent the data effusion stored in dithering cache module, storing a half in described dithering cache module and starting sense data operation, be i.e. sense data operation from reception first frame data unwrap the rear 156ms that begins.
Preferably, write the reference clock that reference clock generation module 24 produces 81.92MHz, it is generated by 327.68MHz reference pulse frequency division, and read the recovered clock that recovered clock generation module 25 produces 81.9281.92MHz, it is generated by 2.048MHz recovered clock frequency multiplication.
Further, described reading control module is also connected with data packet count module 26, described data packet count module 25 for record receive normal bag, duplicate packages, delay package, packet loss quantity.
embodiment 2:the present embodiment provides a kind of simultaneously and recovers the network clocking restoration methods based on TDM that precision is high, recovery required time is short, as shown in Figure 5, comprises following steps: comprise step S100: SCN Space Cable Network data to be passed encapsulated according to appointment frame number.
Comprise step S200: control word part in the network data received separated, and calculate, adjustment and recovery clock.
Comprise step S300: the network data received carried out sorting, packet loss process.
Comprise step S400: the recovered clock frequency that the described network data through sequence, packet loss process and calculating adjust carried out and string manipulation, thus realize the step of described network data clock recovery.
Further, as shown in Figure 6, the described step S200 carrying out counting according to current recovery clock from control word extracting section time series number is namely for the discrete compensation adjustment method step of clock recovery: comprise step S210: in single computing cycle, according to specified sample period t
samsample count is carried out for control word part; The sampling period t of more than 1 is included in described single computing cycle
sam; As in the present embodiment, sampling period t
sam=4ms, computing cycle is set as 4096ms, 16384ms, 32768ms, 65536ms, 131072ms as required; In practical application, computing cycle is longer, and computational accuracy is higher, error is less, but in clock recovery field, cost total time is fewer, illustrates that clock recovery efficiency is higher, so should ensure, under the prerequisite that recovery precision is high and error is little, the shortest total spended time should be pursued.
Comprise step S220: calculate average clock counting in single computing cycle, sampling number in average clock counting Sn=computing cycle internal clock counting accumulated value/computing cycle in described computing cycle.
Comprise step S230: by average clock counting S in current calculation cycle
ns is counted with average clock in last computing cycle
n-1compare.
Comprise the step that next computing cycle is equally divided into N number of adjustment section by step S240, N is the natural number of more than 1, in the present embodiment, N value is 4,8,16,32, namely each computing cycle is divided into 4,8,16 or 32 adjustment sections, make the increase of pulse or reduce more even, thus reduce pulse jitter phenomenon.
Comprise step S250: the step carrying out increasing and decreasing adjustment according to comparative result to the reference pulse number that each adjustment section of current recovery clock in next computing cycle comprises, each number of pulses increased or reduce is nominal pulse quantity I MP
num; IMP
numfor as required preset more than 1 natural number.As IMP in the present embodiment
numvalue can be 2048,1024,512,256,128,64,32,16,8,4,2,1.
In the present embodiment, clock recovery pulse is produced through 160 frequency divisions by 327.68MHz reference pulse, in order to recover network data 2.048MHz clock frequency; In step S350, according to the difference (can be 4096ms, 16384ms, 32768ms, 65536ms, 131072ms) of computing cycle value, by nominal pulse quantity I MP
numindividual reference pulse pulse increases or reduces in each adjustment section of next computing cycle.
Further, as shown in Figure 7, in step S210, step S211 is comprised: before sampling starts, set clock count initial value.
Comprise step S212: the clock frequency provided according to current system, according to specified sample period t
samthe network data received is sampled.
Comprise step S213: according to sampled result, clock count initial value is increased or subtracted, thus realize counting.
Comprise step S214: preserve cumulative for described clock count value after the sampling period terminates.
Comprise step S215: record sampling number also resets clock count initial value.
Further, in step S210, the mode of successively decreasing to clock count initial value is adopted to realize counting, described clock count initial value > sampling period t
saminterior theoretical transmission data value * (computing cycle/sampling period t
sam); Described computing cycle is the sampling period t set as required
samintegral multiple, in the present embodiment, the sampling period is t
sam=4ms, computing cycle is set as 4096ms, 16384ms, 32768ms, 65536ms, 131072ms as required; When adopting 2.048MHz clock to send data, in 4ms theoretical transmission data value should be 8192bit due to the present invention adopt setting initial value after decreasing fashion realize counting, and preserve the counting surplus value after the sampling period, in this case, as initial value arranges too small, initial value then may be caused not enough, otherwise, as initial value is excessive, counting surplus value accumulated value then may be caused to overflow, therefore should set initial value as required, in the present embodiment, described clock count initial value is set as 100000000000000000000000(binary system).
Further, in step S210, sampling period t
samafter end, reset in the step of clock count initial value, comprise the step this sampling period clock count surplus value and a upper sampling period clock count surplus value compared; As | this sampling period clock count surplus value-upper sampling period clock count surplus value | > sampling period t
saminterior theoretical transmission data value, then, next sampling period clock count initial value is set as ceil(| this sampling period clock count surplus value-upper sampling period clock count surplus value |/sampling period t
saminterior theoretical transmission data value) * sampling period t
saminterior theoretical transmission data value+this sampling period clock count surplus value; Otherwise next sampling period clock count initial value is set as this sampling period clock count surplus value+sampling period t
saminterior theoretical transmission data value.When adopting 2.048MHz clock to send data, in 4ms, theoretical transmission data value should be 8192bit, namely as | this sampling period clock count surplus value-upper sampling period clock count surplus value | >8192, then, next sampling period clock count initial value is set as ceil(| this sampling period clock count surplus value-upper sampling period clock count surplus value |/8192) and * 8192+ this sampling period clock count surplus value; Otherwise next sampling period clock count initial value is set as this sampling period clock count surplus value+8192.Wherein ceil () is flow in upper plenum (it returns the smallest positive integral being greater than or equal to and specifying expression formula).
Further, in step S210, after the single sampling period terminates, also comprise the step judging whether described computing cycle terminates: as described in computing cycle do not terminate, then enter next sampling period.
As described in computing cycle terminate, then to calculate in this computing cycle average clock counting S
n; Computing formula is: sampling number in this computing cycle of average clock counting Sn=internal clock counting accumulated value/this computing cycle in described computing cycle; Clock count accumulated value resets, and sampling number resets.
Further, in step S210, after single computing cycle terminates, also comprise this computing cycle average clock counting S
ns is counted with a upper computing cycle average clock
n-1the step compared.
As S
n> S
n-1, then send and tune up clock frequency instruction; Otherwise send and slow down clock frequency instruction.
Further, in step S210, after single computing cycle terminates, also comprise this computing cycle average clock counting S
ns is counted with a upper computing cycle average clock
n-1the step compared: as | S
n-S
n-1| > convergent failure ident value Fail, then send the signal of this clock recovery failure; Described convergent failure ident value Fail be set as required be greater than 1 natural number, as in the present embodiment, convergent failure ident value Fail can be 1024 or 2048 or 4096.
Further, in step 250, as S
n> S
n-1, then in next computing cycle, the reference pulse number of each adjustment section of current recovery clock reduces IMP
numindividual (IMP
numneed to be set as 2048,1024,512,256,128,64,32,16,8,4,2,1 according to the stage), otherwise in described next computing cycle, the reference pulse number of each adjustment section of current recovery clock increases IMP
numindividual; In the present embodiment, described reference pulse is 327.68MHz reference pulse, and by 160 frequency divisions to recover 2.048MHz clock frequency; I.e. described increasing, subtract IMP
numthe operation of individual clock pulse is all carried out for 327.68MHz reference pulse.
Further, in step 250, each IMP increased
numindividual pulse is discrete be inserted in former pulse train; Or, each IMP reduced
numindividual pulse is discrete removing from former pulse train, further can reduce the jitter phenomenon because pulse increases or reduces and cause like this.
Further, as shown in Figure 8, in the step S200 of described calculating, adjustment clock frequency, described network clocking restoration methods is divided into Fast Convergent stage, slow convergence stage and locking converged state three phases according to time order and function and clock convergence rate.
Described Fast Convergent stage, slow convergence stage, locking converged state all include more than one computing cycle.
In the present embodiment, the described Fast Convergent stage comprises STEP0, STEP1, STEP2, STEP3, STEP4, STEP5 six STEP sections; Each STEP section all includes the computing cycle of more than 1.
The slow convergence stage comprises STEP6, STEP7, STEP8, STEP9, STEP10 five STEP sections; Each STEP section all includes the computing cycle of more than 1.
Locking converged state comprises STEP11 STEP section, and (STEP0 to STEP11 in chronological sequence carries out successively, do not show each STEP section in Fig. 8, only display comprises Fast Convergent stage of each STEP section, slow convergence stage, locking converged state three converged state).
Wherein, the computing cycle in described Fast Convergent stage is less than the computing cycle in described slow convergence stage, and the computing cycle in described slow convergence stage is less than the computing cycle of described locking converged state.
Described discrete compensation adjustment method also comprises according to the pre-conditioned step judging whether to enter next converged state or next STEP section.
As, in the present embodiment, the described pre-conditioned computing cycle number >1 for increasing clock pulse number of times in this stage, meanwhile, reduces the computing cycle number >1 of clock pulse number of times; As meet as described in pre-conditioned, then enter next converged state or next STEP section, it is to be noted, when entering next converged state or next STEP section or next computing cycle, the recovered clock pulse that reference pulse produces is the adjusted current recovery clock pulse of a computing cycle, and the unjustified recovered clock pulse of non-primary.
Further, described nominal pulse quantity I MP
numconstantly reduce along with the prolongation of described computing cycle; Wherein, in the computing cycle of described locking converged state, described nominal pulse quantity I MP
numbe 1.
Each STEP section computing cycle, adjustment cycle, adjustment section, nominal pulse quantity I MP in each converged state
numthe table of comparisons as table 1:
Table 1
That is, in the Fast Convergent stage, shorter computing cycle is had, larger nominal pulse quantity I MP
num(IMP
numthe speed that the clock pulse that expression system produces restrains to target clock pulse, IMP
numlarger, the speed that the clock pulse that in single computing cycle, system produces restrains to target clock pulse is faster, but precision is poorer, on the contrary, and IMP
numless, the speed that the clock pulse that in single computing cycle, system produces restrains to target clock pulse is slower, but precision is higher); Longer computing cycle and less nominal pulse quantity I MP is had in the slow convergence stage
num; The longest computing cycle and minimum nominal pulse quantity I MP is had in locking converged state
num; The present embodiment adopts slow convergence after first Fast Convergent, constantly reduces convergence rate simultaneously, and the mode improving convergence precision realizes the few but clock recovery mode that convergence precision is high of overall computation time.
Further, in any converged state or in any STEP section, S
nwith S
n-1when comparing, if | S
n-S
n-1| > convergent failure ident value Fail, then this clock recovery stops, and returns Fast Convergent stage initial condition, restarts to carry out clock recovery calculating; Described convergent failure ident value Fail be set as required be greater than 1 natural number; As in the present embodiment, convergent failure ident value Fail can be 1024 or 2048 or 4096, once | S
n-S
n-1| be greater than the convergent failure ident value Fail of setting, then represent within considerable time, can not by current convergence rate (namely by increasing to the clock recovery pulse of current base pulses generation or reducing current I MP
numindividual pulse, thus recover the close speed of pulse to target clock) achieve the goal; As when STEP8 section, IMP
num=8, when | S
n-S
n-1| during >1024 or 2048 or 4096, at least 128 computing cycles, can not realize restraining object, therefore should judge this clock recovery failure.
Further, describedly the network data received carried out sort, comprise following write data step as described in Figure 10 in the step S300 of packet loss process:
Step S311: system electrification, dithering cache module resets.
Step S312: according to sequence number SEQ value initialization sequence memory module and the read pointer of first packet received; That is, by the primary importance of this sequence number SEQ writing sequence number memory module, and according to the capacity of described sequence number memory module, with this sequence number SEQ for described sequence number memory module is filled up by initial value backward; By the first data packet payload data write data memory module correspondence position, corresponding write-read mark is set to writes mark.
Step S313: receive new data, travel through described sequence number memory module, searches and whether contains new receiving data sequence SEQ, if any, enter step S315, otherwise, enter step S314.
Step S314: this packet is invalid bag, invalid bag counting adds 1, and this invalid bag abandons, and returns step S313.
Step S315: judge whether the write-read mark corresponding with this sequence number SEQ is write mark, in this way, enters step S316; As no, enter step S317.
Step S316: this packet is duplicate packages, duplicate packages counting adds 1; Return step S313.
Step S317: this sequence number correspondence position write payload data in data memory module, is set to the write-read mark corresponding with this sequence number and writes mark; Return step S313.
Further, following sense data step as described in Figure 11 is also comprised in described step 300:
Step S321: order reads number from the sequence number SEQ that described read pointer points to.
Step S322: judge whether the write-read mark that sequence number SEQ that read pointer points to is corresponding is write mark, in this way, enters step S323; Step S324. is entered as no
Step S323: read payload data from data memory module correspondence position; By corresponding write-read flag clear; Data memory module correspondence position resets; Normal bag counting adds 1, enters step S327.
Step S324: judge whether write-read mark memory module is time delay mark, enters step S325 in this way; If not being enter step S326.
Step S325: data corresponding for this sequence number SEQ are read with the packet mode that covers; Packet loss counting adds 1, enters step S327.
Step S326: correspondence is read and write traffic sign placement time delay mark; Data corresponding for this sequence number SEQ are read with the packet mode that covers; Delay package counting adds 1, enters step S327.
Step S327: again cover this position after this SEQ value in sequence memory module is added described sequence number memory module capability value, read-write pointer adds 1 and returns step S322.
Further, in described step S300, described having write is masked as 0X1234, and described time delay is masked as 0X5678.
Further, in described step S300, said write data step works under 81.92MHz reference clock, and it is generated by 327.68MHz reference pulse frequency division; Described sense data step works under 81.92MHz recovered clock, and it is generated by 2.048MHz recovered clock frequency multiplication.
In the present embodiment, dithering cache module is pressed 512ms and is calculated, when transmitting 2.048MHz network data by (1 frame duration is 125 us), the then degree of depth=512*1000/125=4096 of described dithering cache module during 1 frame encapsulation, namely described dithering cache module can while buffer memory 4096 frame data.
Further, in order to prevent the data effusion stored in dithering cache module, storing a half in described dithering cache module and starting sense data operation, be i.e. sense data operation from reception first frame data unwrap the rear 156ms that begins.
Further, in described step S300, refer to the packet mode reading that covers and data are set to 0 reading, be set to 0x0000 by this packet corresponding data position, and these data are added in reading sequence according to data bit size, there is time delay to avoid sense data.
embodiment 3:the present embodiment provides a kind of simultaneously and recovers the network clocking restoration methods based on TDM that precision is high, recovery required time is short, as shown in Figure 5, comprises following steps: comprise step S100: SCN Space Cable Network data to be passed encapsulated according to appointment frame number.
Comprise step S200: control word part in the network data received separated, and calculate, adjustment and recovery clock.
Comprise step S300: the network data received carried out sorting, packet loss process.
Comprise step S400: the recovered clock frequency that the described network data through sequence, packet loss process and calculating adjust carried out and string manipulation, thus realize the step of described network data clock recovery.
Further, as shown in Figure 6, described is discrete compensation adjustment method for clock recovery from control word extracting section time series number according to the step S200 that current recovery clock carries out counting, it comprises following steps: comprise step S210: in single computing cycle, according to specified sample period t
samsample count is carried out for control word part; The sampling period t of more than 1 is included in described single computing cycle
sam; As in the present embodiment, sampling period t
sam=4ms, computing cycle is set as 4096ms, 16384ms, 32768ms, 65536ms, 131072ms as required; In practical application, computing cycle is longer, and computational accuracy is higher, error is less, but in clock recovery field, cost total time is fewer, illustrates that clock recovery efficiency is higher, so should ensure, under the prerequisite that recovery precision is high and error is little, the shortest total spended time should be pursued.
Comprise step S220: calculate average clock counting in single computing cycle, sampling number in average clock counting Sn=computing cycle internal clock counting accumulated value/computing cycle in described computing cycle.
Comprise step S230: by average clock counting S in current calculation cycle
ns is counted with average clock in last computing cycle
n-1compare.
Comprise the step that next computing cycle is equally divided into N number of adjustment section by step S240, N is the natural number of more than 1, in the present embodiment, N value is 4,8,16,32, namely each computing cycle is divided into 4,8,16 or 32 adjustment sections, make the increase of pulse or reduce more even, thus reduce pulse jitter phenomenon.
Comprise step S250: the step carrying out increasing and decreasing adjustment according to comparative result to the reference pulse number that each adjustment section of current recovery clock in next computing cycle comprises, each number of pulses increased or reduce is nominal pulse quantity I MP
num; IMP
numfor as required preset more than 1 natural number.As IMP in the present embodiment
numvalue can be 2048,1024,512,256,128,64,32,16,8,4,2,1.
In the present embodiment, clock recovery pulse is produced through 160 frequency divisions by 327.68MHz reference pulse, in order to recover network data 2.048MHz clock frequency; In step S350, according to the difference (can be 4096ms, 16384ms, 32768ms, 65536ms, 131072ms) of computing cycle value, by nominal pulse quantity I MP
numindividual reference pulse pulse increases or reduces in each adjustment section of next computing cycle.
Further, as shown in Figure 7, in step S210, step S211 is comprised: before sampling starts, set clock count initial value.
Comprise step S212: the recovered clock frequency provided according to current system, according to specified sample period t
samthe network data received is sampled.
Comprise step S213: according to sampled result, clock count initial value is increased or subtracted, thus realize counting.
Comprise step S214: preserve cumulative for described clock count value after the sampling period terminates.
Comprise step S215: record sampling number also resets clock count initial value.
Further, in step S210, the mode of successively decreasing to clock count initial value is adopted to realize counting, described clock count initial value > sampling period t
saminterior theoretical transmission data value * (computing cycle/sampling period t
sam); Described computing cycle is the sampling period t set as required
samintegral multiple, in the present embodiment, the sampling period is t
sam=4ms, computing cycle is set as 4096ms, 16384ms, 32768ms, 65536ms, 131072ms as required; When adopting 2.048MHz clock to send data, in 4ms, theoretical transmission data value should be 8192bit, due to the present invention adopt setting initial value after decreasing fashion realize counting, and preserve the counting surplus value after the sampling period, in this case, as initial value arranges too small, initial value then may be caused not enough, otherwise, as initial value is excessive, then counting surplus value accumulated value may be caused to overflow, therefore should set initial value as required, in the present embodiment, described clock count initial value is set as 100000000000000000000000(binary system).
Further, in step S210, sampling period t
samafter end, described clock count initial value is reverted to original initial value 100000000000000000000000(binary system).
Further, in step S210, after the single sampling period terminates, also comprise the step judging whether described computing cycle terminates: as described in computing cycle do not terminate, then enter next sampling period.
As described in computing cycle terminate, then to calculate in this computing cycle average clock counting S
n; Computing formula is: sampling number in this computing cycle of average clock counting Sn=internal clock counting accumulated value/this computing cycle in described computing cycle; Clock count accumulated value resets, and sampling number resets.
Further, in step S210, after single computing cycle terminates, also comprise this computing cycle average clock counting S
ns is counted with a upper computing cycle average clock
n-1the step compared.
As S
n> S
n-1, then send and tune up clock frequency instruction, the reference pulse of each adjustment section of the current recovery clock namely in next computing cycle reduces IMP
numindividual; Otherwise send and slow down clock frequency instruction, the reference pulse of each adjustment section of the current recovery clock namely in next computing cycle increases IMP
numindividual.
Further, in step S210, after single computing cycle terminates, also comprise this computing cycle average clock counting S
ns is counted with a upper computing cycle average clock
n-1the step compared: as | S
n-S
n-1| > convergent failure ident value Fail, then send the signal of this clock recovery failure; Described convergent failure ident value Fail be set as required be greater than 1 natural number, as in the present embodiment, convergent failure ident value Fail can be 1024 or 2048 or 4096.
Further, in step 250, as S
n> S
n-1, then in next computing cycle, the reference pulse number of each adjustment section of current recovery clock reduces IMP
numindividual (IMP
numneed to be set as 2048,1024,512,256,128,64,32,16,8,4,2,1 according to the stage), otherwise in described next computing cycle, the reference pulse number of each adjustment section of current recovery clock increases IMP
numindividual; In the present embodiment, described reference pulse is 327.68MHz reference pulse, and by 160 frequency divisions to recover 2.048MHz clock frequency; I.e. described increasing, subtract IMP
numthe operation of individual clock pulse is all carried out for 327.68MHz reference pulse.
Further, in step 250, each IMP increased
numindividual pulse is discrete be inserted in former pulse train; Or, each IMP reduced
numindividual pulse is discrete removing from former pulse train, further can reduce the jitter phenomenon because pulse increases or reduces and cause like this.
Further, as shown in Figure 8, in the step S200 of described calculating, adjustment clock frequency, described network clocking restoration methods is divided into Fast Convergent stage, slow convergence stage and locking converged state three phases according to time order and function and clock convergence rate.
Described Fast Convergent stage, slow convergence stage, locking converged state all include more than one computing cycle.
Wherein, the computing cycle in described Fast Convergent stage is less than the computing cycle in described slow convergence stage, and the computing cycle in described slow convergence stage is less than the computing cycle of described locking converged state.
Described discrete compensation adjustment method also comprises according to the pre-conditioned step judging whether to enter next converged state.
As, in the present embodiment, the described pre-conditioned computing cycle number >1 for increasing clock pulse number of times in this stage, meanwhile, reduces the computing cycle number >1 of clock pulse number of times; As meet as described in pre-conditioned, then enter next converged state, it is to be noted, when entering next converged state or next computing cycle, the recovered clock pulse that reference pulse produces is the adjusted current recovery clock pulse of a computing cycle, and the unjustified recovered clock pulse of non-primary.
Further, described nominal pulse quantity I MP
numconstantly reduce along with the prolongation of described computing cycle; Wherein, in the computing cycle of described locking converged state, described nominal pulse quantity I MP
numbe 1.
Each STEP section computing cycle, adjustment cycle, adjustment section, nominal pulse quantity I MP in each converged state
numthe table of comparisons as table 1:
Table 1
That is, in the Fast Convergent stage, shorter computing cycle is had, larger nominal pulse quantity I MP
num(IMP
numthe speed that the clock pulse that expression system produces restrains to target clock pulse, IMP
numlarger, the speed that the clock pulse that in single computing cycle, system produces restrains to target clock pulse is faster, but precision is poorer, on the contrary, and IMP
numless, the speed that the clock pulse that in single computing cycle, system produces restrains to target clock pulse is slower, but precision is higher); Longer computing cycle and less nominal pulse quantity I MP is had in the slow convergence stage
num; The longest computing cycle and minimum nominal pulse quantity I MP is had in locking converged state
num; The present embodiment adopts slow convergence after first Fast Convergent, constantly reduces convergence rate simultaneously, and the mode improving convergence precision realizes the few but clock recovery mode that convergence precision is high of overall computation time.
As shown in Figure 9, in the Fast Convergent stage in step s 200, S
nwith S
n-1when comparing, if | S
n-S
n-1| this stage of > maximum rated number of pulses IMP
num* m, then this clock recovery stops, and returns Fast Convergent stage initial condition, restarts to carry out clock recovery calculating.
In slow convergence stage or locking converged state, S
nwith S
n-1when comparing, if | S
n-S
n-1| this stage of > maximum rated number of pulses IMP
num* m, then this phase clock recovers to stop, and returns initial condition on last stage, restarts to carry out clock recovery calculating.
Wherein, m be set as required be greater than 2 natural number, in the present embodiment, m is 50, then in the Fast Convergent stage, if | S
n-S
n-1| >2048*100=102400, then this clock recovery stops, and returns Fast Convergent stage initial condition, restarts to carry out clock recovery calculating.
In the slow convergence stage, as | S
n-S
n-1| >32*50=1600, then this clock recovery stops, and returns Fast Convergent stage initial condition, restarts to carry out clock recovery calculating.
In locking converged state, as | S
n-S
n-1| >1*50=50, then this clock recovery returns slow convergence stage initial condition, restarts to carry out clock recovery calculating.
Once | S
n-S
n-1| be greater than the convergent failure ident value Fail of setting, then represent within considerable time, can not by current convergence rate (namely by increasing to the clock recovery pulse of current base pulses generation or reducing current I MP
numindividual pulse, thus recover the close speed of pulse to target clock) achieve the goal; As when STEP8 section, IMP
num=8, when | S
n-S
n-1| during >1600, at least 200 computing cycles, can not realize restraining object, therefore should judge this clock recovery failure.Further, describedly the network data received carried out sort, comprise following write data step as described in Figure 10 in the step S300 of packet loss process:
Step S311: system electrification, dithering cache module resets.
Step S312: according to sequence number SEQ value initialization sequence memory module and the read pointer of first packet received; That is, by the primary importance of this sequence number SEQ writing sequence number memory module, and according to the capacity of described sequence number memory module, with this sequence number SEQ for described sequence number memory module is filled up by initial value backward; By the first data packet payload data write data memory module correspondence position, corresponding write-read mark is set to writes mark.
Step S313: receive new data, travel through described sequence number memory module, searches and whether contains new receiving data sequence SEQ, if any, enter step S315, otherwise, enter step S314.
Step S314: this packet is invalid bag, invalid bag counting adds 1, and this invalid bag abandons, and returns step S313.
Step S315: judge whether the write-read mark corresponding with this sequence number SEQ is write mark, in this way, enters step S316; As no, enter step S317.
Step S316: this packet is duplicate packages, duplicate packages counting adds 1; Return step S313.
Step S317: this sequence number correspondence position write payload data in data memory module, is set to the write-read mark corresponding with this sequence number and writes mark; Return step S313.
Further, following sense data step as described in Figure 11 is also comprised in described step 300:
Step S321: order reads number from the sequence number SEQ that described read pointer points to.
Step S322: judge whether the write-read mark that sequence number SEQ that read pointer points to is corresponding is write mark, in this way, enters step S323; Step S324 is entered as no.
Step S323: read payload data from data memory module correspondence position; By corresponding write-read flag clear; Data memory module correspondence position resets; Normal bag counting adds 1, enters step S327.
Step S324: judge whether write-read mark memory module is time delay mark, enters step S325 in this way; If not being enter step S326.
Step S325: data corresponding for this sequence number SEQ are read with the packet mode that covers; Packet loss counting adds 1, enters step S327.
Step S326: correspondence is read and write traffic sign placement time delay mark; Data corresponding for this sequence number SEQ are read with the packet mode that covers; Delay package counting adds 1, enters step S327.
Step S327: again cover this position after this SEQ value in sequence memory module is added described sequence number memory module capability value, read-write pointer adds 1 and returns step S322.
Further, in described step S300, described having write is masked as 0X1234, and described time delay is masked as 0X5678.
Further, in described step S300, said write data step works under 81.92MHz reference clock, and it is generated by 327.68MHz reference pulse frequency division; Described sense data step works under 81.92MHz recovered clock, and it is generated by 2.048MHz recovered clock frequency multiplication.
In the present embodiment, dithering cache module is pressed 512ms and is calculated, when transmitting 2.048MHz network data by (1 frame duration is 125 us), the then degree of depth=512*1000/125=4096 of described dithering cache module during 1 frame encapsulation, namely described dithering cache module can while buffer memory 4096 frame data.
Further, in order to prevent the data effusion stored in dithering cache module, storing a half in described dithering cache module and starting sense data operation, be i.e. sense data operation from reception first frame data unwrap the rear 156ms that begins.
Further, in described step S300, refer to the packet mode reading that covers and data are set to 0 reading, be set to 0x0000 by this packet corresponding data position, and these data are added in reading sequence according to data bit size, there is time delay to avoid sense data.
Claims (8)
1., for a discrete compensation adjustment method for clock recovery, it is characterized in that, comprise following steps:
Be included in single computing cycle, according to current recovery clock frequency according to specified sample period t
samthe network data received is carried out to the step of sample count; The sampling period t of more than 1 is included in described single computing cycle
sam;
Comprise the step calculating average clock counting in single computing cycle, average clock counting S in described computing cycle
nsampling number in=computing cycle internal clock counting accumulated value/computing cycle;
Comprise average clock counting S in current calculation cycle
ns is counted with average clock in last computing cycle
n-1the step compared;
Comprise the step next computing cycle being equally divided into N number of adjustment section, N is the natural number of more than 1;
Comprise the step carrying out increasing and decreasing adjustment according to the reference pulse number of comparative result to each adjustment section of current recovery clock in next computing cycle, each reference pulse quantity increased or reduce is nominal pulse quantity I MP
num; IMP
numfor as required preset more than 1 natural number.
2. as claimed in claim 1 for the discrete compensation adjustment method of clock recovery, it is characterized in that, carry out according to the reference pulse number of comparative result to each adjustment section of current recovery clock in next computing cycle increasing and decreasing in the step of adjustment, as S
n> S
n-1, then in described next computing cycle, the reference pulse of each adjustment section of current recovery clock reduces IMP
numindividual, otherwise in described next computing cycle, the reference pulse number of each adjustment section of current recovery clock increases IMP
numindividual.
3. as claimed in claim 1 for the discrete compensation adjustment method of clock recovery, it is characterized in that, carry out at the reference pulse comprised current recovery clock increasing and decreasing in the step of adjustment, each IM increased
pnumindividual pulse is discrete be inserted in former pulse train; Or, each IMP reduced
numindividual pulse is discrete removing from former pulse train.
4. as claimed in claim 1 for the discrete compensation adjustment method of clock recovery, it is characterized in that, described network clocking restoration methods is divided into Fast Convergent stage, slow convergence stage and locking converged state according to clock convergence rate and time order and function;
Described Fast Convergent stage, slow convergence stage, locking converged state all include more than one computing cycle;
Wherein, the computing cycle in described Fast Convergent stage is less than the computing cycle in described slow convergence stage, and the computing cycle in described slow convergence stage is less than the computing cycle of described locking converged state;
Described discrete compensation adjustment method also comprises according to the pre-conditioned step judging whether to enter next stage.
5. as claimed in claim 4 for the discrete compensation adjustment method of clock recovery, it is characterized in that, the described pre-conditioned computing cycle number >1 for increasing clock pulse number of times in this stage, meanwhile, reduces the computing cycle number >1 of clock pulse number of times; As meet as described in pre-conditioned, then enter next stage.
6. the discrete compensation adjustment method for clock recovery as described in any one of claim 4,5, is characterized in that, described nominal pulse quantity I MP
numconstantly reduce along with the prolongation of described computing cycle time; Wherein, in the computing cycle of described locking converged state, described nominal pulse quantity I MP
numbe 1.
7., as claimed in claim 6 for the discrete compensation adjustment method of clock recovery, it is characterized in that, in any converged state, S
nwith S
n-1when comparing, if | S
n-S
n-1| > convergent failure ident value Fail, then this clock recovery stops, and returns Fast Convergent stage initial condition, restarts to carry out clock recovery calculating; Described convergent failure ident value Fail be set as required be greater than 1 natural number.
8., as claimed in claim 6 for the discrete compensation adjustment method of clock recovery, it is characterized in that,
In the Fast Convergent stage, S
nwith S
n-1when comparing, if | S
n-S
n-1| this stage of > maximum rated number of pulses IMP
num* m, then this clock recovery stops, and returns Fast Convergent stage initial condition, restarts to carry out clock recovery calculating;
In slow convergence stage or locking converged state, S
nwith S
n-1when comparing, if | S
n-S
n-1| this stage of > maximum rated number of pulses IMP
num* m, then this phase clock recovers to stop, and returns initial condition on last stage, restarts to carry out clock recovery calculating;
Wherein, m be set as required be greater than 2 natural number.
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