CN105095100B - A kind of hardware realizes the device of hash chained lists - Google Patents
A kind of hardware realizes the device of hash chained lists Download PDFInfo
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- CN105095100B CN105095100B CN201510444153.XA CN201510444153A CN105095100B CN 105095100 B CN105095100 B CN 105095100B CN 201510444153 A CN201510444153 A CN 201510444153A CN 105095100 B CN105095100 B CN 105095100B
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Abstract
The invention discloses the device that a kind of hardware realizes hash chained lists, belong to the lookup compression field of data.A kind of hardware of the present invention realizes that the device of hash chained lists includes FPGA control logics part, is handled accordingly for the data to input, control data output, controls external DRAM to read and write, and controls the insertion, deletion and traversal of ltsh chain table to search；The subpackage of DRAM1 gauge outfit storage parts contains a piece of external dram chip, for storing gauge outfit data and first node address；The subpackage of DRAM2 node data storage parts contains a piece of external dram chip, for memory node data.Compared with prior art, the present invention realizes the insertion, deletion and the traversal read-write of chained list of ltsh chain table using hardware, can obtain speed more faster than existing software realization mode and Geng Gao efficiency.
Description
Technical field
The present invention relates to the lookup compression field of data, more particularly to a kind of hardware to realize the device of hash chained lists.
Background technology
Lookup is one specific information element of searching in substantial amounts of information, and in computer application, lookup is conventional
Basic operation.Number of comparisons conducted in implementation and search procedure of the search efficiency dependent on locating function.Reason
It is without any comparison in the case of thinking, primary access just can obtain the data of required lookup.Hash table is as one kind according to pass
The data structure that key word directly conducts interviews is widely used in various lookups.However, it is difficult to find a hash function energy
Ensure all to produce different cryptographic Hash to any different keyword.Therefore, the efficient method for solving conflict is found so as to reduce
The search length of inquiry is performed during conflict, shortens query responding time into focus of attention.
The application of ltsh chain table can improve search efficiency, and ltsh chain table is the number of a kind of data structure, gauge outfit and node
It is different according to structure, so it can use unified operation when carrying out gauge outfit or the deletion insertion of node and traversing operation.
Realize that the mode of hash chained lists mainly carries out software realization, hardware reality using high-level languages such as C languages at present
Now compared with software is realized, there are faster speed, higher efficiency and more preferable stability.
The content of the invention
The technical problems to be solved by the invention are overcome the deficiencies in the prior art, there is provided a kind of hardware realizes hash chain
The device of table, it is possible to achieve the insert and delete of ltsh chain table is searched with traversal, has faster speed, higher efficiency and more preferable
Stability.
It is of the invention specifically to solve above-mentioned technical problem using following technical scheme：
A kind of hardware realizes the device of hash chained lists, including FPGA control logics part, DRAM1 gauge outfits storage part and
DRAM2 node datas store part；
The FPGA control logics part, reception for key value, the reception of the node being inserted into or gauge outfit data,
The calculation process of cryptographic Hash, the insert and delete of gauge outfit or node and the read-write control of traversal Read-write Catrol, random storage chip DRAM1
System, random storage chip DRAM2 Read-write Catrol and gauge outfit or the output control of node data；It include serial ports receiving module,
Serial ports sending module, baud rate control module, top layer control module, hash module, the control modules of DRAM 1 and DRAM2 controls
Module；
The DRAM1 gauge outfits store part, for the cryptographic Hash and and gauge outfit to will be obtained after key value Hash operation
The first node address of matching is stored, and coordinates the read-write operation of DRAM1 control modules；It includes a piece of random storage chip
DRAM1；
The DRAM2 node datas store part, for each node data of ltsh chain table to be stored, coordinate
The read-write operation of DRAM2 control modules；It includes a piece of random storage chip DRAM2；
FPGA control logics part by bus on chip respectively with random storage chip DRAM1, random storage chip DRAM2
It is connected, realizes the time-sharing multiplex of address and data/address bus, only having one in two DRAM in the same bus cycles is read and write；
Inside FPGA, serial ports receiving module realizes two-way communication with baud rate module respectively with serial ports sending module, with control data
Receive and send；Top layer control module realizes two-way communication with serial ports sending module, to transmit the data to be exported；Top layer controls
Module realizes two-way communication with hash module, to receive the cryptographic Hash that key value is calculated by hash module；
Top layer control module realizes two-way communication with DRAM1 control modules, to control random storage chip DRAM1 read-write, assists simultaneously
Adjust the order with the work of DRAM2 control modules；Top layer control module and DRAM2 control modules realize two-way communication, with control with
Machine storage chip DRAM2 read-write, while coordinate the job order with DRAM1 control modules.
As one of preferred scheme：
The serial ports receiving module is a kind of hardware logic for controlling serial interface to receive data, for receiving outside input
Key value and data and send hash module to after this key value is handled；
The baud rate control module is a kind of hardware logic for producing baud rate, and its effect is the speed of control data transmission
Rate；
The serial ports sending module is a kind of hardware logic for controlling serial interface to send data, and its effect is by top layer control
The data that molding block is sent are sent to host computer by serial ports.
As other in which preferred scheme, the hash module is that a kind of hardware for realizing simple hash function computing is patrolled
Volume, cryptographic Hash is obtained for carrying out Hash operation to key value, then sends this cryptographic Hash and key value to top layer control
Molding block.
As further optimisation of the present invention：
The top layer control module be by finite state machine realize hardware logic, for coordinate DRAM1 control modules with
The work of DRAM2 control modules, the cryptographic Hash of reception processing hash module transmission, judges number according to some positions of key value
According to tupe, selected what next cycle to be read and write to deposit according to the feedback information of DRAM1 control modules or DRAM2 control modules
Store up chip；
The DRAM1 control modules are the hardware logics realized by finite state machine, for controlling the read-write of DRAM1 chips
Operation, and managed by top layer control module, transmit feedback information to top-level module；
The DRAM2 control modules are the hardware logics realized by finite state machine, for controlling the read-write of DRAM2 chips
Operation, and managed by top layer control module, transmit feedback information to top-level module.
Compared with prior art, present invention employs hardware description language to describe required various functions, and utilizes two
Piece dram chip stores gauge outfit and node data respectively, and logic control is carried out using FPGA.FPGA can type selecting it is relatively abundant, can basis
The scale requirements of hash chained lists select suitable model.High-speed traffic can also be realized between FPGA and two panels dram chip,
Access speed is improved, there is stronger flexibility.In patent formula of the present invention, data input output is handled completely by hardware pipe
Reason, compared to software, speed is faster, more efficient, and access scale can be bigger.
Brief description of the drawings
Fig. 1 is a kind of preferred structure for the device that a kind of hardware of the present invention realizes hash chained lists；
Fig. 2 is the basic handling flow for the device data receiver that a kind of hardware of the present invention realizes hash chained lists；
Fig. 3 is that a kind of hardware of the present invention realizes the basic handling flow that the device data of hash chained lists are sent；
Fig. 4 realizes the basic handling flow that the device of hash chained lists inserts for node for a kind of hardware of the present invention；
Fig. 5 is basic handling flow of the device for knot removal that a kind of hardware of the present invention realizes hash chained lists；
Fig. 6 is that a kind of hardware of the present invention realizes the basic handling flow that the device of hash chained lists is searched for traversal.
Embodiment
Technical scheme is described in detail below in conjunction with the accompanying drawings：
Fig. 1 shows that a kind of hardware of the present invention realizes the basic structure of a preferred embodiment of the device of hash chained lists.
The hardware realizes that the device of hash chained lists includes FPGA control logics part, DRAM1 gauge outfits storage part and DRAM2 node datas
Store part；Wherein, FPGA control logics part includes serial ports receiving module, baud rate control module, serial ports sending module, Kazakhstan
Uncommon module, top layer control module, DRAM1 control modules and DRAM2 control modules；DRAM1 gauge outfits storage part point is included in a piece of
Deposit chip DRAM1；DRAM2 node datas storage part point includes a piece of memory chip DRAM2；
Serial ports receiving module, baud rate control module and serial ports sending module are to control serial communication interface UART to enter
The reception and transmission of row data, write realization using hardware description language and carry out encapsulation process, serial ports receiving module passes through
Hash module and top layer control module two-way communication, to realize data receiver function, serial ports sending module directly controls with top layer
Module two-way communication, to realize data sending function.Baud rate module is used for the generation for controlling baud rate, and sends mould with serial ports
Block and serial ports receiving module two-way communication, the speed with sending is received with control data.
Hash module is used to realize Hash operation, is write realization using hardware description language and is carried out encapsulation process,
After serial ports receiving module receives outside incoming key value, then hash module is sent to, calculates cryptographic Hash, and by Hash
Value and key value send top layer control module, hash module and top layer control module two-way communication to.
Top layer control module realizes two-way communication with hash module, DRAM1 control modules and DRAM2 control modules respectively,
Its role is to the cryptographic Hash for receiving hash module transmission is analyzed and processed, and selects data processing mode（Delete, insertion or
Traversal is searched）, coordinate the job order of control DRAM1 control modules and DRAM2 control modules, ensure same clock cycle two panels
Dram chip only has one and read and write.
DRAM1 control modules are used for the read-write operation for controlling DRAM1 chips, and send feedback information to top-level module；
DRAM2 control modules are used for the read-write operation for controlling DRAM2 chips, and send feedback information to top-level module.
DRAM1 chips are interconnected with DRAM2 chips with FPGA control logics part by bus on chip, address bus and data
Time-sharing multiplex rule is respectively adopted in bus, ensures only have one piece of dram chip reading and writing in the same bus cycles, is deleting, is inserting
Enter with traversal search procedure, storing the gauge outfit or node data of the transmission of FPGA control logics part.
Fig. 2 shows that a kind of hardware of the present invention realizes the basic handling flow of the device data receiver of hash chained lists, including
Following steps：
Step 1：Serial ports receiving module passes with baud rate module cooperative operational reception from external serial communication interface UART
The data brought；
Step 2：After serial ports receiving module receives the data of the digit of requirement, hash module, Hash are transferred data to
Module carries out Hash operation to key value and obtains cryptographic Hash, and transmits feedback signal to serial ports receiving module；
Step 3：Hash module sends cryptographic Hash and key value to Top-layer Design Method module, and Top-layer Design Method module is sentenced accordingly
It is disconnected which kind of data processing mode selected, select DRAM1 control modules or the operation of DRAM2 control modules, and to hash module transmission
Feedback signal；
Step 4：DRAM1 control modules carry out write operation to DRAM1 chips, or DRAM2 control modules are entered to DRAM2 chips
Row write operates, and transmits feedback signal to top layer control module.
Fig. 3 shows that a kind of hardware of the present invention realizes the basic handling flow that the device data of hash chained lists are sent, including
Following steps：
Step 1：DRAM1 control modules carry out read operation to DRAM1 chips, or DRAM2 control modules are entered to DRAM2 chips
Row read operation, and the information read is transmitted to top-level module；
Step 2：Top layer control module receives the reading data of DRAM1/DRAM2 control module transmission, carries out respective handling,
Data after processing are sent to serial ports sending module, and feedback information is transmitted to DRAM1/DRAM2 control modules；
Step 3：Serial ports sending module receives the data of top layer control module transmission, and feedback letter is transmitted to top layer control module
Breath, after to data processing, host computer to is sent data by serial communication interface UART according to baud rate requirement.
Fig. 4 shows that a kind of hardware of the present invention realizes the basic handling flow that the device of hash chained lists inserts for node,
After top layer control module receives cryptographic Hash and key value, judgement data processing mode is first carried out, if being judged as, node inserts,
The gauge outfit to match with this cryptographic Hash is then found out in DRAM1 chips by DRAM1 control modules, therefrom extracts the gauge outfit
The address of corresponding first node, send address to top layer control module, then by DRAM2 control modules in DRAM2 chips
Above-mentioned first node is positioned, then inserts node data by comparing key value, while records the address of node preservation.
Fig. 5 shows that a kind of hardware of the present invention realizes basic handling flow of the device for knot removal of hash chained lists,
After top layer control module receives cryptographic Hash and key value, judgement data processing mode is first carried out, if being judged as knot removal,
The gauge outfit to match with this cryptographic Hash is then found out in DRAM1 chips by DRAM1 control modules, therefrom extracts the gauge outfit
The address of corresponding first node, send address to top layer control module, then by DRAM2 control modules in DRAM2 chips
Above-mentioned first node is positioned, then traversal searches each node after this first node, finds out what is matched with above-mentioned key value
Node, empty space of the address in DRAM2 chips corresponding to the node.
Fig. 6 shows that a kind of hardware of the present invention realizes the basic handling flow that the device of hash chained lists is searched for traversal,
After top layer control module receives cryptographic Hash and key value, judgement data processing mode is first carried out, if being judged as, traversal is searched,
The gauge outfit to match with this cryptographic Hash is then traveled through out in DRAM1 chips by DRAM1 control modules, therefrom extracts the gauge outfit
The address of corresponding first node, send address to top layer control module, then by DRAM2 control modules in DRAM2 chips
Above-mentioned first node is positioned, then traversal searches each node after this first node successively, finds out and above-mentioned key value phase
The node matched somebody with somebody, the data of the read/write node.
Claims (1)
1. a kind of hardware realizes the device of hash chained lists, it is characterised in that is deposited including FPGA control logics part, DRAM1 gauge outfits
Storage part and DRAM2 node datas storage part；
The FPGA control logics part, reception, the Hash of reception for key value, the node being inserted into or gauge outfit data
The insert and delete of the calculation process of value, gauge outfit or node and traversal Read-write Catrol, random storage chip DRAM1 Read-write Catrol,
Random storage chip DRAM2 Read-write Catrol and gauge outfit or the output control of node data；It includes serial ports receiving module, serial ports
Sending module, baud rate control module, top layer control module, hash module, the control modules of DRAM 1 and DRAM2 control moulds
Block；The serial ports receiving module is a kind of hardware logic for controlling serial interface to receive data, for receiving the pass of outside input
Key value and data simultaneously send hash module to after this key value is handled；The baud rate control module is a kind of production
The hardware logic of raw baud rate, its effect are the speed of control data transmission；The serial ports sending module is a kind of control serial ports
Interface sends the hardware logic of data, and it is acted on, and to be that the data for sending top layer control module are sent to by serial ports upper
Machine；The hash module is a kind of hardware logic for realizing hash function computing, is obtained for carrying out Hash operation to key value
To cryptographic Hash, then this cryptographic Hash and key value are sent to top layer control module；The top layer control module is by limited
The hardware logic that state machine is realized, for coordinating the work of DRAM1 control modules and DRAM2 control modules, reception processing Hash
The cryptographic Hash of module transmission, judges data processing mode according to some positions of key value, according to DRAM1 control modules or
The feedback information of DRAM2 control modules selects the storage chip to be read and write of next cycle；The DRAM1 control modules are by having
The hardware logic that state machine is realized is limited, is managed for controlling the read-write operation of DRAM1 chips, and by top layer control module, to
Top-level module transmits feedback information；The DRAM2 control modules are the hardware logics realized by finite state machine, for controlling
The read-write operation of DRAM2 chips, and managed by top layer control module, transmit feedback information to top-level module；
The DRAM1 gauge outfits store part, for being matched by the cryptographic Hash obtained after key value Hash operation and with gauge outfit
First node address stored, coordinate DRAM1 control modules read-write operation；It includes a piece of random storage chip DRAM1；
The DRAM2 node datas store part, for each node data of ltsh chain table to be stored, coordinate DRAM2
The read-write operation of control module；It includes a piece of random storage chip DRAM2；FPGA control logics part passes through bus on chip point
It is not connected with random storage chip DRAM1, random storage chip DRAM2, realizes the time-sharing multiplex of address and data/address bus, it is same
Only have one in two DRAM in the individual bus cycles to be read and write；Inside FPGA, serial ports receiving module and serial ports sending module point
Two-way communication is not realized with baud rate module, with the reception and transmission of control data；Top layer control module and serial ports sending module
Two-way communication is realized, to transmit the data to be exported；Top layer control module realizes two-way communication with hash module, to receive process
The cryptographic Hash that key value is calculated hash module；Top layer control module realizes two-way with DRAM1 control modules
Letter, to control random storage chip DRAM1 read-write, while coordinate the order with the work of DRAM2 control modules；Top layer controls mould
Block realizes two-way communication with DRAM2 control modules, to control random storage chip DRAM2 read-write, while coordinates to control with DRAM1
The job order of molding block.
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| CN105827394A (en) * | 2016-03-10 | 2016-08-03 | 浙江亿邦通信科技股份有限公司 | Hash algorithm hardware realization device based on FPGA |
| CN110309374A (en) * | 2019-05-22 | 2019-10-08 | 深圳市金泰克半导体有限公司 | A kind of analytic method, system, terminal device and computer readable storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6654889B1 (en) * | 1999-02-19 | 2003-11-25 | Xilinx, Inc. | Method and apparatus for protecting proprietary configuration data for programmable logic devices |
| CN102571494A (en) * | 2012-01-12 | 2012-07-11 | 东北大学 | Field programmable gate array-based (FPGA-based) intrusion detection system and method |
| CN103023782A (en) * | 2012-11-22 | 2013-04-03 | 北京星网锐捷网络技术有限公司 | Method and device for accessing ternary content addressable memory (TCAM) |
| CN103780460A (en) * | 2014-01-15 | 2014-05-07 | 珠海市佳讯实业有限公司 | System for realizing hardware filtering of TAP device through FPGA |
-
2015
- 2015-07-24 CN CN201510444153.XA patent/CN105095100B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6654889B1 (en) * | 1999-02-19 | 2003-11-25 | Xilinx, Inc. | Method and apparatus for protecting proprietary configuration data for programmable logic devices |
| CN102571494A (en) * | 2012-01-12 | 2012-07-11 | 东北大学 | Field programmable gate array-based (FPGA-based) intrusion detection system and method |
| CN103023782A (en) * | 2012-11-22 | 2013-04-03 | 北京星网锐捷网络技术有限公司 | Method and device for accessing ternary content addressable memory (TCAM) |
| CN103780460A (en) * | 2014-01-15 | 2014-05-07 | 珠海市佳讯实业有限公司 | System for realizing hardware filtering of TAP device through FPGA |
Non-Patent Citations (2)
| Title |
|---|
| A FLEXIBLE HASH TABLE DESIGN FOR 10GBPS KEY-VALUE STORES ON FPGAS;Zsolt Istv´an 等;《Field Programmable Logic and Applications》;20130904(第23期);1-8 * |
| High-throughput Online Hash Table on FPGA;Da Tong 等;《IEEE Computer Society Washington》;20150525;105-112 * |
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