CN105095100A - Device for hash linked list hardware implementation - Google Patents
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- CN105095100A CN105095100A CN201510444153.XA CN201510444153A CN105095100A CN 105095100 A CN105095100 A CN 105095100A CN 201510444153 A CN201510444153 A CN 201510444153A CN 105095100 A CN105095100 A CN 105095100A
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Abstract
The invention discloses a device for hash linked list hardware implementation, and belongs to the field of searching and compression of data. The device for hash linked list hardware implementation comprises a FPGA control logic portion, a DRAM1 header storage portion, and a DRAM2 node data storage portion. The FPGA control logic portion is used to perform corresponding processing on the input data, control data output, and control external DRAM reading-writing, control insertion, deleting, and traversal search of the hash linked list. The DRAM1 header storage portion comprises an external DRAM chip, and is used to store header data and a head node address. The DRAM2 node data storage portion comprises an external DRAM chip, and is used to store node data. Compared with the prior art, hardware is used to realize insertion and deleting of the hash linked list and traversal search of the linked list. The device can obtain faster speed and higher efficiency than an existing software implementation method.
Description
Technical field
What the present invention relates to data searches compression field, particularly relates to a kind of device of hardware implementing hash chained list.
Background technology
Searching is find a specific information element in a large amount of information, and in computer utility, searching is conventional fundamental operation.Search efficiency depends on the number of comparisons of carrying out in the implementation of locating function and search procedure.Be ideally without any comparison, primary access just can obtain the data of desired seek.Hash table is widely used in various searching as a kind of data structure directly conducted interviews according to key word.But, be difficult to find a hash function can ensure all to produce different cryptographic hash to key words different arbitrarily.Therefore, perform the search length of inquiry when finding the method thus reduction conflict that efficiently manage conflict, shorten query responding time and become the focus of concern.
The application of ltsh chain table can improve search efficiency, and ltsh chain table is a kind of data structure, and gauge outfit is different with the data structure of node, can adopt unified operation like this when carrying out deletion insertion and the traversing operation of gauge outfit or node.
The mode realizing hash chained list at present mainly utilizes the higher level lanquages such as C language to carry out software simulating, and hardware implementing, compared with software simulating, has speed, higher efficiency and better stability faster.
Summary of the invention
Technical matters to be solved by this invention is to overcome the deficiencies in the prior art, provides a kind of device of hardware implementing ltsh chain table, and insertion deletion and the traversal that can realize ltsh chain table are searched, and has speed, higher efficiency and better stability faster.
The present invention specifically solves the problems of the technologies described above by the following technical solutions:
A device for hardware implementing hash chained list, comprises FPGA steering logic part, DRAM1 gauge outfit storage area and DRAM2 node data storage area;
Described FPGA steering logic part, the insertion for the calculation process of the reception of the reception of key value, the node be inserted into or gauge outfit data, cryptographic hash, gauge outfit or node is deleted and is controlled with the Read-write Catrol of traversal Read-write Catrol, random storage chip DRAM1, the random Read-write Catrol of storage chip DRAM2 and the output of gauge outfit or node data; It comprises serial ports receiver module, serial ports sending module, baud rate control module, top layer control module, hash module, DRAM1 control module and DRAM2 control module;
Described DRAM1 gauge outfit storage area, for storing by the cryptographic hash obtained after key value Hash operation and the first node address that mates with gauge outfit, coordinates the read-write operation of DRAM1 control module; It comprises the random storage chip DRAM1 of a slice;
Described DRAM2 node data storage area, for being stored by each node data of ltsh chain table, coordinates the read-write operation of DRAM2 control module; It comprises the random storage chip DRAM2 of a slice;
FPGA steering logic part is connected with random storage chip DRAM1, random storage chip DRAM2 respectively by bus on chip, realizes the time-sharing multiplex of address and data bus, only has one to be read and write in the same bus cycles in two DRAM; Inner at FPGA, serial ports receiver module and serial ports sending module realize two-way communication with baud rate module respectively, with the reception of control data and transmission; Top layer control module and serial ports sending module realize two-way communication, to transmit the data that will export; Top layer control module and hash module realize two-way communication, to receive the cryptographic hash calculated key value through hash module; Top layer control module and DRAM1 control module realize two-way communication, to control the read-write of random storage chip DRAM1, coordinate the order with the work of DRAM2 control module simultaneously; Top layer control module and DRAM2 control module realize two-way communication, to control the read-write of random storage chip DRAM2, coordinate the job order with DRAM1 control module simultaneously.
As one of them preferred version:
Described serial ports receiver module is that a kind of serial interface that controls receives the hardware logic of data, is used for receiving the key value of outside input and data and sends hash module to after being processed by this key value;
Described baud rate control module is a kind of hardware logic producing baud rate, and its effect is the speed of control data transmission;
Described serial ports sending module is a kind of hardware logic controlling serial interface transmission data, and its effect is that the data that top layer control module sends are sent to host computer through serial ports.
As wherein another preferred version, described hash module is a kind of hardware logic realizing simple hash function computing, is used for carrying out Hash operation to key value and obtains cryptographic hash, then send this cryptographic hash and key value to top layer control module.
As the present invention's preferred version again:
Described top layer control module is the hardware logic realized by finite state machine, for coordinating the work of DRAM1 control module and DRAM2 control module, receive the cryptographic hash that process hash module transmits, some position according to key value judges data processing mode, according to the storage chip that the feedback information of DRAM1 control module or DRAM2 control module selects next cycle to read and write;
Described DRAM1 control module is the hardware logic realized by finite state machine, for the read-write operation of control DRAM1 chip, and is subject to the management of top layer control module, transmits feedback information to top-level module;
Described DRAM2 control module is the hardware logic realized by finite state machine, for the read-write operation of control DRAM2 chip, and is subject to the management of top layer control module, transmits feedback information to top-level module.
Compared with prior art, present invention employs hardware description language to describe required various functions, and utilize two panels dram chip to store gauge outfit and node data respectively, utilize FPGA to carry out logic control.FPGA can type selecting abundanter, suitable model can be selected according to the scale requirements of hash chained list.Also can realize high-speed traffic between FPGA and two panels dram chip, improve access speed, there is stronger dirigibility.In patent formula of the present invention, data input and output process is completely by hardware management, and compared to software, speed is faster, and efficiency is higher, and access scale can be larger.
Accompanying drawing explanation
Fig. 1 is a kind of preferred structure of the device of a kind of hardware implementing of the present invention hash chained list;
Fig. 2 is the base conditioning flow process of the device data receiver of a kind of hardware implementing hash of the present invention chained list;
Fig. 3 is the base conditioning flow process that the device data of a kind of hardware implementing hash of the present invention chained list send;
Fig. 4 is the base conditioning flow process of device for node city of a kind of hardware implementing hash of the present invention chained list;
Fig. 5 is the base conditioning flow process of device for knot removal of a kind of hardware implementing hash of the present invention chained list;
Fig. 6 is that the device of a kind of hardware implementing hash of the present invention chained list is for traveling through the base conditioning flow process of searching.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in detail:
Fig. 1 shows the basic structure of a preferred embodiment of the device of a kind of hardware implementing hash of the present invention chained list.The device of this hardware implementing hash chained list comprises FPGA steering logic part, DRAM1 gauge outfit storage area and DRAM2 node data storage area; Wherein, FPGA steering logic part comprises serial ports receiver module, baud rate control module, serial ports sending module, hash module, top layer control module, DRAM1 control module and DRAM2 control module; DRAM1 gauge outfit storage area comprises a slice memory chip DRAM1; DRAM2 node data storage area comprises a slice memory chip DRAM2;
Serial ports receiver module, baud rate control module and serial ports sending module control reception and the transmission that serial communication interface UART carries out data, utilize hardware description language to write and realize and carry out encapsulation process, serial ports receiver module is by hash module and the two-way communication of top layer control module, to realize data receiver function, serial ports sending module directly and the two-way communication of top layer control module, to realize data sending function.Baud rate module for controlling the generation of baud rate, and with serial ports sending module and the two-way communication of serial ports receiver module, with control data receive with send speed.
Hash module is used for realizing Hash operation, utilize hardware description language to write and realize and carry out encapsulation process, after receiving at serial ports receiver module the key value imported into outside, be sent to hash module again, calculate cryptographic hash, and send cryptographic hash and key value to top layer control module, hash module and the two-way communication of top layer control module.
Top layer control module realizes two-way communication with hash module, DRAM1 control module and DRAM2 control module respectively, its role is to, the cryptographic hash receiving hash module transmission carries out analyzing and processing, select data processing mode (delete, insert or travel through and search), the job order of cooperation control DRAM1 control module and DRAM2 control module, ensures that same clock period two panels dram chip only has one in read-write.
DRAM1 control module for the read-write operation of control DRAM1 chip, and sends feedback information to top-level module; DRAM2 control module for the read-write operation of control DRAM2 chip, and sends feedback information to top-level module.
DRAM1 chip and DRAM2 chip and FPGA steering logic part are interconnected by bus on chip, address bus and data bus adopt time-sharing multiplex rule respectively, ensure to only have one piece of dram chip in read-write in the same bus cycles, in deletion, insert and in traversal search procedure, store gauge outfit or the node data of FPGA steering logic part transmission.
Fig. 2 shows the base conditioning flow process of the device data receiver of a kind of hardware implementing hash of the present invention chained list, comprises the steps:
Step 1: the data that serial ports receiver module and baud rate module cooperative operational reception send from external serial communication interface UART;
Step 2: serial ports receiver module sends data to hash module after receiving the data of the figure place of requirement, hash module carries out Hash operation to key value and obtains cryptographic hash, and transmits feedback signal to serial ports receiver module;
Step 3: hash module sends cryptographic hash and key value to Top-layer Design Method module, Top-layer Design Method module judges to select which kind of data processing mode accordingly, selects DRAM1 control module or the operation of DRAM2 control module, and transmits feedback signal to hash module;
Step 4:DRAM1 control module carries out write operation to DRAM1 chip, or DRAM2 control module carries out write operation to DRAM2 chip, and transmits feedback signal to top layer control module.
The base conditioning flow process that the device data that Fig. 3 shows a kind of hardware implementing hash of the present invention chained list send, comprises the steps:
Step 1:DRAM1 control module carries out read operation to DRAM1 chip, or DRAM2 control module carries out read operation to DRAM2 chip, and transmits the information read to top-level module;
Data after process are sent to serial ports sending module by step 2: top layer control module receives the reading data that DRAM1/DRAM2 control module is transmitted, and carries out respective handling, and transmit feedback information to DRAM1/DRAM2 control module;
Step 3: serial ports sending module receives the data that top layer control module is transmitted, transmits feedback information to top layer control module, after to data processing, requires to send data to host computer through serial communication interface UART according to baud rate.
Fig. 4 shows the base conditioning flow process of device for node city of a kind of hardware implementing hash of the present invention chained list, after top layer control module receives cryptographic hash and key value, first carry out judgement data processing mode, if be judged as node city, then in DRAM1 chip, find out by DRAM1 control module the gauge outfit that cryptographic hash therewith matches, therefrom extract the first address of node that this gauge outfit is corresponding, address is sent to top layer control module, in DRAM2 chip, above-mentioned first node is located again by DRAM2 control module, then node data is inserted by comparing key value, record the address that node is preserved simultaneously.
Fig. 5 shows the base conditioning flow process of device for knot removal of a kind of hardware implementing hash of the present invention chained list, after top layer control module receives cryptographic hash and key value, first carry out judgement data processing mode, if be judged as knot removal, then in DRAM1 chip, find out by DRAM1 control module the gauge outfit that cryptographic hash therewith matches, therefrom extract the first address of node that this gauge outfit is corresponding, address is sent to top layer control module, in DRAM2 chip, above-mentioned first node is located again by DRAM2 control module, then each node searched after this first node is traveled through, find out the node matched with above-mentioned key value, empty the space of address in DRAM2 chip corresponding to this node.
Fig. 6 shows the device of a kind of hardware implementing hash of the present invention chained list for traveling through the base conditioning flow process of searching, after top layer control module receives cryptographic hash and key value, first carry out judgement data processing mode, if be judged as, traversal is searched, then in DRAM1 chip, travel through out by DRAM1 control module the gauge outfit that cryptographic hash therewith matches, therefrom extract the first address of node that this gauge outfit is corresponding, address is sent to top layer control module, in DRAM2 chip, above-mentioned first node is located again by DRAM2 control module, then each node searched after this first node is traveled through successively, find out the node matched with above-mentioned key value, the data of this node of read/write.
Claims (4)
1. a device for hardware implementing hash chained list, is characterized in that, comprises FPGA steering logic part, DRAM1 gauge outfit storage area and DRAM2 node data storage area;
Described FPGA steering logic part, the insertion for the calculation process of the reception of the reception of key value, the node be inserted into or gauge outfit data, cryptographic hash, gauge outfit or node is deleted and is controlled with the Read-write Catrol of traversal Read-write Catrol, random storage chip DRAM1, the random Read-write Catrol of storage chip DRAM2 and the output of gauge outfit or node data; It comprises serial ports receiver module, serial ports sending module, baud rate control module, top layer control module, hash module, DRAM1 control module and DRAM2 control module;
Described DRAM1 gauge outfit storage area, for storing by the cryptographic hash obtained after key value Hash operation and the first node address that mates with gauge outfit, coordinates the read-write operation of DRAM1 control module; It comprises the random storage chip DRAM1 of a slice;
Described DRAM2 node data storage area, for being stored by each node data of ltsh chain table, coordinates the read-write operation of DRAM2 control module; It comprises the random storage chip DRAM2 of a slice;
FPGA steering logic part is connected with random storage chip DRAM1, random storage chip DRAM2 respectively by bus on chip, realizes the time-sharing multiplex of address and data bus, only has one to be read and write in the same bus cycles in two DRAM; Inner at FPGA, serial ports receiver module and serial ports sending module realize two-way communication with baud rate module respectively, with the reception of control data and transmission; Top layer control module and serial ports sending module realize two-way communication, to transmit the data that will export; Top layer control module and hash module realize two-way communication, to receive the cryptographic hash calculated key value through hash module; Top layer control module and DRAM1 control module realize two-way communication, to control the read-write of random storage chip DRAM1, coordinate the order with the work of DRAM2 control module simultaneously; Top layer control module and DRAM2 control module realize two-way communication, to control the read-write of random storage chip DRAM2, coordinate the job order with DRAM1 control module simultaneously.
2. device as claimed in claim 1, is characterized in that,
Described serial ports receiver module is that a kind of serial interface that controls receives the hardware logic of data, is used for receiving the key value of outside input and data and sends hash module to after being processed by this key value;
Described baud rate control module is a kind of hardware logic producing baud rate, and its effect is the speed of control data transmission;
Described serial ports sending module is a kind of hardware logic controlling serial interface transmission data, and its effect is that the data that top layer control module sends are sent to host computer through serial ports.
3. device as claimed in claim 1, it is characterized in that, described hash module is a kind of hardware logic realizing hash function computing, is used for carrying out Hash operation to key value and obtains cryptographic hash, then send this cryptographic hash and key value to top layer control module.
4. device as claimed in claim 1, is characterized in that,
Described top layer control module is the hardware logic realized by finite state machine, for coordinating the work of DRAM1 control module and DRAM2 control module, receive the cryptographic hash that process hash module transmits, some position according to key value judges data processing mode, according to the storage chip that the feedback information of DRAM1 control module or DRAM2 control module selects next cycle to read and write;
Described DRAM1 control module is the hardware logic realized by finite state machine, for the read-write operation of control DRAM1 chip, and is subject to the management of top layer control module, transmits feedback information to top-level module;
Described DRAM2 control module is the hardware logic realized by finite state machine, for the read-write operation of control DRAM2 chip, and is subject to the management of top layer control module, transmits feedback information to top-level module.
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| CN201510444153.XA CN105095100B (en) | 2015-07-24 | 2015-07-24 | A kind of hardware realizes the device of hash chained lists |
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| CN201510444153.XA CN105095100B (en) | 2015-07-24 | 2015-07-24 | A kind of hardware realizes the device of hash chained lists |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105827394A (en) * | 2016-03-10 | 2016-08-03 | 浙江亿邦通信科技股份有限公司 | Hash algorithm hardware realization device based on FPGA |
| CN110309374A (en) * | 2019-05-22 | 2019-10-08 | 深圳市金泰克半导体有限公司 | A kind of analytic method, system, terminal device and computer readable storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6654889B1 (en) * | 1999-02-19 | 2003-11-25 | Xilinx, Inc. | Method and apparatus for protecting proprietary configuration data for programmable logic devices |
| CN102571494A (en) * | 2012-01-12 | 2012-07-11 | 东北大学 | Field programmable gate array-based (FPGA-based) intrusion detection system and method |
| CN103023782A (en) * | 2012-11-22 | 2013-04-03 | 北京星网锐捷网络技术有限公司 | Method and device for accessing ternary content addressable memory (TCAM) |
| CN103780460A (en) * | 2014-01-15 | 2014-05-07 | 珠海市佳讯实业有限公司 | System for realizing hardware filtering of TAP device through FPGA |
-
2015
- 2015-07-24 CN CN201510444153.XA patent/CN105095100B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6654889B1 (en) * | 1999-02-19 | 2003-11-25 | Xilinx, Inc. | Method and apparatus for protecting proprietary configuration data for programmable logic devices |
| CN102571494A (en) * | 2012-01-12 | 2012-07-11 | 东北大学 | Field programmable gate array-based (FPGA-based) intrusion detection system and method |
| CN103023782A (en) * | 2012-11-22 | 2013-04-03 | 北京星网锐捷网络技术有限公司 | Method and device for accessing ternary content addressable memory (TCAM) |
| CN103780460A (en) * | 2014-01-15 | 2014-05-07 | 珠海市佳讯实业有限公司 | System for realizing hardware filtering of TAP device through FPGA |
Non-Patent Citations (2)
| Title |
|---|
| DA TONG 等: "High-throughput Online Hash Table on FPGA", 《IEEE COMPUTER SOCIETY WASHINGTON》 * |
| ZSOLT ISTV´AN 等: "A FLEXIBLE HASH TABLE DESIGN FOR 10GBPS KEY-VALUE STORES ON FPGAS", 《FIELD PROGRAMMABLE LOGIC AND APPLICATIONS》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105827394A (en) * | 2016-03-10 | 2016-08-03 | 浙江亿邦通信科技股份有限公司 | Hash algorithm hardware realization device based on FPGA |
| CN110309374A (en) * | 2019-05-22 | 2019-10-08 | 深圳市金泰克半导体有限公司 | A kind of analytic method, system, terminal device and computer readable storage medium |
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| CN105095100B (en) | 2018-01-02 |
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