CN104486020B - Network data counting method for clock recovery - Google Patents
Network data counting method for clock recovery Download PDFInfo
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- CN104486020B CN104486020B CN201410761197.0A CN201410761197A CN104486020B CN 104486020 B CN104486020 B CN 104486020B CN 201410761197 A CN201410761197 A CN 201410761197A CN 104486020 B CN104486020 B CN 104486020B
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Abstract
The invention relates to the field of network communication, in particular to a network data counting method for clock recovery. The network data counting method for clock recovery includes the following steps: before sampling is started, an initial clock counting value is set; according to the current clock frequency provided by a system and a specified sampling period tsam, received network data are sampled; according to a sampling result, the initial clock counting value is increased or decreased, and thereby counting is implemented; after the sampling period ends, clock counting values are summed and stored; sampling frequency is recorded, and the initial clock counting value is reset. A network data counter for clock recovery which is provided by the invention adopts a data sequence number sampling and counting mode to implement the analysis of the speed of the current clock of data, and provides an accelerating or slowing instruction for the next step of operation in the clock recovery of the data; when the counter provided by the invention is adopted to carry out network data clock recovery, the needed time is short, the recovery precision is high, and thereby the aim of receiving and transmission synchronization of network data is met well.
Description
Technical field
The present invention relates to a kind of network communication field, more particularly to a kind of network data counting side for clock recovery
Method.
Background technology
As shown in figure 1, CES（Circuit Emulation Service）Circuit simulation provides one kind from Circuit Switching Network
To the smooth transition scheme of the packet switching network, by tdm data by encapsulation in real time, grouped network transmission reaches transmitting terminal PE equipment
Receiving terminal, recovers synchronised clock, synchronised clock decapsulation Frame, weight in receiving terminal PE equipment receiving terminal data buffer storage queues
Group is tdm traffic；But because TDM nets are a kind of synchronous nets, packet net is typical asynchronous network, and tdm data is by packet
Net can cause the clock information of itself to lose when being sent to receiving terminal, therefore the clock recovery when receiving terminal recovers tdm data
Technology is most important, and the recovery of data clock information directly affects the quality of data transfer, and current clock recovery techniques are present
The problems such as long the time required to recovery, recovery low precision.
The content of the invention
It is an object of the invention to the above-mentioned deficiency in the presence of overcoming prior art, there is provided a kind of high precision, extensive recovered
The short network clocking recovery system based on TDM the time required to multiple；Including data clock point footpath module, data cache module, when
Clock recovery module string manipulation module；The data clock point footpath module respectively with the data cache module, clock recovery mould
Block connects；The data cache module, the clock recovery module are connected with described and string manipulation module.
Data clock point footpath module is for the control character segment in the network data received from packet network is sent
Enter clock recovery module.
The data cache module is for being ranked up to the network data, packet loss process.
The clock recovery module is used for the control character segment for receiving the network data, and calculates, adjusts the network
The recovered clock of data.
Described and string manipulation module is extensive for what is adjusted out the network data processed through sequence, packet loss and calculating
Multiple clock frequency is carried out and string manipulation.
Further, the clock recovery module includes network data counting module and clock adjusting module, the network
Data count module includes control module, counting module, deviation computing module；The control module respectively with the counting module
Connect with deviation computing module；The deviation computing module is connected with the clock adjusting module；The clock adjusting module
Outfan is connected with the counting module.
The control module is used for the operation for controlling modules；The counting module is for according to clock adjustment mould
The current recovery clock frequency of block output is counted to the data for receiving；The deviation computing module is used to calculate current extensive
The clock jitter of multiple clock frequency；The clock adjusting module is for according to the result of calculation of deviation computing module adjustment number
According to recovered clock, and current recovery clock is exported.
Further, the deviation computing module includes clock count value accumulator module, clock sampling number of times accumulator module,
Average clock counts computing module and average clock count contrast module.
The clock count value accumulator module is used for the clock count accumulated value added up in single calculating cycle.
The clock sampling number of times module is used to record actual samples number of times in single calculating cycle.
Average clock counts computing module to be used to calculating and storing the counting of the average clock in single calculating cycle, calculates week
Actual samples number of times in the clock count accumulated value/calculating cycle in average clock counting=calculating cycle in phase.
The average clock counts contrast module to be used to contrast average clock counting and a upper clock in present clock period
The size that average clock in cycle is counted.
Further, the clock adjusting module includes reference pulse generation module, recovered clock generation module and arteries and veins
Rush swap modules.
The reference pulse generation module is used to produce reference pulse.
The recovered clock generation module is for according to reference pulse generation current recovery clock.
The pulse swap modules are for including to current recovery clock according to the result of calculation of the deviation computing module
Reference pulse carry out increase and decrease operation.
Preferably, the reference pulse frequency is 327.68MHz.
Preferably, the counting of receiving data is realized in the counting module by the way of successively decreasing.
Further, the data cache module includes writing control module, reads control module, dithering cache module,
The input of said write control module is connected with data receiver port, the outfan of said write control module and the shake
Cache module connects, and the dithering cache module is also connected with the reading control module；Said write control module is used to control
The write of network data processed；The dithering cache module is used to store the network data；The reading control module is used to control
Make the reading of network data in the dithering cache module.
Further, the dithering cache module includes indicating memory module and data memory module, the mark storage
Module includes write-read mark memory module and serial number memory module；The data memory module is used to store the network data
Payload part；The read-write mark memory module is used for storage and the one-to-one write-read mark of payload part；The sequence
Number memory module is used for the sequence number portion for storing network data.
Further, said write control module is also associated with writing reference clock generation module, the reading control module
Be also associated with read recovered clock generation module, it is described write reference clock generation module for produce control said write control module
Reference clock；The recovered clock generation module of reading is used to produce the control recovered clock for reading control module.
Preferably, said write data step works under 81.92MHz reference clocks, and the reading data step exists
81.92MHz work under recovered clock.
Further, the data cache module also includes data packet count module, and the data packet count module is simultaneously
Be connected with said write control module and the reading control module, its be used for the normal bag that record system receives, duplicate packages,
Delay package, packet loss quantity.
Present invention simultaneously provides a kind of recover high precision, recover the short network clocking recovery side based on TDM of required time
Method, comprises the steps of：
The step of comprising SCN Space Cable Network data to be passed are packaged according to specified frame number.
Comprising will in the network data that received control character segment separate, and calculate, adjustment and recovery clock the step of.
Comprising the network data for receiving is ranked up, the step of packet loss is processed.
Carry out simultaneously comprising the recovered clock frequency for the process sorting, the network data of packet loss process and calculating are adjusted out
The step of string manipulation.
Further, it is described from control word extracting section time series number counted according to current recovery clock the step of
In：
It is included in single calculating cycle, according to specified sample period tsamSampled for controlling character segment, and according to
The step of sampled result carries out clock count；Include the sampling period t of more than 1 in the single calculating cyclesam。
Comprising the step of average clock is counted in single calculating cycle is calculated, in the calculating cycle, average clock counts Sn
Sampling number in=calculating cycle internal clock count accumulation/calculating cycle.
S is counted comprising by average clock in current calculation cyclenS is counted with average clock in last calculating cyclen-1Carry out
Relatively the step of.
The step of comprising next calculating cycle is equally divided into N number of adjustment section, N are more than 1 natural number.
Comprising the reference pulse included to each adjustment section of current recovery clock in next calculating cycle according to comparative result
The step of number carries out increase and decrease adjustment, the number of pulses for increasing every time or reducing are nominal pulse quantity I MPnum; IMPnumFor
Default more than 1 natural number as needed.
Further, the benchmark for each adjustment section of current recovery clock in next calculating cycle being included according to comparative result
In the step of umber of pulse carries out increase and decrease adjustment, such as Sn> Sn-1, then each adjustment of current recovery clock in the next calculating cycle
The reference pulse number of section reduces IMPnumIt is individual, the benchmark of each adjustment section of current recovery clock in otherwise described next calculating cycle
Umber of pulse increases IMPnumIt is individual.
Further, in the step of reference pulse included to current recovery clock carries out increase and decrease adjustment, increase every time
IMPnumIndividual pulse is discrete being inserted in former pulse train；Or, the IMP for reducing every timenumIndividual pulse is discrete from original
Remove in pulse train.
Further, the network clocking restoration methods are divided into Fast Convergent rank according to time order and function and clock convergence rate
Section, slow convergence stage and locking converged state three phases.
The Fast Convergent stage, slow convergence stage, locking converged state include more than one calculating cycle.
Wherein, calculating cycle of the calculating cycle in the Fast Convergent stage less than the slow convergence stage, it is described slow
Calculating cycle of the calculating cycle of fast converged state less than the locking converged state.
The discrete compensation adjustment method is also comprising according to the step of pre-conditioned judging whether into next stage.
Further, the pre-conditioned calculating cycle number to increase clock pulses number of times in this stage>1, meanwhile, subtract
The calculating cycle number of few clock pulses number of times>1；It is pre-conditioned as described in meeting, then into next stage.
Further, nominal pulse quantity I MPnumConstantly reduce with the prolongation of the calculating cycle；Wherein,
In the calculating cycle of the locking converged state, nominal pulse quantity I MPnumFor 1.
Further, in any converged state, SnWith Sn-1When being compared, if | Sn- Sn-1| >Convergent failure is identified
Value Fail, then this clock recovery terminate, and return Fast Convergent stage original state, restart to carry out clock recovery calculating；
The convergent failure ident value Fail is according to the natural number more than 1 for needing setting.
Further, in the Fast Convergent stage, SnWith Sn-1When being compared, if | Sn- Sn-1| >This stage is maximum
Nominal pulse quantity I MPnum* m, then this clock recovery terminate, and return Fast Convergent stage original state, restart to carry out
Clock recovery is calculated.
In slow convergence stage or locking converged state, SnWith Sn-1When being compared, if | Sn- Sn-1| >This rank
Maximum rated number of pulses IMP of sectionnum* m, then this phase clock recover to terminate, return original state on last stage, restart
Carry out clock recovery calculating.
Wherein, m is according to the natural number more than 2 for needing setting.
Further, it is described the network data for receiving is ranked up, the step of packet loss is processed in comprising following write
Data step：
（1）System electrification, dithering cache module reset.
（2）Referred to according to the serial number SEQ value initialization sequence memory modules of first packet for receiving and reading
Pin；That is, by the first position of serial number SEQ writing sequence number memory modules, and according to the appearance of the serial number memory module
The serial number memory module is filled up backward by amount by initial value of serial number SEQ；First data packet payload data are write
Data memory module correspondence position, correspondence write-read mark are set to write mark.
（3）New data is received, the serial number memory module is traveled through, is searched whether containing new receiving data sequence SEQ,
If any into step（5）, otherwise, into step（4）.
（4）The packet is invalid bag, and count is incremented for invalid bag, and the invalid bag is abandoned, return to step 3.
（5）Judge whether write-read mark corresponding with serial number SEQ is to have write mark, in this way, into step（6）；Such as
It is no, into step（7）.
（6）The packet is duplicate packages, and count is incremented for duplicate packages；Return to step（3）.
（7）In data memory module, the serial number correspondence position writes payload data, corresponding with the serial number will write
Read mark to be set to write mark；Return to step（3）.
Further, it is described the network data for receiving is ranked up, the step of packet loss is processed in also include following reading
Go out data step：
（1）The serial number SEQ pointed to from the read pointer starts order receive data.
（2）Judge whether the corresponding write-read marks of serial number SEQ that read pointer is pointed to are to have write mark, in this way, into step
Suddenly（3）；Such as no entrance step（4）.
（3）Payload data is read from data memory module correspondence position；Will correspondence write-read flag clear；Data memory module
Correspondence position resets；Count is incremented for normal bag, into step（7）.
（4）Judge whether write-read mark memory module is time delay mark, in this way into step（5）；If not being to enter step
（6）.
（5）By serial number SEQ corresponding data with the packet mode reading that covers；Count is incremented for packet loss, into step（7）.
（6）By correspondence read-write traffic sign placement time delay mark；By serial number SEQ corresponding data with the packet mode reading that covers
Go out；Count is incremented for delay package, into step（7）.
（7）The position is covered again will after the SEQ values in sequence memory module plus the serial number memory module capability value,
Read-write pointer adds 1 and return to step（2）.
Further, it is described the network data for receiving is ranked up, the step of packet loss is processed in, it is described to have write mark
For 0X1232, the time delay is masked as 0X5678.
Further, it is described the network data for receiving is ranked up, the step of packet loss is processed in, said write data
Step works under 81.92MHz reference clocks, and the reading data step works under 81.92MHz recovered clocks.
Further, it is described the network data for receiving is ranked up, the step of packet loss is processed in, with the packet mode that covers
Reading refers to and for data to be set to 0 reading, will the packet corresponding data position be set to 0x00, and by the data according to data
Position size is added in reading sequence, time delay occurs to avoid reading data.
Compared with prior art, beneficial effects of the present invention：Provided by the present invention for the network data meter of clock recovery
Number device realizes that by the way of for data sequence number sample count the speed to data present clock is analyzed, and is the clock of data
Recover next-step operation quickening to be provided or slows down order, the enumerator provided using the present invention is carried out needed for network data clock recovery
Time is short, recovers high precision, meets the synchronous purpose of network data transmitting-receiving very well.
Description of the drawings：
Fig. 1 is tdm data packet transmission schematic diagram in background technology.
Fig. 2 is inventive network clock recovery system structural representation.
Fig. 3 is clock recovery module structural representation of the present invention.
Fig. 4 is data cache module structural representation of the present invention.
Flow charts of the Fig. 5 for inventive network data clock restoration methods.
Fig. 6 is calculated for the present invention, adjustment clock frequency flow chart.
Fig. 7 is inventive network data counts flow chart.
Fig. 8 is recovered clock frequency flow chart stage by stage in the embodiment of the present invention 2.
Fig. 9 is recovered clock frequency flow chart stage by stage in the embodiment of the present invention 3.
Figure 10 is dithering cache module write data flowchart in the embodiment of the present invention.
Figure 11 reads data flowchart for slow module is shaken in the embodiment of the present invention.
Figure 12 is inventive network data counter structural representation.
Labelling in figure：1- data clocks point footpath module, 2- data cache modules, 21- write control modules, 22- shakes are slow
Storing module, 23- read control module, and 24- writes reference clock generation module, and 25- reads recovered clock generation module, 26- packets
Counting module, 3- clock recovery modules, 31- network data enumerators, 311- control modules, 312- counting modules, 313- deviations
Computing module, 32- clock adjusting modules, 4- string manipulation module.
Specific embodiment
With reference to specific embodiment, the present invention is described in further detail.But this should not be interpreted as in the present invention
The scope for stating theme is only limitted to below example, and all technologies realized based on present invention belong to the model of the present invention
Enclose.
Embodiment 1：As shown in Fig. 2 the present embodiment provide it is a kind of recover high precision, recover the time required to it is short based on TDM
Network clocking recovery system；Including data clock point footpath module 1, data cache module 2, clock recovery module 3, and string manipulation
Module 4；The data clock point footpath module 1 is connected 3 with the data cache module 2, clock recovery module respectively；The data
Cache module 2, the clock recovery module 3 are connected with described and string manipulation module 4.
Data clock point footpath module 1 is for the control character segment in the network data received from packet network is sent
Enter clock recovery module 3.
The data cache module 2 is for being ranked up to the network data, packet loss process.
The clock recovery module 3 is for receiving the control character segment of the network data, and calculates, adjusts the net
The recovered clock of network data.
Described and string manipulation module 4 for by it is described through sorting, the network data of packet loss process and calculating adjusts out
Recovered clock frequency is carried out and string manipulation, so as to realize the network data clock recovery.
Further, such as Fig. 3, shown in Figure 12, the clock recovery module 3 includes that network data enumerator 31 and clock are adjusted
Mould preparation block 32；The network data enumerator 31 includes control module 311, counting module 312, deviation computing module 313；It is described
Control module 311 is connected 313 with the counting module 312 and deviation computing module respectively；The deviation computing module 313 and institute
State clock adjusting module 32 to connect；The outfan of the clock adjusting module 32 is connected with the counting module 312, the clock
The outfan of adjusting module 32 is connected with the counting module 312.
The control module 311 is used for the operation for controlling modules；The counting module 312 is for according to the clock
The current recovery clock frequency of the output of adjusting module 32 is counted to the data for receiving；The deviation computing module 313 is used
In the clock jitter for calculating current recovery clock frequency；The clock adjusting module 32 is for according to the deviation computing module
Result of calculation adjusts the recovered clock of data, and current recovery clock is exported.
Further, the deviation computing module 313 includes clock count value accumulator module, and clock sampling number of times adds up mould
Block, average clock count computing module and average clock count contrast module.
The clock count value accumulator module is used for the clock count accumulated value added up in single calculating cycle.
The clock sampling number of times module is used to record actual samples number of times in single calculating cycle.
Average clock counts computing module to be used to calculating and storing the counting of the average clock in single calculating cycle, the list
It is actual in the clock count accumulated value/single calculating cycle in average clock counting=single calculating cycle in one calculating cycle
Sampling number.
The average clock counts contrast module to be used to contrast average clock counting and a upper clock in present clock period
The size that average clock in cycle is counted.
Further, the clock adjusting module 32 include reference pulse generation module, recovered clock generation module and
Pulse swap modules；The reference pulse generation module is used to produce reference pulse；The recovered clock generation module is used for root
Current recovery clock is produced according to the reference pulse；The pulse swap modules are for the calculating according to the deviation computing module
As a result the reference pulse for including to current recovery clock carries out increase and decrease operation.
In the present embodiment, the reference pulse generation module is used to produce 327.68MHz reference pulses, and to recover
2.048MHz clock frequency.
Preferably, the counting of receiving data is realized in the counting module 312 by the way of successively decreasing.
Further, as shown in figure 4, data cache module 2 includes writing control module 21, reads control in the present embodiment
Module 23, dithering cache module 22, the input and data receiver port of said write control module 21（The data point footpath mould
The outfan of block 1）Connection, the outfan of said write control module 21 are connected with the dithering cache module 22, the shake
Cache module 22 is also connected with the reading control module 23；Said write control module 21 is used for writing for controlling network data
Enter；The dithering cache module 22 is used to store the network data；The reading control module 23 is used to control the shake
The reading of network data in cache module, is provided with read pointer in the reading control module 23, the read pointer is by system
The network data serial number SEQ initialization for once receiving, after starting read operation, often runs through a packet, the read pointer
Next packet is pointed in operation Jia 1.
Further, the dithering cache module 22 includes indicating memory module and data memory module that the mark is deposited
Storage module includes write-read mark memory module and serial number memory module；The data memory module is used to store the network number
According to payload part；The read-write mark memory module is used for storage and the one-to-one write-read mark of payload part；The sequence
Row number memory module is used for the sequence number portion for storing network data.In the present embodiment, dithering cache module presses 512ms calculating,
When 2.048MHz network datas are transmitted by the encapsulation of 1 frame（A length of 125 us during 1 frame）, then the depth of the dithering cache module=
512*1000/125=4096, i.e., described dithering cache module can cache 4096 frame data simultaneously.
Further, said write control module 21 is also associated with writing reference clock generation module 24, described to read control
Module 23 is also associated with reading recovered clock generation module 25, it is described write reference clock generation module 24 for produce control described in write
Enter the reference clock of control module 21；The reading recovered clock generation module 25 is used to produce the control reading control module 23
Recovered clock.
Further, for the data effusion for preventing from storing in dithering cache module, in the dithering cache module stores
Data manipulation is started reading out during half, i.e., 156ms after the beginning is unwrapped from the first frame data of reception and start reading out data manipulation.
Preferably, the reference clock that reference clock generation module 24 produces 81.92MHz is write, which is by 327.68MHz benchmark arteries and veins
Punching frequency dividing is generated, and reads the recovered clock that recovered clock generation module 25 produces 81.9281.92MHz, when which is recovered by 2.048MHz
Clock frequency multiplication is generated.
Further, the reading control module is also associated with data packet count module 26, the data packet count module
The 25 normal bags received for record, duplicate packages, delay package, the quantity of packet loss.
Embodiment 2：The present embodiment provides a kind of network based on TDM short the time required to recovering high precision, recovery simultaneously
Clock recovery method, as shown in figure 5, comprising the steps of：Comprising step S100:By SCN Space Cable Network data to be passed according to specified frame number
It is packaged.
Comprising step S200：By in the network data for receiving control character segment separate, and calculate, adjustment and recovery clock.
Comprising step S300：The network data for receiving is ranked up, packet loss is processed.
Comprising step S400：By the recovered clock adjusted out through sequence, the network data of packet loss process and calculating
Frequency is carried out and string manipulation, the step of so as to realize the network data clock recovery.
Further, as shown in fig. 6, described carried out from control word extracting section time series number according to current recovery clock
In the step of counting S200：Comprising step S210：In single calculating cycle, according to specified sample period tsamFor control word
Part is sampled, and carries out clock count according to sampled result；Include the sampling of more than 1 in the single calculating cycle
Cycle tsam；Such as in the present embodiment, sampling period tsam=4ms, calculating cycle be set as needed 4096ms, 16384ms,
32768ms、65536ms、131072ms；In practical application, calculating cycle is longer, and computational accuracy is higher, error is less, but when
Clock recovers field, spends total time fewer, illustrates that clock recovery efficiency is higher, so should ensure that recovery high precision and error are little
On the premise of, most short total cost time should be pursued.
Comprising step S220：Calculate average clock in single calculating cycle to count, average clock meter in the calculating cycle
Sampling number in number Sn=calculating cycles internal clock count accumulation/calculating cycle.
Comprising step S230：Average clock in current calculation cycle is counted into SnWith average clock meter in last calculating cycle
Number Sn-1It is compared.
The step of next calculating cycle is equally divided into N number of adjustment section comprising step S240, N are more than 1 natural number, this
In embodiment, N values are divided into 4,8,16 or 32 adjustment sections for 4,8,16,32, i.e. each calculating cycle so that arteries and veins
Increasing or decreasing for punching is more uniform, so as to reduce pulse jitter phenomenon.
Comprising step S250：Each adjustment section of current recovery clock in next calculating cycle is included according to comparative result
The step of reference pulse number carries out increase and decrease adjustment, the number of pulses for increasing every time or reducing are nominal pulse quantity I MPnum;
IMPnumIt is according to the natural number for needing default more than 1.Such as IMP in the present embodimentnumValue can for 2048,1024,512,
256、128、64、32、16、8、4、2、1。
In the present embodiment, clock recovery pulse is produced through 160 frequency dividings by 327.68MHz reference pulses, to instauration net
Network data 2.048MHz clock frequency；In step S350, according to the difference of calculating cycle value（Can for 4096ms, 16384ms,
32768ms、65536ms、131072ms）, by nominal pulse quantity I MPnumIndividual reference pulse pulse is increased or decreased to next meter
In each adjustment section in calculation cycle.
Further, as shown in fig. 7, in step S210, comprising step S211：Set at the beginning of clock count before sampling starts
Initial value.
Comprising step S212：According to the clock frequency that current system is provided, according to specified sample period tsamTo what is received
Network data is sampled.
Comprising step S213：According to sampled result, clock count initial value is increased or subtracted, so as to realize counting.
Comprising step S214：Preserve the clock count value cumulative after the sampling period terminates.
Comprising step S215：Record sampling number simultaneously resets clock count initial value.
Further, in step S210, realize counting by the way of clock count initial value is successively decreased, the clock meter
Number initial value>Sampling period tsamInterior theoretical transmission data value *（Calculating cycle/sampling period tsam）；The calculating cycle is root
According to the sampling period t for needing settingsamIntegral multiple, in the present embodiment, the sampling period is tsam=4ms, calculating cycle is as needed
It is set as 4096ms, 16384ms, 32768ms, 65536ms, 131072ms；When data are sent using 2.048MHz clocks,
In 4ms, theoretical transmission data value should be 8192bit as the present invention realizes counting using decreasing fashion after setting initial value, and protect
The counting surplus value after the sampling period is deposited, in this case, such as initial value arranges too small, then it is not enough to be likely to result in initial value,
Conversely, as initial value is excessive, be then likely to result in counting surplus value accumulated value and overflow, therefore initial value should be set as needed, this
In embodiment, the clock count initial value is set as 100000000000000000000000（Binary system）.
Further, in step S210, sampling period tsamAfter end, reset clock count initial value the step of in, comprising
The step of this sampling period clock count surplus value is compared with upper sampling period clock count surplus value；Such as | originally adopt
Sample cycle clock counts surplus value-upper sampling period clock count surplus value |>Sampling period tsamInterior theoretical transmission data value,
Then, next sampling period clock count initial value is set as ceil（| this sampling period clock count surplus value-upper sampling week
Phase clock count surplus value |/sampling period tsamInterior theoretical transmission data value）* sampling period tsamInterior theoretical transmission data value+sheet
Sampling period clock count surplus value；Otherwise next sampling period clock count initial value is set as this sampling period clock count
Surplus value+sampling period tsamInterior theoretical transmission data value.When data are sent using 2.048MHz clocks, theoretical transmission in 4ms
Data value should be 8192bit, i.e., such as | this sampling period clock count surplus value-upper sampling period clock count surplus value |>
8192, then, next sampling period clock count initial value is set as ceil（| this sampling period clock count surplus value-upper is adopted
Sample cycle clock counts surplus value | and/8192）* 8192+ this sampling period clock counts surplus value；Otherwise next sampling period when
Clock counts initial value and is set as this sampling period clock count surplus value+8192.Wherein ceil () is flow in upper plenum（Which returns
Return more than or equal to the smallest positive integral for specifying expression formula）.
Further, in step S210, after the single sampling period terminates, also including judging whether the calculating cycle terminates
The step of：As the calculating cycle is not over, then into next sampling period.
As the calculating cycle terminates, then calculate average clock in this calculating cycle and count Sn；Computing formula is：The meter
In the calculation cycle, average clock counts sampling number in Sn=this calculating cycle internal clock count accumulations/this calculating cycle；Clock meter
Number accumulated value resets, and sampling number resets.
Further, in step S210, after single calculating cycle terminates, also include this calculating cycle average clock meter
Number SnS is counted with upper calculating cycle average clockn-1The step of being compared.
Such as Sn> Sn-1, then send and tune up clock frequency instruction；Otherwise send and slow down clock frequency instruction.
Further, in step S210, after single calculating cycle terminates, also include this calculating cycle average clock meter
Number SnS is counted with upper calculating cycle average clockn-1The step of being compared：Such as | Sn- Sn-1| >Convergent failure ident value
Fail, then send the signal of this clock recovery failure；The convergent failure ident value Fail is more than 1 according to needs setting
Natural number, such as in the present embodiment convergent failure ident value Fail can be 1024 or 2048 or 4096.
Further, in step 250, such as Sn> Sn-1, then each adjustment section of current recovery clock in next calculating cycle
Reference pulse number reduce IMPnumIt is individual（IMPnumNeed to may be set to 2048 according to the stage, 1024,512,256,128,64,32,
16、8、4、2、1）, in otherwise described next calculating cycle, the reference pulse number of each adjustment section of current recovery clock increases IMPnum
It is individual；In the present embodiment, the reference pulse is 327.68MHz reference pulses, and divides to recover 2.048MHz clocks by 160
Frequency；I.e. described increasing, subtract IMPnumThe operation of individual clock pulses is carried out for 327.68MHz reference pulses.
Further, in step 250, the IMP for increasing every timenumIndividual pulse is discrete being inserted in former pulse train；
Or, the IMP for reducing every timenumIndividual pulse is the discrete removal from former pulse train, so further can be reduced because of pulse
The jitter phenomenon for increasing or decreasing and causing.
Further, as shown in figure 8, the calculating, adjustment clock frequency the step of S200 in, the network clocking recovery side
Method is divided into Fast Convergent stage, slow convergence stage and locking converged state three phases according to time order and function and clock convergence rate.
The Fast Convergent stage, slow convergence stage, locking converged state include more than one calculating cycle.
In the present embodiment, the Fast Convergent stage includes STEP0, STEP1, STEP2, STEP3, STEP4, STEP5 six
Individual STEP sections；Each STEP section includes the calculating cycle of more than 1.
The slow convergence stage includes five STEP sections of STEP6, STEP7, STEP8, STEP9, STEP10；Each STEP section is equal
Include the calculating cycle of more than 1.
Locking converged state includes mono- STEP section of STEP11（STEP0 to STEP11 is in chronological sequence carried out successively, Fig. 8
In do not show each STEP sections, only show the Fast Convergent stage comprising each STEP sections, slow convergence stage, locking converged state three
Individual converged state）.
Wherein, calculating cycle of the calculating cycle in the Fast Convergent stage less than the slow convergence stage, it is described slow
Calculating cycle of the calculating cycle of fast converged state less than the locking converged state.
The discrete compensation adjustment method is also comprising judging whether into next converged state or next according to pre-conditioned
The step of STEP sections.
Such as, in the present embodiment, the pre-conditioned calculating cycle number to increase clock pulses number of times in this stage>1, together
When, reduce the calculating cycle number of clock pulses number of times>1；It is pre-conditioned as described in meeting, then into next converged state or next
STEP sections, it should be pointed out that when into next converged state or next STEP sections or next calculating cycle, reference pulse are produced
Raw recovered clock pulse is the adjusted current recovery clock pulse of a calculating cycle, and non-primary is unjustified extensive
Multiple clock pulses.
Further, nominal pulse quantity I MPnumConstantly reduce with the prolongation of the calculating cycle；Wherein,
In the calculating cycle of the locking converged state, nominal pulse quantity I MPnumFor 1.
Each STEP section calculating cycle, adjustment cycle, adjustment section, nominal pulse quantity I MP in each converged statenum's
Synopsis such as table 1：
Table 1
That is, in the Fast Convergent stage, shorter calculating cycle, bigger nominal pulse quantity I MP are possessednum（IMPnumTable
Show the speed that the clock pulses that system is produced is restrained to target clock pulse, IMPnumBigger, in single calculating cycle, system is produced
Clock pulses is faster to the speed that target clock pulse restrains, but precision is poorer, conversely, IMPnumIt is less, system in single calculating cycle
The clock pulses that system is produced is slower to the speed that target clock pulse restrains, but precision is higher）；The slow convergence stage possess compared with
Long calculating cycle and less nominal pulse quantity I MPnum；Possess most long calculating cycle and minimum in locking converged state
Nominal pulse quantity I MPnum；The present embodiment, is carried while constantly reducing convergence rate using slow convergence after first Fast Convergent
The mode of high convergence precision realizes that overall computation time is few, but the high clock recovery mode of convergence precision.
Further, in any converged state or arbitrarily in STEP sections, SnWith Sn-1When being compared, if | Sn- Sn-1 |
>Convergent failure ident value Fail, then this clock recovery terminate, and return Fast Convergent stage original state, restart to carry out
Clock recovery is calculated；The convergent failure ident value Fail is according to the natural number more than 1 for needing setting；As in the present embodiment
Convergent failure ident value Fail can be 1024 or 2048 or 4096, once | Sn- Sn-1| more than the convergent failure mark of setting
Value Fail, then it represents that within considerable time, it is impossible to by current convergence rate（I.e. by producing to current base pulse
Raw clock recovery pulse increases or decreases current IMPnumIndividual pulse, so as to recover the close speed of pulse to target clock）Reach
To purpose；Such as in STEP8 sections, IMPnum=8, when | Sn- Sn-1|>When 1024 or 2048 or 4096, calculate at least 128
In cycle, it is impossible to realize convergence purpose, therefore should judge that this clock recovery fails.
Further, it is described the network data for receiving is ranked up, the step of packet loss is processed in S300 comprising as schemed
Following write data step described in 10：
Step S311：System electrification, dithering cache module reset.
Step S312：According to the serial number SEQ value initialization sequence memory modules of first packet for receiving with
And read pointer；That is, by the first position of serial number SEQ writing sequence number memory modules, and mould is stored according to the serial number
The serial number memory module is filled up backward by the capacity of block by initial value of serial number SEQ；By the first data packet payload number
According to write data memory module correspondence position, correspondence write-read mark is set to write mark.
Step S313：New data is received, the serial number memory module is traveled through, is searched whether containing new receiving data sequence
Number SEQ, if any into step S315, otherwise, into step S314.
Step S314：The packet is invalid bag, and count is incremented for invalid bag, and the invalid bag is abandoned, return to step S313.
Step S315：Judge whether write-read mark corresponding with serial number SEQ is to have write mark, in this way, into step
S316；It is such as no, into step S317.
Step S316：The packet is duplicate packages, and count is incremented for duplicate packages；Return to step S313.
Step S317：In data memory module, the serial number correspondence position writes payload data, will be with the serial number pair
The write-read mark answered is set to write mark；Return to step S313.
Further, also include following reading data step as described in Figure 11 in the step 300：
Step S321：The serial number SEQ pointed to from the read pointer starts order receive data.
Step S322：Judge whether the corresponding write-read marks of serial number SEQ that read pointer is pointed to are to have write mark, in this way,
Into step S323；Such as no entrance step S324.
Step S323：Payload data is read from data memory module correspondence position；Will correspondence write-read flag clear；Data are deposited
Storage module correspondence position resets；Count is incremented for normal bag, into step S327.
Step S324：Judge whether write-read mark memory module is time delay mark, in this way into step S325；If do not entered
Enter step S326.
Step S325：By serial number SEQ corresponding data with the packet mode reading that covers；Count is incremented for packet loss, into step
S327。
Step S326：By correspondence read-write traffic sign placement time delay mark；By serial number SEQ corresponding data with the Bao Fang that covers
Formula reads；Count is incremented for delay package, into step S327.
Step S327：Again will cover after the SEQ values in sequence memory module plus the serial number memory module capability value
The position, read-write pointer add 1 and return to step S322.
Further, in step S300, described having write is masked as 0X1232, and the time delay is masked as 0X5678.
Further, in step S300, said write data step works under 81.92MHz reference clocks, its by
327.68MHz reference pulse frequency dividing is generated；It is described reading data step work under 81.92MHz recovered clocks, its by
2.048MHz recovered clock frequency multiplication is generated.
In the present embodiment, dithering cache module presses 512ms calculating, when 2.048MHz network datas are transmitted by the encapsulation of 1 frame
（A length of 125 us during 1 frame）, then depth=the 512*1000/125=4096 of the dithering cache module, i.e., described dithering cache mould
Block can cache 4096 frame data simultaneously.
Further, for the data effusion for preventing from storing in dithering cache module, in the dithering cache module stores
Data manipulation is started reading out during half, i.e., 156ms after the beginning is unwrapped from the first frame data of reception and start reading out data manipulation.
Further, in step S300, referred to the packet mode reading that covers and data are set to into 0 reading, will
Packet corresponding data position is set to 0x0000, and the data are added in reading sequence, to avoid according to data bit size
Read data and time delay occur.
Embodiment 3：The present embodiment provides a kind of network based on TDM short the time required to recovering high precision, recovery simultaneously
Clock recovery method, as shown in figure 5, comprising the steps of：Comprising step S100:By SCN Space Cable Network data to be passed according to specified frame number
It is packaged.
Comprising step S200：By in the network data for receiving control character segment separate, and calculate, adjustment and recovery clock.
Comprising step S300：The network data for receiving is ranked up, packet loss is processed.
Comprising step S400：By the recovered clock adjusted out through sequence, the network data of packet loss process and calculating
Frequency is carried out and string manipulation, the step of so as to realize the network data clock recovery.
Further, as shown in fig. 6, described carried out from control word extracting section time series number according to current recovery clock
In the step of counting S200：Comprising step S210：In single calculating cycle, according to specified sample period tsamFor control word
Part is sampled, and carries out clock count according to sampled result；Include the sampling of more than 1 in the single calculating cycle
Cycle tsam；Such as in the present embodiment, sampling period tsam=4ms, calculating cycle be set as needed 4096ms, 16384ms,
32768ms、65536ms、131072ms；In practical application, calculating cycle is longer, and computational accuracy is higher, error is less, but when
Clock recovers field, spends total time fewer, illustrates that clock recovery efficiency is higher, so should ensure that recovery high precision and error are little
On the premise of, most short total cost time should be pursued.
Comprising step S220：Calculate average clock in single calculating cycle to count, average clock meter in the calculating cycle
Sampling number in number Sn=calculating cycles internal clock count accumulation/calculating cycle.
Comprising step S230：Average clock in current calculation cycle is counted into SnWith average clock meter in last calculating cycle
Number Sn-1It is compared.
The step of next calculating cycle is equally divided into N number of adjustment section comprising step S240, N are more than 1 natural number, this
In embodiment, N values are divided into 4,8,16 or 32 adjustment sections for 4,8,16,32, i.e. each calculating cycle so that arteries and veins
Increasing or decreasing for punching is more uniform, so as to reduce pulse jitter phenomenon.
Comprising step S250：Each adjustment section of current recovery clock in next calculating cycle is included according to comparative result
The step of reference pulse number carries out increase and decrease adjustment, the number of pulses for increasing every time or reducing are nominal pulse quantity I MPnum;
IMPnumIt is according to the natural number for needing default more than 1.Such as IMP in the present embodimentnumValue can for 2048,1024,512,
256、128、64、32、16、8、4、2、1。
In the present embodiment, clock recovery pulse is produced through 160 frequency dividings by 327.68MHz reference pulses, to instauration net
Network data 2.048MHz clock frequency；In step S350, according to the difference of calculating cycle value（Can for 4096ms, 16384ms,
32768ms、65536ms、131072ms）, by nominal pulse quantity I MPnumIndividual reference pulse pulse is increased or decreased to next meter
In each adjustment section in calculation cycle.
Further, as shown in fig. 7, in step S210, comprising step S211：Set at the beginning of clock count before sampling starts
Initial value.
Comprising step S212：According to the recovered clock frequency that current system is provided, according to specified sample period tsamTo receiving
To network data sampled.
Comprising step S213：According to sampled result, clock count initial value is increased or subtracted, so as to realize counting.
Comprising step S214：Preserve the clock count value cumulative after the sampling period terminates.
Comprising step S215：Record sampling number simultaneously resets clock count initial value.
Further, in step S210, realize counting by the way of clock count initial value is successively decreased, the clock meter
Number initial value>Sampling period tsamInterior theoretical transmission data value *（Calculating cycle/sampling period tsam）；The calculating cycle is root
According to the sampling period t for needing settingsamIntegral multiple, in the present embodiment, the sampling period is tsam=4ms, calculating cycle is as needed
It is set as 4096ms, 16384ms, 32768ms, 65536ms, 131072ms；When data are sent using 2.048MHz clocks,
In 4ms, theoretical transmission data value should be 8192bit, as the present invention realizes counting using decreasing fashion after setting initial value, and
The counting surplus value after the sampling period is preserved, in this case, such as initial value arranges too small, then be likely to result in initial value inadequate
With, conversely, as initial value is excessive, be then likely to result in counting surplus value accumulated value and overflow, therefore initial value should be set as needed,
In the present embodiment, the clock count initial value is set as 100000000000000000000000（Binary system）.
Further, in step S210, sampling period tsamAfter end, the clock count initial value is reverted to original
Initial value 100000000000000000000000（Binary system）.
Further, in step S210, after the single sampling period terminates, also including judging whether the calculating cycle terminates
The step of：As the calculating cycle is not over, then into next sampling period.
As the calculating cycle terminates, then calculate average clock in this calculating cycle and count Sn；Computing formula is：The meter
In the calculation cycle, average clock counts sampling number in Sn=this calculating cycle internal clock count accumulations/this calculating cycle；Clock meter
Number accumulated value resets, and sampling number resets.
Further, in step S210, after single calculating cycle terminates, also include this calculating cycle average clock meter
Number SnS is counted with upper calculating cycle average clockn-1The step of being compared.
Such as Sn> Sn-1, then send tune up clock frequency instruction, i.e., the current recovery clock in next calculating cycle each tune
Whole section of reference pulse reduces IMPnumIt is individual；Otherwise send and slow down clock frequency instruction, i.e., the current recovery in next calculating cycle
The reference pulse of clock each adjustment section increases IMPnumIt is individual.
Further, in step S210, after single calculating cycle terminates, also include this calculating cycle average clock meter
Number SnS is counted with upper calculating cycle average clockn-1The step of being compared：Such as | Sn- Sn-1| >Convergent failure ident value
Fail, then send the signal of this clock recovery failure；The convergent failure ident value Fail is more than 1 according to needs setting
Natural number, such as in the present embodiment convergent failure ident value Fail can be 1024 or 2048 or 4096.
Further, in step 250, such as Sn> Sn-1, then each adjustment section of current recovery clock in next calculating cycle
Reference pulse number reduce IMPnumIt is individual（IMPnumNeed to may be set to 2048 according to the stage, 1024,512,256,128,64,32,
16、8、4、2、1）, in otherwise described next calculating cycle, the reference pulse number of each adjustment section of current recovery clock increases IMPnum
It is individual；In the present embodiment, the reference pulse is 327.68MHz reference pulses, and divides to recover 2.048MHz clocks by 160
Frequency；I.e. described increasing, subtract IMPnumThe operation of individual clock pulses is carried out for 327.68MHz reference pulses.
Further, in step 250, the IMP for increasing every timenumIndividual pulse is discrete being inserted in former pulse train；
Or, the IMP for reducing every timenumIndividual pulse is the discrete removal from former pulse train, so further can be reduced because of pulse
The jitter phenomenon for increasing or decreasing and causing.
Further, as shown in figure 8, the step of the calculating, adjustment clock frequency in S200, the network clocking is recovered
Method is divided into Fast Convergent stage, slow convergence stage and locking converged state three according to time order and function and clock convergence rate
Stage.
The Fast Convergent stage, slow convergence stage, locking converged state include more than one calculating cycle.
Wherein, calculating cycle of the calculating cycle in the Fast Convergent stage less than the slow convergence stage, it is described slow
Calculating cycle of the calculating cycle of fast converged state less than the locking converged state.
The discrete compensation adjustment method is also comprising according to the step of pre-conditioned judging whether into next converged state.
Such as, in the present embodiment, the pre-conditioned calculating cycle number to increase clock pulses number of times in this stage>1, together
When, reduce the calculating cycle number of clock pulses number of times>1；It is pre-conditioned as described in meeting, then into next converged state, need
, it is noted that when into next converged state or next calculating cycle, the recovered clock pulse that reference pulse is produced is
The adjusted current recovery clock pulse of one calculating cycle, and the unjustified recovered clock pulse of non-primary.
Further, nominal pulse quantity I MPnumConstantly reduce with the prolongation of the calculating cycle；Wherein,
In the calculating cycle of the locking converged state, nominal pulse quantity I MPnumFor 1.
Each STEP section calculating cycle, adjustment cycle, adjustment section, nominal pulse quantity I MP in each converged statenum's
Synopsis such as table 2：
Table 2
That is, in the Fast Convergent stage, shorter calculating cycle, bigger nominal pulse quantity I MP are possessednum(IMPnumTable
Show the speed that the clock pulses that system is produced is restrained to target clock pulse, IMPnumBigger, in single calculating cycle, system is produced
Clock pulses is faster to the speed that target clock pulse restrains, but precision is poorer, conversely, IMPnumIt is less, system in single calculating cycle
The clock pulses that system is produced is slower to the speed that target clock pulse restrains, but precision is higher)；The slow convergence stage possess compared with
Long calculating cycle and less nominal pulse quantity I MPnum；Possess most long calculating cycle and minimum in locking converged state
Nominal pulse quantity I MPnum；The present embodiment, is carried while constantly reducing convergence rate using slow convergence after first Fast Convergent
The mode of high convergence precision realizes that overall computation time is few, but the high clock recovery mode of convergence precision.
As shown in figure 9, in Fast Convergent stage in step s 200, SnWith Sn-1When being compared, if | Sn- Sn-1
| >This stage maximum rated number of pulses IMPnum* m, then this clock recovery terminate, and return Fast Convergent stage original state,
Restart to carry out clock recovery calculating.
In slow convergence stage or locking converged state, SnWith Sn-1When being compared, if | Sn- Sn-1| >This rank
Maximum rated number of pulses IMP of sectionnum* m, then this phase clock recover to terminate, return original state on last stage, restart
Carry out clock recovery calculating.
Wherein, m is that, according to the natural number more than 2 for needing setting, in the present embodiment, m is 50, then in the Fast Convergent stage
In, if | Sn- Sn-1| >2048*100=102400, then this clock recovery terminate, and return Fast Convergent stage initial shape
State, restarts to carry out clock recovery calculating.
In the slow convergence stage, such as | Sn- Sn-1| >32*50=1600, then this clock recovery terminate, and return quick
Converged state original state, restarts to carry out clock recovery calculating.
In locking converged state, such as | Sn- Sn-1| >1*50=50, then at the beginning of this clock recovery returns the slow convergence stage
Beginning state, restarts to carry out clock recovery calculating.
Once | Sn- Sn-1| more than the convergent failure ident value Fail of setting, then it represents that within considerable time, no
May be by current convergence rate（I.e. by increasing or decreasing currently to the clock recovery pulse of current base pulses generation
IMPnumIndividual pulse, so as to recover the close speed of pulse to target clock）Achieve the goal；Such as in STEP8 sections, IMPnum=8,
When | Sn- Sn-1|>When 1600, at least 200 calculating cycles, it is impossible to realize convergence purpose, therefore this clock should be judged
Recover failure.Further, it is described the network data for receiving is ranked up, the step of packet loss is processed in S300 comprising as schemed
Following write data step described in 10：
Step S311：System electrification, dithering cache module reset.
Step S312：According to the serial number SEQ value initialization sequence memory modules of first packet for receiving with
And read pointer；That is, by the first position of serial number SEQ writing sequence number memory modules, and mould is stored according to the serial number
The serial number memory module is filled up backward by the capacity of block by initial value of serial number SEQ；By the first data packet payload number
According to write data memory module correspondence position, correspondence write-read mark is set to write mark.
Step S313：New data is received, the serial number memory module is traveled through, is searched whether containing new receiving data sequence
Number SEQ, if any into step S315, otherwise, into step S314.
Step S314：The packet is invalid bag, and count is incremented for invalid bag, and the invalid bag is abandoned, return to step S313.
Step S315：Judge whether write-read mark corresponding with serial number SEQ is to have write mark, in this way, into step
S316；It is such as no, into step S317.
Step S316：The packet is duplicate packages, and count is incremented for duplicate packages；Return to step S313.
Step S317：In data memory module, the serial number correspondence position writes payload data, will be with the serial number pair
The write-read mark answered is set to write mark；Return to step S313.
Further, also include following reading data step as described in Figure 11 in the step 300：
Step S321：The serial number SEQ pointed to from the read pointer starts order receive data.
Step S322：Judge whether the corresponding write-read marks of serial number SEQ that read pointer is pointed to are to have write mark, in this way,
Into step S323；Such as no entrance step S324.
Step S323：Payload data is read from data memory module correspondence position；Will correspondence write-read flag clear；Data are deposited
Storage module correspondence position resets；Count is incremented for normal bag, into step S327.
Step S324：Judge whether write-read mark memory module is time delay mark, in this way into step S325；If do not entered
Enter step S326.
Step S325：By serial number SEQ corresponding data with the packet mode reading that covers；Count is incremented for packet loss, into step
S327。
Step S326：By correspondence read-write traffic sign placement time delay mark；By serial number SEQ corresponding data with the Bao Fang that covers
Formula reads；Count is incremented for delay package, into step S327.
Step S327：Again will cover after the SEQ values in sequence memory module plus the serial number memory module capability value
The position, read-write pointer add 1 and return to step S322.
Further, in step S300, described having write is masked as 0X1232, and the time delay is masked as 0X5678.
Further, in step S300, said write data step works under 81.92MHz reference clocks, its by
327.68MHz reference pulse frequency dividing is generated；It is described reading data step work under 81.92MHz recovered clocks, its by
2.048MHz recovered clock frequency multiplication is generated.
In the present embodiment, dithering cache module presses 512ms calculating, when 2.048MHz network datas are transmitted by the encapsulation of 1 frame
（A length of 125 us during 1 frame）, then depth=the 512*1000/125=4096 of the dithering cache module, i.e., described dithering cache mould
Block can cache 4096 frame data simultaneously.
Further, for the data effusion for preventing from storing in dithering cache module, in the dithering cache module stores
Data manipulation is started reading out during half, i.e., 156ms after the beginning is unwrapped from the first frame data of reception and start reading out data manipulation.
Further, in step S300, referred to the packet mode reading that covers and data are set to into 0 reading, will
Packet corresponding data position is set to 0x0000, and the data are added in reading sequence, to avoid according to data bit size
Read data and time delay occur.
Claims (6)
1. a kind of network data method of counting for clock recovery, it is characterised in that comprise the steps of：
The step of being included in setting clock count initial value before sampling starts；
Comprising the clock frequency provided according to current system, the network data for receiving is carried out according to specified sample period tsam
The step of sampling；
Comprising according to sampled result, clock count initial value is increased or subtracted, so as to realize the step of counting；
Be included in the sampling period terminate after by the clock count value cumulative preservation the step of；
Comprising record sampling number and the step of reset clock count initial value；
Realize counting by the way of clock count initial value is successively decreased, the clock count initial value>In sampling period tsam
Theoretical transmission data value *（Calculating cycle/sampling period tsam）；The calculating cycle is according to the sampling period for needing setting
The integral multiple of tsam.
2. the network data method of counting of clock recovery is used for as claimed in claim 1, it is characterised in that sampling period tsam
After end, the clock count initial value is reverted to into original initial value；The original initial value refers to that sampling period first time opens
The clock count initial value of setting before beginning.
3. the network data method of counting of clock recovery is used for as claimed in claim 1, it is characterised in that sampling period tsam
After end, reset clock count initial value the step of in, comprising by this sampling period clock count surplus value and upper one sampling week
The step of phase clock count surplus value is compared；Such as | this sampling period clock count surplus value-upper sampling period clock meter
Number surplus value |>Theoretical transmission data value in sampling period tsam, then, next sampling period clock count initial value is set as
ceil（| this sampling period clock count surplus value-upper sampling period clock count surplus value | is theoretical in/sampling period tsam
Transmission data value）* theoretical transmission data value+this sampling period clock count surplus value in sampling period tsam；It is otherwise next to adopt
Sample cycle clock counts initial value and is set as theoretical transmission data in this sampling period clock count surplus value+sampling period tsam
Value.
4. the network data method of counting for clock recovery as described in any one of Claims 2 or 3, it is characterised in that institute
The network data method of counting for clock recovery is stated, after the single sampling period terminates, also including judging that the calculating cycle is
The step of no end；
As the calculating cycle is not over, then into next sampling period；
As the calculating cycle terminates, then calculate average clock in this calculating cycle and count Sn；Computing formula is：It is described to calculate week
In phase, average clock counts sampling number in Sn=this calculating cycle internal clock count accumulations/this calculating cycle；Clock count tires out
Value added clearing, sampling number reset.
5. the network data method of counting of clock recovery is used for as claimed in claim 4, it is characterised in that described for clock
The network data method of counting of recovery, after single calculating cycle terminates, also includes for this calculating cycle average clock counting Sn
The step of being compared with upper calculating cycle average clock counting Sn-1；
Such as Sn>Sn-1, then send and tune up clock frequency instruction；Otherwise send and slow down clock frequency instruction.
6. the network data method of counting of clock recovery is used for as claimed in claim 4, it is characterised in that described for clock
The network data method of counting of recovery, after single calculating cycle terminates, also includes for this calculating cycle average clock counting Sn
The step of being compared with upper calculating cycle average clock counting Sn-1；
Such as | Sn- Sn-1 |>Convergent failure ident value Fail, then send the signal of this clock recovery failure；The convergence is lost
It is according to the natural number more than 1 for needing setting to lose ident value Fail.
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| CN102315851A (en) * | 2011-04-19 | 2012-01-11 | 无锡辐导微电子有限公司 | Counting, phase-detecting and decoding device and method |
| CN102932084A (en) * | 2012-10-17 | 2013-02-13 | 航天科工深圳（集团）有限公司 | Sampling clock synchronizing method and system |
| CN104144023A (en) * | 2013-05-10 | 2014-11-12 | 中国电信股份有限公司 | Method, device and system for clock synchronization |
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| CN102315851A (en) * | 2011-04-19 | 2012-01-11 | 无锡辐导微电子有限公司 | Counting, phase-detecting and decoding device and method |
| CN102932084A (en) * | 2012-10-17 | 2013-02-13 | 航天科工深圳（集团）有限公司 | Sampling clock synchronizing method and system |
| CN104144023A (en) * | 2013-05-10 | 2014-11-12 | 中国电信股份有限公司 | Method, device and system for clock synchronization |
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