CN106559159B - Circuit emulation service clock synchronization detecting method and device - Google Patents
Circuit emulation service clock synchronization detecting method and device Download PDFInfo
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- CN106559159B CN106559159B CN201510642244.4A CN201510642244A CN106559159B CN 106559159 B CN106559159 B CN 106559159B CN 201510642244 A CN201510642244 A CN 201510642244A CN 106559159 B CN106559159 B CN 106559159B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0647—Synchronisation among TDM nodes
Abstract
The present invention provides a kind of circuit emulation service clock synchronization detecting method and device, this method include：Obtain the first CES data and the 2nd CES data in network, wherein the first CES data are the data that the jitter cache that the 2nd CES data are PSN destination NE exports into the data before the jitter cache of PSN destination NE；It detects the first CES data and whether the clock frequency of the 2nd CES data is synchronous.The clock frequency that the present invention passes through the data before and after the jitter cache of comparison PSN destination NE determines whether CES clock synchronizes, and can quickly detect whether CES data both ends clock synchronizes, finds the problem in advance, reduce subsequent processing cost.
Description
Technical field
The present invention relates to the communication technology more particularly to a kind of circuit emulation service clock synchronization detecting methods and device.
Background technique
With the continuous development of the communication technology, network data transmission and friendship mainly will be carried out by basic unit of data packet
It changes, we term it packet switching network or packet networks (Packet Switched Network, abbreviation PSN).Circuit is imitative
True business (Circuit Emulation Service, abbreviation CES) is that traditional time division multiplexing (Time is carried on PSN
Division Multiplex, referred to as TDM) data technology.Use edge-to-edge pseudo-line simulation (Pseudo Wire
Emulation Edge-to-Edge, abbreviation PWE3) technology, by the way of circuit simulation, on PSN be plesiochronous digital system
Arrange (Plesiochronous Digital Hierarchy, abbreviation PDH)/synchronous digital system (Synchronous Digital
Hierarchy, abbreviation SDH) business data flow provides transparent transmission end to end.
Now net requires whole network clock synchronous when disposing CES, i.e. CES source, CES access side gusset and CES egress clock
It must synchronize, otherwise will appear data packetloss leads to voice service flash.CES accesses side gusset such as PSN source network element
(Network Element, abbreviation NE) and PSN destination NE.Now networking scene is extremely complex in net, and centre may have SDH net
The transmission networks such as network, Microwave Net and the equipment of each producer, occur that CES business is impaired to ask because clock is asynchronous frequent occurrence
Topic.Generally, now net first disposes business, when occurring gradually positioning the environment of investigation network when business is impaired again, if eliminated
Environmental problem, then clock configuration is checked, if clock configuration is also correct, finally need to check using station test under correlate meter
The clock problem of whole net.
Fast method is not yet proposed at present to check whether CES clock synchronizes, and whole network clock stationary problem is checked
Time is long, at high cost, inefficiency, influences network O&M efficiency.
Summary of the invention
The embodiment of the present invention provides a kind of circuit emulation service clock synchronization detecting method and device, can not be by instrument
Also CES clock synchronization issue can be quickly checked, the cost of investigation CES clock synchronization issue is reduced, improves network O&M efficiency.
In a first aspect, a kind of circuit emulation service clock synchronization detecting method is provided, including：
Obtain the first CES data and the 2nd CES data in network, wherein the first CES data are into PSN destination NE
Jitter cache before data, the 2nd CES data be PSN destination NE jitter cache export data；
It detects the first CES data and whether the clock frequency of the 2nd CES data is synchronous.
Implementation with reference to first aspect, in a first possible implementation of that first aspect, above-mentioned acquisition network
In the first CES data and the 2nd CES data, specifically include：The revolution of first CES data ring is sent to the first of PSN source NE to tremble
In dynamic caching；The revolution of 2nd CES data ring is sent in the second jitter cache of PSN source NE.
With reference to first aspect or first aspect the first possible implementation, in second of first aspect possible reality
In existing mode, in above-mentioned acquisition network before the first CES data and the 2nd CES data, further include：Configure sense channel, the inspection
It includes the first loopback and the first jitter cache corresponding with the first loopback and the second loopback and corresponding with the second loopback for surveying channel
The second jitter cache, wherein the first loopback for loopback forward the first CES data, the second loopback for loopback forwarding second
CES data.
With reference to first aspect or first aspect the first to second of any possible implementation, in first aspect
In three kinds of possible implementations, above-mentioned configuration sense channel, including：First loopback is set in PSN destination NE, and
The first jitter cache corresponding with the first loopback is set in PSN source NE；Second loopback is set in PSN destination NE, and
The second jitter cache corresponding with the second loopback is set in PSN source NE.
With reference to first aspect or first aspect the first to the third any possible implementation, in first aspect
In four kinds of possible implementations, above-mentioned setting sense channel, including：The first loopback is set in PSN source NE, and in PSN
The first jitter cache corresponding with the first loopback is set in source NE；The second loopback is set in PSN destination NE, and in PSN
The second jitter cache corresponding with the second loopback is set in source NE.
With reference to first aspect or first aspect the first to the 4th kind of any possible implementation, in first aspect
In five kinds of possible implementations, whether above-mentioned the first CES data of detection and the clock frequency of the 2nd CES data are synchronous, including：
Data are extracted from the first jitter cache and the second jitter cache with the equipment clock frequency of PSN source NE；The first shake of detection
The waterline position of caching and the second jitter cache；Difference according to the first jitter cache and the waterline position of the second jitter cache is true
Whether fixed first CES data and the clock frequency of the 2nd CES data are synchronous.
With reference to first aspect or first aspect the first to the 5th kind of any possible implementation, in first aspect
In six kinds of possible implementations, the above-mentioned difference according to the first jitter cache and the waterline position of the second jitter cache determines
Whether one CES data and the clock frequency of the 2nd CES data are synchronous, including：If the first jitter cache and the second jitter cache
The difference of waterline position remains unchanged, it is determined that the clock rate synchronization of the first CES data and the 2nd CES data；If first trembles
The difference of the waterline position of dynamic caching and the second jitter cache changes, it is determined that the first CES data and the 2nd CES data
Clock frequency is asynchronous.
Second aspect provides a kind of circuit emulation service clock sync detection device, including：
Obtain module, for obtaining the first CES data and the 2nd CES data in network, wherein the first CES data be into
Enter the data before the jitter cache of PSN destination NE, the number that the jitter cache that the 2nd CES data are PSN destination NE exports
According to；
Detection module, it is whether synchronous for detecting the first CES data and the clock frequency of the 2nd CES data.
In conjunction with the implementation of second aspect, in second aspect in the first possible implementation, above-mentioned acquisition module
It is specifically used for：The revolution of first CES data ring is sent in the first jitter cache of PSN source NE；2nd CES data ring is turned round
It is sent in the second jitter cache of PSN source NE.
In conjunction with second aspect or second aspect the first possible implementation, in second of second aspect possible reality
In existing mode, above-mentioned apparatus further includes：Configuration module, for configuring sense channel, the sense channel include the first loopback and with
Corresponding first jitter cache of first loopback and the second loopback and the second jitter cache corresponding with the second loopback, the first ring
It is back to loopback and forwards the first CES data, the second loopback forwards the 2nd CES data for loopback.
In conjunction with second aspect or second aspect the first to second of any possible implementation, in second aspect
In three kinds of possible implementations, above-mentioned configuration module is specifically used for：The first loopback is set in PSN destination NE, and in PSN
The first jitter cache corresponding with the first loopback is set in source NE；The second loopback is set in PSN destination NE, and in PSN
The second jitter cache corresponding with the second loopback is set in source NE.
In conjunction with second aspect or second aspect the first to the third any possible implementation, in second aspect
In four kinds of possible implementations, above-mentioned configuration module is specifically used for：First loopback is set in PSN source NE, and in the source PSN
Hold setting the first jitter cache corresponding with the first loopback in NE；Second loopback is set in PSN destination NE, and in the source PSN
Hold setting the second jitter cache corresponding with the second loopback in NE.
In conjunction with second aspect or second aspect the first to the 4th kind of any possible implementation, in second aspect
In five kinds of possible implementations, above-mentioned detection module is specifically used for：It is shaken with the equipment clock frequency of PSN source NE from first
Data are extracted in caching and the second jitter cache；Detect the waterline position of the first jitter cache and the second jitter cache；According to
The difference of the waterline position of one jitter cache and the second jitter cache determines the clock frequency of the first CES data and the 2nd CES data
Whether rate synchronizes.
In conjunction with second aspect or second aspect the first to the 5th kind of any possible implementation, in second aspect
In six kinds of possible implementations, above-mentioned detection module is specifically used for：If the waterline of the first jitter cache and the second jitter cache
The difference of position remains unchanged, it is determined that the clock rate synchronization of the first CES data and the 2nd CES data；If the first shake is slow
It deposits and changes with the difference of the waterline position of the second jitter cache, it is determined that the clock of the first CES data and the 2nd CES data
Frequency is asynchronous.
Circuit emulation service clock synchronization detecting method and device provided in an embodiment of the present invention, by comparing PSN purpose
It holds the clock frequency of the data before and after the jitter cache of NE to determine whether CES clock synchronizes, can quickly detect CES data two
Whether end clock synchronizes, and finds the problem in advance, reduces subsequent processing cost.Even if being asked in regular traffic operational process
It inscribes, what the business caused by clock performance difference that can also quickly exclude in the case where being tested without lower station pocket watch was damaged can
Can, issue handling efficiency is improved, human cost is reduced, can effectively improve network O&M efficiency.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of the present invention or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is of the invention one
A little embodiments for those of ordinary skill in the art without creative efforts, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the schematic diagram according to the transmission CES data packet of the relevant technologies；
Fig. 2 is a kind of flow chart of CES clock synchronization detecting method provided in an embodiment of the present invention；
Fig. 3 is a kind of sense channel configuration schematic diagram provided in an embodiment of the present invention；
Fig. 4 is another sense channel configuration schematic diagram provided in an embodiment of the present invention；
Fig. 5 is a kind of CES clock sync detection device schematic diagram provided in an embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained under that premise of not paying creative labor, shall fall within the protection scope of the present invention.
The embodiment of the present invention can be applied to be centered around on PSN carry out TDM circuit exchange business data penetration transmission and
The network interoperability of later evolution.In terms of TDM business transparent transmission standard formulation, internet engineering task group (Internet
Engineering Task Force, abbreviation IETF) PWE3 working group plays a leading role, the TDM business transparent transmission standard formulated
It is the most complete, therefore become the field mainstream standard, it will briefly be introduced by the analysis to TDM PWE3 technical solution below
TDM Signal Transparent Transmission Technology.
Pseudo-wire (Pseudo Wire, abbreviation PW) is a kind of the key element of one artificial service to be transported from one by PSN
Battalion quotient's edge device (Provider Edge, abbreviation PE) is carried to the mechanism of another or a number of other PEs.Pass through PSN network
On a tunnel multiple business is emulated, PSN can transmit the payload user data of multiple business.We are in this scheme
The tunnel definition used is pseudo-wire (PW).The internal data traffic that PW is carried is sightless to core network, it may also be said to
Core network is transparent to customer edge (Customer Edge, abbreviation CE) data flow.
Fig. 1 is according to the schematic diagram of the transmission CES data packet of the relevant technologies, as shown in Figure 1, TDM circuit artificial service is real
Now mode is：TDM business datum is imitated with special circuit in the source network element (Network Element, abbreviation NE) of PSN
True heading is packaged, and frame format information, warning information, the signaling information of TDM business datum are carried in specific message head
And synchronous timing information, the message after encapsulation are known as PW message (i.e. CES data packet), then are carried out with transport protocol to PW message
Corresponding PSN is passed through in carrying, after reaching PW tunnel exit, executes the process of decapsulation again in the destination NE of PSN, then
It rebuilds TDM circuit and exchanges business data flow.
PW message passes through after PSN arrival destination NE, and message is not waited there may be arrival time interval and packet out-ordering
The case where, in order to guarantee that TDM business data flow can be rebuild on destination NE, need by the smooth PW data of jitter cache technology
The time interval of packet carries out permutatation to out-of-order PW message.As shown in Figure 1, jitter cache (the Jitter of PSN destination NE
Buffer, abbreviation JB) JB_C is exactly the time interval for reaching the CES data packet of destination NE for smoothly passing through PSN, and to unrest
The CES data packet of sequence carries out permutatation, then sends destination NE's for the CES data after JB_C progress jitter cache
Upstream device.
Fig. 2 is a kind of flow chart of CES clock synchronization detecting method provided in an embodiment of the present invention, as shown in Fig. 2, this reality
The CES clock synchronization detecting method for applying example offer, may include steps of：
S21 obtains the first CES data and the 2nd CES data in network, wherein the first CES data are into PSN purpose
Hold the data before the jitter cache of NE, the data that the jitter cache that the 2nd CES data are PSN destination NE exports；
S22, detects the first CES data and whether the clock frequency of the 2nd CES data is synchronous.
In the present embodiment, the schematic diagram for being referred to transmission CES data packet shown in FIG. 1 schematically illustrates.
It is understood that according to the principle of jitter cache technology in CES standard it is found that being trembled in PSN destination NE
Data before dynamic caching, clock frequency do not change still, remain as the clock frequency f of CES data source0.However, in PSN
Destination NE carries out the data after jitter cache, and clock frequency is just changed, and the equipment of NE is held for the purpose of changing
Clock frequency f2.If guaranteeing CES data clock rate synchronization, it is required that f0=f2, i.e. f0And f2Difference it is almost nil when,
Illustrate that CES data clock rate is synchronous in network, conversely, then asynchronous.
In the present embodiment, it is determined by the clock frequency of the data before and after the jitter cache of comparison PSN destination NE
Whether CES clock synchronizes, and can quickly detect whether CES data both ends clock synchronizes, and finds the problem in advance, reduces subsequent place
Manage cost.It, can also be in the case where being tested without lower station pocket watch even if going wrong in regular traffic operational process
The impaired possibility of business caused by clock performance difference is quickly excluded, issue handling efficiency is improved, reduces human cost, it can be effective
Improve network O&M efficiency.
Embodiment in order to more clearly describe the present invention will be described in further details below by specific example.
In embodiments of the present invention, in order to obtain the first CES data and the 2nd CES data, CES can be configured in a network
Data Detection channel.Then the first CES data and the 2nd CES data in network are obtained by the CES Data Detection channel configured,
And finally determine whether the first CES data and the 2nd CES data clock rate are synchronous.
Specifically, Fig. 3 is a kind of sense channel configuration schematic diagram provided in an embodiment of the present invention, as shown in figure 3, can be
Loopback point (loopback point, abbreviation LP) LP1 and LP2 is respectively configured on PSN destination NE, and divides in PSN source NE
It Pei Zhi not jitter cache JB_A and JB_B corresponding with LP1 and LP2.In turn, CES data herein can be replicated at LP1 simultaneously
Loopback is forwarded to the JB_A of source NE, realizes the acquisition of the first CES data, while CES data herein can be replicated at LP2
And loopback is forwarded to the JB_B of source NE, realizes the acquisition of the 2nd CES data.
Fig. 4 is another sense channel configuration schematic diagram provided in an embodiment of the present invention, as shown in figure 4, can be in the source PSN
LP1 is configured on the NE of end, LP2 is configured on PSN destination NE, and is respectively configured in PSN source NE corresponding with LP1 and LP2
Jitter cache JB_A and JB_B.In turn, the JB_A that CES data and loopback herein are forwarded to source NE can be replicated at LP1,
It realizes the acquisition of the first CES data, while the JB_ that CES data and loopback herein are forwarded to source NE can be replicated at LP2
B realizes the acquisition of the 2nd CES data.
Because CES data have already been through JB_C when reaching at LP2, according to the principle of jitter cache technology in CES standard
It is found that the clock frequency of the CES data of loopback forwarding is changed here, that is, the equipment clock frequency of NE is held for the purpose of changing
Rate f2.And the CES data at LP1, jitter cache processing is carried out because not yet passing through JB_C, here the CES data of loopback forwarding
Clock frequency do not change, remain as the clock frequency f of CES data source0。
Further, the JB_A of source NE receives the clock frequency f that the rate of data is CES data source0, source NE's
The equipment clock frequency f of NE is held for the purpose of the rate of JB_B reception data2.In general, the device frequency f of PSN source NE1With PSN mesh
End NE equipment clock frequency f2It is identical, therefore can be with the equipment clock frequency f of source NE1Simultaneously from JB_A and JB_
Remove data in B, and the size of memory space that real-time detection JB_A and JB_B have been used.Wherein, JB_A and JB_B be
The size of the memory space used can pass through waterline (waterline) position w of JB_A and JB_B1And w2It determines.
Obviously, it is f that JB_A, which receives the rate of data,0, the rate for removing data is also f1, and JB_B receives the rate of data
For f2, the rate for removing data is f1, then have：
If f0=f2, and f1=f2, then JB_A and JB_B and with identical rate receiving data and remove data, root
According to the principle of jitter cache technology it is found that the size for the memory space that JB_A and JB_B have been used will not change, i.e. JB_
The difference of the waterline position of A and JB_B is held essentially constant；
If f0>f2, and f1=f2, JB_B with identical rate receiving data and removes data at this time, therefore JB_B has made
The size of memory space will not change；And JB_A can be with biggish rate receiving data, but with the shifting of lesser rate
Except data, therefore the size of memory space that JB_A has been used can become larger, correspondingly, the difference of the waterline position of JB_A and JB_B
It will change；
If f0<f2, and f1=f2, JB_B with identical rate receiving data and removes data at this time, therefore JB_B has made
The size of memory space will not change；And JB_A can be with lesser rate receiving data, but with the shifting of biggish rate
Except data, therefore the size of memory space that JB_A has been used can become smaller, likewise, the difference of the waterline position of JB_A and JB_B
Also it can change.
It, can be according to the waterline position w of JB_A and JB_B based on above-mentioned1And w2Difference determine the first CES data and second
Whether the clock frequency of CES data synchronizes, i.e., if the difference of the waterline position of the first jitter cache and the second jitter cache is protected
It holds constant, it is determined that the clock rate synchronization of the first CES data and the 2nd CES data；If the first jitter cache and second is trembled
The difference of the waterline position of dynamic caching changes, it is determined that the first CES data are different with the clock frequency of the 2nd CES data
Step.
When the difference of the first jitter cache and the waterline position of the second jitter cache is held essentially constant, it is believed that no
Will appear data packetloss leads to voice service flash, that is, determines that CES clock is synchronous.When the first jitter cache and second are trembled
When the difference holding of the waterline position of dynamic caching changes, so that it may think that will appear data packetloss leads to voice service flash
The problems such as, that is, determine that CES clock is asynchronous, at this time should also report and alarm information in time, so as to staff can in time into
To repair network, guarantee business is normally carried out for row adjustment.
It is understood that working as f0>f2, and f1=f2When, if the waterline position that original state is JB_A is higher than JB_B's
Waterline position, then the difference of the waterline position of JB_A and JB_B can be increasing；If original state is the waterline position of JB_A
Waterline position lower than JB_B, then the difference of the waterline position of JB_A and JB_B is initially smaller and smaller, until the waterline of JB_A
After position is higher by the waterline position of JB_B, the difference of the waterline position of JB_A and JB_B again can be increasing；If original state
Equal for the waterline position of JB_A and the waterline position of JB_B, then the difference of the waterline position of JB_A and JB_B also can be increasingly
Greatly.
Likewise, f0<f2, and f1=f2When, if original state is that the waterline position of JB_A is higher than the waterline position of JB_B
It sets, then the difference of the waterline position of JB_A and JB_B is initially smaller and smaller, until the low water of JB_B excessively of the waterline position of JB_A
After line position, the difference of the waterline position of JB_A and JB_B again can be increasing；If original state is the waterline position of JB_A
Waterline position lower than JB_B, then the difference of the waterline position of JB_A and JB_B can be increasing；If original state is JB_A
Waterline position it is equal with the waterline position of JB_B, then the difference of the waterline position of JB_A and JB_B also can be increasing.
It will also be appreciated that in practical applications, being the CES clock stringent synchronization that can not accomplish the whole network, can permit
There is a certain error, there is corresponding error threshold values.When the difference of the first jitter cache and the waterline position of the second jitter cache
When fluctuating in a certain range, i.e. the variation of very little has occurred in the difference of the two, as long as no more than the corresponding water of error threshold values
The difference of line position, it is considered that the difference of the waterline position of the first jitter cache and the second jitter cache is kept not substantially
Become, that is, thinks that CES clock is synchronous.
Further it will be understood that in the present embodiment, it can also be with the equipment clock frequency f of PSN destination NE2Together
When remove data from JB_A and JB_B, and the size of memory space that real-time detection JB_A and JB_B have been used.It determines
Principle be it is identical, details are not described herein again.Furthermore it is also possible to understand, the rate that data are removed from JB_A and JB_B is answered
This is equal to any reception data rate of JB_A or JB_B, otherwise may cause one of JB_A and JB_B data overflow or nothing
Data storage, and then can not judge the size for the memory space that JB_A or JB_B have been used.
Finally it is worth mentioning that, in embodiments of the present invention, if sense channel configuration schematic diagram according to Fig.3, into
The sense channel of row CES data configures, it is ensured that and the first CES data and the 2nd CES data pass through identical network transmission path,
Ensure that the indexs such as the first CES data and delay and shake in the network transmission environment of the 2nd CES data are consistent, makes testing result
It is more acurrate.
CES clock synchronization detecting method provided in an embodiment of the present invention is configured by two different locations in a network
Loopback, before the jitter cache of an end equipment that PSN mesh is entered in CES data, one enters PSN destination in CES data
After the jitter cache of equipment.It can guarantee that the CES data an of loopback are sent using original clock frequency in this way, a ring
The CES data returned are sent using the clock frequency of the end equipment of PSN mesh.When the CES data transmitted in network pass through each loopback
Shi Douhui copies a business datum and back sends, this two CES data are sent to by identical or different network path
In two jitter caches of PSN source equipment, reuses identical clock frequency and extract data from two jitter caches, and is real
When the size of memory space that has respectively used of two jitter caches of detection, respectively used according to two jitter caches
The variation tendency of the difference of memory space, determines whether two CES data clocks synchronize.The detection method can be not necessarily to lower station
Pocket watch quickly excludes the impaired possibility of business caused by clock performance difference in the case where being tested, improve issue handling efficiency,
Human cost is reduced, can effectively improve network O&M efficiency.
Fig. 5 is a kind of CES clock sync detection device schematic diagram provided in an embodiment of the present invention, which can use
In the CES clock synchronization detecting method for realizing that embodiment illustrated in fig. 2 of the present invention provides, details are not described herein again.As shown in figure 5, should
Device includes obtaining module 51 and detection module 52.
Wherein, obtaining module 51 can be used for obtaining the first CES data and the 2nd CES data in network, wherein first
CES data are into the data before the jitter cache of PSN destination NE, and the shake that the 2nd CES data are PSN destination NE is slow
Deposit the data of output；Detection module 52 can be used for detecting the first CES data and whether the clock frequency of the 2nd CES data is same
Step.
It is trembled specifically, obtaining module 51 and specifically can be used for the first CES data ring revolution being sent to the first of PSN source NE
In dynamic caching；The revolution of 2nd CES data ring is sent in the second jitter cache of PSN source NE.
In practical applications, which further includes configuration module 53, can be used for configuring sense channel, the sense channel packet
It includes the first loopback and and corresponding first jitter cache of the first loopback and the second loopback and corresponding with the second loopback second is trembled
Dynamic caching.Wherein, the first loopback can be used for loopback the first CES data of forwarding, and the second loopback can be used for loopback forwarding second
CES data.
As an alternative embodiment, configuration module 53 can be arranged the first loopback in PSN destination NE, and
Corresponding with the first loopback the first jitter cache is set in PSN source NE, the second loopback is set in PSN destination NE, and
The second jitter cache corresponding with the second loopback is set in PSN source NE.
As another optional embodiment, specifically the first ring can also be arranged in PSN source NE in configuration module 53
It returns, and the first jitter cache corresponding with the first loopback is set in PSN source NE；The second ring is set in PSN destination NE
It returns, and the second jitter cache corresponding with the second loopback is set in PSN source NE.
Further, as a kind of preferable embodiment, in practical applications, detection module 52 specifically can be used for：
Data are extracted from the first jitter cache and the second jitter cache with the equipment clock frequency of PSN source NE；The first shake of detection
The waterline position of caching and the second jitter cache；Difference according to the first jitter cache and the waterline position of the second jitter cache is true
Whether fixed first CES data and the clock frequency of the 2nd CES data are synchronous.
Further, in practical applications, detection module 52 specifically can be also used for：If the first jitter cache and second is trembled
The difference of the waterline position of dynamic caching remains unchanged, it is determined that the clock rate synchronization of the first CES data and the 2nd CES data；
If the difference of the waterline position of the first jitter cache and the second jitter cache changes, it is determined that the first CES data and second
The clock frequency of CES data is asynchronous.
CES clock sync detection device provided in this embodiment may be implemented what embodiment illustrated in fig. 2 of the present invention provided
CES clock synchronization detecting method, it is similar that the realization principle and technical effect are similar, and details are not described herein again.
Those of ordinary skill in the art will appreciate that：Realize that all or part of the steps of above-mentioned each method embodiment can lead to
The relevant hardware of program instruction is crossed to complete.Program above-mentioned can be stored in a computer readable storage medium.The journey
When being executed, execution includes the steps that above-mentioned each method embodiment to sequence；And storage medium above-mentioned includes：ROM, RAM, magnetic disk or
The various media that can store program code such as person's CD.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, those skilled in the art should understand that：Its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (12)
1. a kind of circuit emulation service clock synchronization detecting method, which is characterized in that including：
Obtain the first circuit emulation service CES data and the 2nd CES data in network, wherein the first CES data are to enter
Data before the jitter cache of packet network PSN destination network element NE, the 2nd CES data are the PSN destination
The data of the jitter cache output of NE；
It detects the first CES data and whether the clock frequency of the 2nd CES data is synchronous；
Wherein, the first CES data and the 2nd CES data in the acquisition network, specifically include：
First CES data ring revolution is sent in the first jitter cache of PSN source NE；
2nd CES data ring revolution is sent in the second jitter cache of the PSN source NE.
2. the method according to claim 1, wherein the first CES data and the 2nd CES number in the acquisition network
According to before, further include：
Sense channel is configured, the sense channel includes that the first loopback and first shake corresponding with first loopback are slow
It deposits and the second loopback and second jitter cache corresponding with second loopback, first loopback turns for loopback
Send out the first CES data described, second loopback forwards the 2nd CES data for loopback.
3. according to the method described in claim 2, it is characterized in that, the configuration sense channel, including：
First loopback is set in the PSN destination NE, and setting and first loopback in the PSN source NE
Corresponding first jitter cache；
Second loopback is set in the PSN destination NE, and setting and second loopback in the PSN source NE
Corresponding second jitter cache.
4. according to the method described in claim 2, it is characterized in that, the setting sense channel, including：
First loopback is set in the PSN source NE, and setting and first loopback pair in the PSN source NE
First jitter cache answered；
Second loopback is set in the PSN destination NE, and setting and second loopback in the PSN source NE
Corresponding second jitter cache.
5. method according to claim 1-4, which is characterized in that described to detect the first CES data and institute
Whether the clock frequency for stating the 2nd CES data synchronizes, including：
Number is extracted from first jitter cache and second jitter cache with the equipment clock frequency of the PSN source NE
According to；
Detect the waterline position of first jitter cache and second jitter cache；
The first CES data are determined according to the difference of first jitter cache and the waterline position of second jitter cache
It is whether synchronous with the clock frequency of the 2nd CES data.
6. according to the method described in claim 5, it is characterized in that, described tremble according to first jitter cache and described second
The difference of the waterline position of dynamic caching determines whether the first CES data and the clock frequency of the 2nd CES data are synchronous,
Including：
If the difference of the waterline position of first jitter cache and second jitter cache remains unchanged, it is determined that described
The clock rate synchronization of one CES data and the 2nd CES data；
If the difference of the waterline position of first jitter cache and second jitter cache changes, it is determined that described
The clock of one CES data and the 2nd CES data is asynchronous.
7. a kind of circuit emulation service clock sync detection device, which is characterized in that including：
Module is obtained, for obtaining the first circuit emulation service CES data and the 2nd CES data in network, wherein described first
CES data are into the data before the jitter cache of packet network PSN destination network element NE, and the 2nd CES data are
The data of the jitter cache output of the PSN destination NE；
Detection module, it is whether synchronous for detecting the first CES data and the clock frequency of the 2nd CES data；
The acquisition module is specifically used for：
First CES data ring revolution is sent in the first jitter cache of PSN source NE；
2nd CES data ring revolution is sent in the second jitter cache of the PSN source NE.
8. device according to claim 7, which is characterized in that further include：
Configuration module, for configuring sense channel, the sense channel includes the first loopback and corresponding with first loopback
First jitter cache and the second loopback and second jitter cache corresponding with second loopback, described first
Loopback forwards the first CES data for loopback, and second loopback forwards the 2nd CES data for loopback.
9. device according to claim 8, which is characterized in that the configuration module is specifically used for：
First loopback is set in the PSN destination NE, and setting and first loopback in the PSN source NE
Corresponding first jitter cache；
Second loopback is set in the PSN destination NE, and setting and second loopback in the PSN source NE
Corresponding second jitter cache.
10. device according to claim 8, which is characterized in that the configuration module is specifically used for：
First loopback is set in the PSN source NE, and setting and first loopback pair in the PSN source NE
First jitter cache answered；
Second loopback is set in the PSN destination NE, and setting and second loopback in the PSN source NE
Corresponding second jitter cache.
11. according to any device of claim 7-10, which is characterized in that the detection module is specifically used for：
Number is extracted from first jitter cache and second jitter cache with the equipment clock frequency of the PSN source NE
According to；
Detect the waterline position of first jitter cache and second jitter cache；
The first CES data are determined according to the difference of first jitter cache and the waterline position of second jitter cache
It is whether synchronous with the clock frequency of the 2nd CES data.
12. device according to claim 11, which is characterized in that the detection module is specifically used for：
If the difference of the waterline position of first jitter cache and second jitter cache remains unchanged, it is determined that described
The clock rate synchronization of one CES data and the 2nd CES data；
If the difference of the waterline position of first jitter cache and second jitter cache changes, it is determined that described
The clock frequency of one CES data and the 2nd CES data is asynchronous.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1946017A (en) * | 2006-10-09 | 2007-04-11 | 华为技术有限公司 | Method and system for clock synchronizing of transmission end and receiving end in package switching network |
| CN101895364A (en) * | 2010-06-25 | 2010-11-24 | 中兴通讯股份有限公司 | Method and device for transmitting time division multiplexing (TDM) service |
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| CN1281036C (en) * | 2003-08-15 | 2006-10-18 | 上海贝尔阿尔卡特股份有限公司 | Packet switching network distributed adaptive dither buffer adjusting method |
| CN1320805C (en) * | 2003-09-17 | 2007-06-06 | 上海贝尔阿尔卡特股份有限公司 | Regulating method of adaptive scillation buffer zone of packet switching network |
| CN101640578A (en) * | 2009-08-25 | 2010-02-03 | 北京邮电大学 | TDM service clock recovery method for packet transport network |
| CN102340365B (en) * | 2010-07-27 | 2014-06-11 | 中兴通讯股份有限公司 | Timestamp-based clock recovery method and device |
| CN104486020B (en) * | 2014-12-12 | 2017-04-12 | 成都朗锐芯科技发展有限公司 | Network data counting method for clock recovery |
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| CN1946017A (en) * | 2006-10-09 | 2007-04-11 | 华为技术有限公司 | Method and system for clock synchronizing of transmission end and receiving end in package switching network |
| CN101895364A (en) * | 2010-06-25 | 2010-11-24 | 中兴通讯股份有限公司 | Method and device for transmitting time division multiplexing (TDM) service |
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