CN104393170A - Preparation method of three-dimensional high-density resistance transformation type memorizer - Google Patents
Preparation method of three-dimensional high-density resistance transformation type memorizer Download PDFInfo
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- CN104393170A CN104393170A CN201410557993.2A CN201410557993A CN104393170A CN 104393170 A CN104393170 A CN 104393170A CN 201410557993 A CN201410557993 A CN 201410557993A CN 104393170 A CN104393170 A CN 104393170A
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Abstract
Disclosed in the invention is a preparation method of a three-dimensional high-density resistance transformation type memorizer. The preparation method comprises the following steps: preparing a substrate; coating a photoresist on the substrate and carrying out photoetching, exposure and development on the photoresist to form an electrode pattern; carrying out noble electrode electron beam evaporation on the substrate with the electrode pattern; stripping the photoresist and the metal arranged on the photoresist to form a noble electrode; spinning and coating an electron beam photoresist HSQ on the substrate with the noble electrode and carrying out electron beam exposure; coating a photoresist and carrying out photoetching, exposure and development on the photoresist so as to form an active electrode pattern; carrying out active electrode electron beam evaporation on the substrate with the active electrode pattern; stripping the photoresist and the metal arranged on the photoresist to form an active electrode; spinning and coating an electron beam photoresist HSQ on the substrate with the active electrode and carrying out electron beam exposure; coating a photoresist and carrying out photoetching, exposure and development on the photoresist to form an electrode pattern; carrying out noble electrode electron beam evaporation on the substrate with the electrode pattern; and stripping the photoresist and the metal arranged on the photoresist to form a noble electrode.
Description
Technical field
The present invention relates to nano electron device and technical field of nano-processing, particularly relate to a kind of manufacture method of high storage density electric resistance changing memory.
Background technology
Along with the development of large data and cloud computing, the demand of highdensity Nonvolatile semiconductor memory devices is also more and more urgent.In order to realize high-density city, first it is considered that by device size scaled down, the amount of information that unit are can store is increased with this, but, along with microelectronic processing technology approaches its physics limit, the simple satisfied higher storage density that reduces of device area that relies on requires to have become very difficult.Another way promoting storage density is exactly the Nonvolatile Memory Device that exploitation has multilevel storage ability, but research shows, often retentivity is bad to have " intermediate state " of the non-volatile device of multilevel storage, easily cause device to store the loss of information, moreover multilevel storage is difficult to significantly promote storage density.Traditional electric resistance changing memory device is all on the backing material of two dimension arrangement, namely substrate only has one deck memory device, if the stacking of different layers memory can be realized in the third dimension, and effectively can realize the operations such as the gating of each device, programming, erasing and reading, so this three-dimensional stacked method can promote the density of memory widely.
At present for electric resistance changing memory, realize three-dimensional stacked scheme and mainly concentrate on cross array structure, because the crosspoint place of mutually perpendicular two metal wires both can form memory device unit, this two metal line can serve as again place one arrange or the addressing of a line memory device, programming, reading line.The memory device ratio directly realizing one deck crossed array on smooth substrate is easier to realize, but increasing along with the number of plies, and evenness variation can bring problems to follow-up technique, causes the instability of structure and the inefficacy of device.In order to increase evenness, technique can realize metal nanometer line " is imbedded " in dielectric layer, making nano wire consistent with dielectric layer height, then deposit functional layers, the like, make every one deck can form a smooth structure.Although this mode solves the problem of evenness, process costs promotes greatly, and the technique of " planarization " can produce certain harmful effect to device.The three-dimensional integrated morphology so realizing a kind of low-cost high-density becomes particularly important.
Summary of the invention
(1) technical problem that will solve
The present invention mainly provides a kind of three-dimensional resistance of preparing to change the method for memory, prepares that three-dimensional high-density memory flow process is complicated, uncontrollable, high in cost of production series of problems at present to solve.
(2) technical scheme
For achieving the above object, the invention provides a kind of preparation method of three-dimensional high-density electric resistance changing memory, comprising:
Step 1: substrate preparation;
Step 2: apply photoresist on substrate, carries out photoetching, exposure and development to photoresist and forms electrode pattern;
Step 3: electron beam evaporation inert electrode on the substrate forming electrode pattern;
Step 4: stripping photoresist and on metal, formed inert electrode;
Step 5: spin coating electron beam resist HSQ electron beam exposure on the substrate forming inert electrode;
Step 6: coating photoresist, carries out photoetching, exposure and development to photoresist and forms active electrode figure;
Step 7: electron beam evaporation active electrode on the substrate forming active electrode figure;
Step 8: stripping photoresist and on metal, formed active electrode;
Step 9: spin coating electron beam resist HSQ electron beam exposure on the substrate forming active electrode;
Step 10: coating photoresist, carries out photoetching, exposure and development to photoresist and forms electrode pattern;
Step 11: electron beam evaporation inert electrode on the substrate forming electrode pattern;
Step 12: stripping photoresist and on metal, formed inert electrode.
In such scheme, substrate described in step 1 is the silicon chip having prepared medium of oxides layer, and this medium of oxides layer is high-temperature thermal oxidation silicon chip and being formed in oxygen atmosphere.
In such scheme, photoresist described in step 2 is 9920, and the electrode pattern of formation is of a size of 2 μm × 1 μm.
In such scheme, in step 3, electron beam evaporation inert electrode metal is platinum (Pt), thickness 70-80 nanometer.
In such scheme, peeling off reagent described in step 4 is acetone+ethanol.
In such scheme, the thickness of the electron beam resist of spin coating described in step 5 HSQ is 120 nanometers.
In such scheme, photoresist described in step 6 is 9920, and the electrode pattern of formation is of a size of 1mm × 2 μm.
In such scheme, active electrode described in step 7 is silver (Ag), and thickness is 80 nanometers.
In such scheme, peeling off reagent described in step 8 is acetone+ethanol.
In such scheme, the thickness of the electron beam resist of spin coating described in step 9 HSQ is 120 nanometers.
In such scheme, photoresist described in step 10 is 9920, and the electrode pattern of formation is of a size of 2 μm × 1 μm.
In such scheme, in step 11, electron beam evaporation inert electrode metal is platinum (Pt), thickness 80 nanometer.
In such scheme, peeling off reagent described in step 12 is acetone+ethanol.
(3) beneficial effect
As can be seen from technique scheme, the present invention has following beneficial effect:
1, the electric resistance changing memory with three-dimensional structure utilizing the present invention to prepare, while ensureing higher storage density, also possesses the advantages such as technique is simple, cost is low, controllability is good.
2, the present invention is utilized, the electric resistance changing memory that active electrode serves as anode can form the nano-filaments of metalline in the process that electric resistance changing occurs, low power consumption operation and multilevel storage can be realized by regulating the size of Limited Current, such devices has low operating voltage and read or write speed faster, and there is good device retention performance, there is very large application potential.
3, utilize the present invention, can obtain 3-dimensional multi-layered stacking electric resistance changing memory device, device fabrication process is simple, and cost is low workable, has realistic meaning for the correlative study of three-dimensional high-density electric resistance changing memory and application.
Accompanying drawing explanation
Fig. 1 is the method flow diagram preparing three-dimensional high-density electric resistance changing memory provided by the invention.
Fig. 2 is the schematic diagram of the three-dimensional high-density electric resistance changing memory prepared according to Fig. 1.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention by preparation layer of metal nano wire, spin coating one deck HSQ, prepare the mode of other layer of metal nano wire again, the array of the metal nanometer line of every one deck is all wrapped in HSQ, controls thickness by spin coating and can planarization be realized.HSQ is a kind of comparatively special Other substrate materials, in the process of spin coating, can well be coated on around metal nanometer line, and make surfacing, in addition, after electron beam exposure, HSQ will sex change, profit prepares the electric resistance changing memory with three-dimensional structure in this way while ensureing higher storage density, also possesses the advantages such as technique is simple, cost is low, controllability is good.
The electric resistance changing memory that this active electrode serves as anode can form the nano-filaments of metalline in the process that electric resistance changing occurs, low power consumption operation and multilevel storage can be realized by regulating the size of Limited Current, such devices has low operating voltage and read or write speed faster, and there is good device retention performance, there is very large application potential.
As shown in Figure 1, Fig. 1 is the method flow diagram preparing three-dimensional high-density electric resistance changing memory provided by the invention, and the method comprises the following steps:
Step 1: substrate preparation; Wherein substrate is the silicon chip having prepared medium of oxides layer, and this medium of oxides layer is high-temperature thermal oxidation silicon chip and being formed in oxygen atmosphere.
Embodiment of the present invention substrate used is 2 inch silicon wafer having formed substrate dielectric layer, and before formation substrate dielectric layer, silicon chip to carry out strict cleaning process, is specially: 2 inch silicon wafer are at sulfuric acid (H
2sO
4) and hydrogen peroxide (H
2o
2) solution in (both ratios are 7: 3) boil 30 minutes, temperature is 400 degrees Celsius, organics removal and metal impurities, then put into hydrofluoric acid (HF) and deionized water (DIW) rinsing, finally uses deionized water (DIW) to rinse.
Step 2: apply photoresist on substrate, carries out photoetching, exposure and development to photoresist and forms electrode pattern; Wherein photoresist adopts 9920, and spin coating thickness is 1.2 μm, 85 DEG C of hot plate bake 4.5 minutes, and adopt mask exposure, figure is the strip array of 2 μm × 1mm, 3.5 seconds time for exposure, then soaks 40 seconds in developing solution.
Step 3: electron beam evaporation inert electrode on the substrate forming electrode pattern; Wherein electron beam evaporation inert electrode metal is platinum (Pt), thickness 70-80 nanometer.
Step 4: stripping photoresist and on metal, formed inert electrode; Wherein peeling off reagent is acetone+ethanol, is specially and first soaks 5 minutes in acetone, have the place of photoresist and acetone to react and dissolved, and the metal be communicated with on photoresist is stripped together, embathes respectively after metal departs from ethanol and deionized water.
Step 5: spin coating electron beam resist HSQ electron beam exposure on the substrate forming inert electrode; Wherein the thickness of spin coating electron beam resist HSQ is 120 nanometers, and rotating speed is 7000 revs/min.
Step 6: coating photoresist, carries out photoetching, exposure and development to photoresist and forms active electrode figure; Wherein photoresist is 9920, and the electrode pattern of formation is of a size of 1mm × 2 μm, other conditional synchronization rapid 2.
Step 7: electron beam evaporation active electrode on the substrate forming active electrode figure; Wherein active electrode is silver (Ag), and thickness is 80 nanometers.
Step 8: stripping photoresist and on metal, formed active electrode; Wherein peeling off reagent is acetone+ethanol, other conditional synchronization rapid 4.
Step 9: spin coating electron beam resist HSQ electron beam exposure on the substrate forming active electrode; Wherein the thickness of spin coating electron beam resist HSQ is 120 nanometers, other conditional synchronization rapid 5.
Step 10: coating photoresist, carries out photoetching, exposure and development to photoresist and forms electrode pattern; Wherein photoresist is 9920, and the electrode pattern of formation is of a size of 2 μm × 1 μm, other conditional synchronization rapid 2.
Step 11: electron beam evaporation inert electrode on the substrate forming electrode pattern; Wherein electron beam evaporation inert electrode metal is platinum (Pt), thickness 80 nanometer, other conditional synchronization rapid 3.
Step 12: stripping photoresist and on metal, formed inert electrode; Wherein peeling off reagent is acetone+ethanol, other conditional synchronization rapid 4.
Embodiment
The present embodiment selects 2 inch silicon wafer, and substrate dielectric layer selects silica, and active electrode adopts silver (Ag), and inert electrode adopts platinum (Pt).
Standard cleaning process described above is carried out to the silicon chips of 2 inches, removes surface and oil contaminant and metallic pollution.
Silicon chip after cleaning oxidation processes in high temperature oxidation furnace, surface forms insulating oxide silicon, and as substrate dielectric layer, thickness is 100 ran.
On the substrate of long good silica, photoetching forms inert electrode figure spin coating photoresist 9920, rotating speed 7000 rpms, spin coating one minute, about 1.2 microns of thickness, and the exposure in 4.5 minutes of 85 DEG C of hot plate bake selects vacuum exposure pattern, 3.5 seconds time for exposure.Then develop 40 seconds in the developer solution of 9920 correspondences, clean in deionized water after forming figure, electron beam evaporation growth Pt after moisture evaporation, thickness is 70 nanometers, peel off in acetone soln subsequently, spin coating HSQ electron beam exposure afterwards, rotating speed is 7000 rpms, then alignment forms the figure of active electrode, the top electrode active metal silver (Ag) of electron-beam evaporation 80 nanometer thickness, spin coating HSQ electron beam exposure again after stripping, alignment forms the electrode of one deck topmost again, evaporation inert electrode Pt metal, thickness is 70 nanometers, 5 minutes are soaked in acetone after taking-up, embathe with ethanol again after metal-stripping is clean.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. a preparation method for three-dimensional high-density electric resistance changing memory, is characterized in that, comprising:
Step 1: substrate preparation;
Step 2: apply photoresist on substrate, carries out photoetching, exposure and development to photoresist and forms electrode pattern;
Step 3: electron beam evaporation inert electrode on the substrate forming electrode pattern;
Step 4: stripping photoresist and on metal, formed inert electrode;
Step 5: spin coating electron beam resist HSQ electron beam exposure on the substrate forming inert electrode;
Step 6: coating photoresist, carries out photoetching, exposure and development to photoresist and forms active electrode figure;
Step 7: electron beam evaporation active electrode on the substrate forming active electrode figure;
Step 8: stripping photoresist and on metal, formed active electrode;
Step 9: spin coating electron beam resist HSQ electron beam exposure on the substrate forming active electrode;
Step 10: coating photoresist, carries out photoetching, exposure and development to photoresist and forms electrode pattern;
Step 11: electron beam evaporation inert electrode on the substrate forming electrode pattern;
Step 12: stripping photoresist and on metal, formed inert electrode.
2. the preparation method of three-dimensional high-density electric resistance changing memory according to claim 1, it is characterized in that, substrate described in step 1 is the silicon chip having prepared medium of oxides layer, and this medium of oxides layer is high-temperature thermal oxidation silicon chip and being formed in oxygen atmosphere.
3. the preparation method of three-dimensional high-density electric resistance changing memory according to claim 1, is characterized in that, photoresist described in step 2 is 9920, and the electrode pattern of formation is of a size of 2 μm × 1 μm.
4. the preparation method of three-dimensional high-density electric resistance changing memory according to claim 1, is characterized in that, in step 3, electron beam evaporation inert electrode metal is platinum (Pt), thickness 70-80 nanometer.
5. the preparation method of three-dimensional high-density electric resistance changing memory according to claim 1, is characterized in that, peeling off reagent described in step 4 is acetone+ethanol.
6. the preparation method of three-dimensional high-density electric resistance changing memory according to claim 1, is characterized in that, the thickness of the electron beam resist of spin coating described in step 5 HSQ is 120 nanometers.
7. the preparation method of three-dimensional high-density electric resistance changing memory according to claim 1, is characterized in that, photoresist described in step 6 is 9920, and the electrode pattern of formation is of a size of 1mm × 2 μm.
8. the preparation method of three-dimensional high-density electric resistance changing memory according to claim 1, is characterized in that, active electrode described in step 7 is silver (Ag), and thickness is 80 nanometers.
9. the preparation method of three-dimensional high-density electric resistance changing memory according to claim 1, is characterized in that, peeling off reagent described in step 8 is acetone+ethanol.
10. the preparation method of three-dimensional high-density electric resistance changing memory according to claim 1, is characterized in that, the thickness of the electron beam resist of spin coating described in step 9 HSQ is 120 nanometers.
The preparation method of 11. three-dimensional high-density electric resistance changing memories according to claim 1, it is characterized in that, photoresist described in step 10 is 9920, and the electrode pattern of formation is of a size of 2 μm × 1 μm.
The preparation method of 12. three-dimensional high-density electric resistance changing memories according to claim 1, is characterized in that, in step 11, electron beam evaporation inert electrode metal is platinum (Pt), thickness 80 nanometer.
The preparation method of 13. three-dimensional high-density electric resistance changing memories according to claim 1, is characterized in that, peeling off reagent described in step 12 is acetone+ethanol.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111564363A (en) * | 2020-04-24 | 2020-08-21 | 天津华慧芯科技集团有限公司 | Method for preparing overlay mark by electron beam lithography based on HSQ |
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| CN101452891A (en) * | 2007-12-05 | 2009-06-10 | 中国科学院微电子研究所 | Method for manufacturing resistance variant memory crossover array |
| US20120182787A1 (en) * | 2009-06-23 | 2012-07-19 | Micron Technology, Inc. | Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array |
| CN104051623A (en) * | 2014-06-19 | 2014-09-17 | 中国科学院半导体研究所 | Method for manufacturing multi-bit high-integrity memory of vertical structure |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101431144A (en) * | 2007-11-07 | 2009-05-13 | 中国科学院微电子研究所 | Method for producing self-isolation resistor transformation type memory unit |
| CN101452891A (en) * | 2007-12-05 | 2009-06-10 | 中国科学院微电子研究所 | Method for manufacturing resistance variant memory crossover array |
| US20120182787A1 (en) * | 2009-06-23 | 2012-07-19 | Micron Technology, Inc. | Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array |
| CN104051623A (en) * | 2014-06-19 | 2014-09-17 | 中国科学院半导体研究所 | Method for manufacturing multi-bit high-integrity memory of vertical structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111564363A (en) * | 2020-04-24 | 2020-08-21 | 天津华慧芯科技集团有限公司 | Method for preparing overlay mark by electron beam lithography based on HSQ |
| CN111564363B (en) * | 2020-04-24 | 2022-07-29 | 天津华慧芯科技集团有限公司 | Method for preparing overlay mark by electron beam lithography based on HSQ |
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Effective date of registration: 20211220 Address after: 230000 China (Anhui) pilot Free Trade Zone, Hefei, Anhui Province a1205-a1208, future center, Institute of advanced technology, University of science and technology of China, No. 5089, Wangjiang West Road, high tech Zone, Hefei Patentee after: Hefei Zhongke microelectronics Innovation Center Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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