CN104795493A - Nanowire array based memristor and manufacturing method thereof - Google Patents
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Abstract
The invention belongs to the field of micro-nano electronic devices, and particularly relates to a nanowire array based memristor and manufacturing method thereof. A nanowire array device comprises an upper electrode, a lower electrode and a nanowire array layer arranged between upper and lower electrode layers; a nanowire array can be a metal-oxide semiconductor or an insulator and further needs sputtering processing through reducing gas ions of Ar, Ar/H2, NH3 and the like resulting in formation of oxygen defect in the surface layer of a nanowire and disordering of the micro-structure, and the surface layer containing the structural defect is a main resistance change area of the nanowire array memristor. The memristor with the nanowire array structure can be obtained, and the memristor has the advantages of continuous multi-resistance changes, stable operation, high storage density, simpleness in manufacturing, low cost and the like.
Description
Technical field
The invention belongs to micro-nano field of electronic devices, relate to a kind of memristor based on nano-wire array and preparation method thereof.
Background technology
Memristor is considered to the 4th kind of passive electronic components except resistance, electric capacity, inductance, and the electrology characteristic of its novelty is that resistance can occurrence dynamics changes with the electric charge flowing through device, and realizes the storage of continuous resistance state.1971, scientist professor Cai Shaotang of Chinese origin foretold the existence of this basic electronic component of memristor theoretically.2008, memristor antetype device was constructed first experimentally in HP Lab.Memristor has novel non-linear electric character, and have the features such as density is high, size is little, low in energy consumption, non-volatile concurrently, be considered to one of ideal scheme developing novel nonvolatile storage technologies of future generation, thus become the study hotspot in the field such as information, material.In addition, the resistive behavior of memristor and organism neural plasticity have the similitude of height, thus in the development bionical device of nerve synapse and neuromorphic computer etc., have potentiality.
The memory resistor that HP Lab proposes have employed by anoxic and oxygen enrichment TiO
2the double-decker that film is formed, utilizes electric field induce oxygen defect to realize the regulation and control of device resistance in the migration of two interlayers.Subsequently, the memory resistor of different structure, different materials is succeeded in developing in succession.Such as, one is disclosed in CN102738387A patent based on individual layer TiO
x(0.5<x<3) memristor and preparation method thereof of membrane structure, and in CN103050622A patent, disclose a kind of memory resistor based on AgInSbTe material system.
In memory resistor research, the application of its potential high storage density is the pith of research always, especially in the bionical device research of nerve synapse.About 10 are had in human brain
14individual nerve synapse, compared to the preparation method of conventional artificial's cynapse, the artificial synapse utilizing highdensity nanometer memristor to construct equal number will lower power consumption and volume greatly.Common memory resistor many employings thin layer is as its functional shift layer, and therefore the use of the micro-nano technology such as photoetching, electrograving technology is preparation and the key of integrated high density memory resistor.In view of the high density characteristic of nano-wire array, exploitation has the memory resistor of nano thread structure, is to realize the easy of high density memory cells and effective way.Meanwhile, the structural design being introduced as memristor of nanostructure provides new scheme, and is that the memory resistor of memory cell provides Research foundation for developing further with single nano-wire.
Summary of the invention
The object of the invention is to provide a kind of memristor based on nano-wire array and preparation method thereof, wherein by carrying out gas ion sputtering to monocrystal nano line array top layer, the generation of oxygen defect and the disordering of micro-structural in induced nano line superficial layer, form memristor resistance state transition layer.Meanwhile, device can with apply voltage realize continuous resistance adjustable recall resistance behavior.
It is as follows that the present invention realizes the above-mentioned technical scheme based on nano-wire array memristor: a kind of memristor based on nanowire array structure, comprises the memristor resistance state transition layer between top electrode, bottom electrode and two electrodes.It is characterized in that, resistance state transition layer is metal oxide nano-wire array, and metal oxide can be TiO
2, ZnO etc.
On the basis of technique scheme, the present invention can also do preferably following.
Described bottom electrode is FTO or ITO electro-conductive glass, and its resistance is 10 Ω to 400 Ω.
Described very metal electrode or the conducting oxide electrode etc. of powering on.
Described upper electrode material can be one or more combinations in the metal electrodes such as Pt, Au, Ti, W, Al, Ta; Described conducting oxide electrode comprises ITO, IZO, FTO etc.; Described top electrode thickness is 20nm to 500nm.
Described nano-wire array is hydrothermal method preparation, and its diameter is 80nm to 200nm, and length is 800nm to 3 μm.
Described nano-wire array need experience Ar, Ar/H
2, NH
3deng reducibility gas ion sputtering process, produce oxygen defect in induced nano line upper end face layer and micro-structural is unordered, form resistance state transition layer.
Present invention also offers a kind of preparation method realizing above-mentioned memory resistor:
Step one: prepare bottom electrode;
Step 2: in FTO or ITO Conducting Glass, utilizes hydrothermal method to prepare monocrystalline metal oxide nano-wire array;
Step 3: utilize magnetron sputtering at Ar, Ar/H
2, NH
3deng in reducibility gas, backwash process is carried out to monocrystalline metal oxide nano-wire array, induction top layer, array upper end produce oxygen defect and micro-structural unordered, form resistance state transition layer;
Step 4: use the metal oxide nano-wire array after the process of macromolecular material encapsulation gas ion, and use the methods such as thermal evaporation, electron beam evaporation or sputtering to deposit top electrode at array top.
The invention has the beneficial effects as follows: the invention provides a kind of based on nano-wire array memristor and preparation method thereof, the constructing plan of memory resistor can be expanded.Meanwhile, this memory resistor has the advantages such as continuous many resistance states change, stable, performance is controlled, technique is simple, cost is low, high density.
Accompanying drawing explanation
Fig. 1 is the structural representation of nano-wire array memristor in the inventive method;
Fig. 2 is embodiment TiO in the inventive method
2nano-wire array memristor preparation method flow chart;
Fig. 3 is structural representation corresponding to each step of preparation method shown in Fig. 2;
Fig. 4 is TiO in Fig. 3 (b)
2eSEM sectional drawing corresponding to nano-wire array;
Fig. 5 is embodiment of the present invention memristor fundamental voltage-current curve under continuous positive bias;
Fig. 6 is embodiment of the present invention memristor fundamental voltage-current curve under continuous back bias voltage.
Embodiment
For making object of the present invention, technical scheme and advantage more clear, below in conjunction with accompanying drawing and instantiation, operating process of the present invention is described in further detail.Need to illustrate, instantiation described herein only for explaining the present invention, is wherein illustrated as illustrative nature, the scope be not intended to limit the present invention.
Embodiment
Fig. 1 is the structural representation of nano-wire array memristor in the inventive method.As shown in Figure 1, memristor comprises: substrate 100; Bottom electrode 101; Be grown on the nano-wire array 102 on bottom electrode, in this embodiment, select TiO
2; The resistance state transition layer 103 of experience gas ion sputter process; For the macromolecular material 104 of encapsulated nanowire array; Be deposited on the top electrode 105 on nano-wire array top.
Described substrate 100 is generally quartz, glass or silicon etc.
Described bottom electrode 101 can select FTO or ITO conductive film, and its resistance is 10 Ω to 400 Ω.Select in conjunction with substrate, can be understood as and can directly use FTO or ITO electro-conductive glass, or deposition FTO or ITO conductive film is applicable equally in other substrate.
Described top electrode 105 can be one or more combinations in the metal electrodes such as Pt, Au, Cu, Ag, Ti, W, Al, Ta; Described conductive compound electrode comprises ITO, IZO, FTO etc.; Described top electrode 105 thickness is 20nm to 500nm; Described top electrode 105 can adopt the modes such as magnetron sputtering, thermal evaporation, electron beam evaporation to prepare.
Described nano-wire array 102 can be hydrothermal method preparation, and its diameter is 80nm to 200nm, and length is 800nm to 3 μm.
Further, described nano-wire array need experience Ar, Ar/H
2, NH
3deng reducibility gas ion sputtering process, top layer, induced nano linear array upper end produce oxygen defect and micro-structural unordered, form resistance state transition layer 103;
Described macromolecular material 104 can select PMMA etc.
Meanwhile, the invention provides above-described embodiment preparation method:
Figure 2 shows that the flow chart of embodiment memristor preparation method, below with reference to Fig. 3, preparation process be described:
Step B101, prepares bottom electrode.
As shown in Fig. 3 (a), according to preparation flow, first on substrate, bottom electrode 101 will be prepared on 100.In the present embodiment, choose the commercial FTO electro-conductive glass that resistance is 50 Ω, and its size is cut into the small pieces of length × wide=2cm × 1cm.
Step B102, growth TiO
2monocrystal nano line array.
As shown in Fig. 3 (b), at FTO electro-conductive glass (100 and 101) growth TiO
2monocrystal nano line array 102.Specific experiment step is as follows:
(1) the FTO Conducting Glass (100 and 101) will crossed with ethanol purge, puts into ultrasonic cleaning instrument and cleans several minutes, then use deionized water rinsing, and dry up with nitrogen for subsequent use;
(2) be that 1:50:50 prepares 50ml solution by butyl titanate (98%), hydrochloric acid (36%-38%), water etc. according to volume ratio; Solution is moved in hydrothermal reaction kettle, and FTO electro-conductive glass (100 and 101) is inserted reactor; Reactor is placed in drying box and carries out hydro-thermal reaction, reaction temperature is 150
oc, the reaction time is 3-6 hour; Room temperature cools reactor naturally, takes out FTO substrate (100 and 101) and removes Liquid Residue with deionized water rinsing, can obtain TiO
2monocrystal nano line array 102.Figure 4 shows that in the present embodiment at the upper TiO prepared of FTO conductive substrates (100 and 101)
2monocrystal nano line array 102.
Step B103, utilizes gas ion sputter process TiO
2nano-wire array, forms resistive and forms layer.
As shown in Fig. 3 (c), by gas ion sputter process TiO
2nano-wire array 102, induces its upper end to produce oxygen defect and disordering structure, and then forms change resistance layer 103; Described gas can select Ar, Ar/H
2, NH
3deng gas.In the present embodiment, at high-purity Ar/H
2in (97%/3%) gas, utilize the reverse sputtering function of magnetron sputtering to TiO
2monocrystal nano line array 102 processes, and wherein radio-frequency power is 30W, and the processing time is 5 minutes; To TiO
2monocrystal nano line array 102 carries out backwash process, induction top layer, array upper end produce oxygen defect and micro-structural unordered, form resistance state transition layer 103.
Step B104, packaging also prepares top electrode.
As shown in Fig. 3 (d), macromolecular material PMMA is utilized to carry out encapsulation 104 to nano wire.In the present embodiment, PMMA is dissolved in acetone and prepares the solution that mass fraction is 0.32%, be spin-coated on nano-wire array 102 surface and form uniform encapsulated layer 104; Use the methods such as heat steaming, electron beam evaporation or sputtering at array top deposition top electrode 105.
Fig. 5 and Fig. 6 is the voltage-current characteristic curve of the embodiment of the present invention under the continuous positive bias of top electrode 105 and continuous back bias voltage scanning.As shown in Figure 5, device current increases with positive bias scanning times and increases.As shown in Figure 6, device current increases with back bias voltage scanning times and reduces.Fig. 5 and Fig. 6 shows that the resistance of external voltage to memory resistor has modulating action, and the present embodiment memory resistor has the non-linear electric character similar with existing memristor.
Above-mentioned embodiment is the unrestricted technical scheme of the present invention in order to explanation only, and any technical scheme not departing from spirit and scope of the invention all should be encompassed in the middle of patent claim of the present invention.
Claims (5)
1., based on a memristor for nanowire array structure, comprise the memristor resistance state transition layer between top electrode, bottom electrode and two electrodes, it is characterized in that, resistance state transition layer is metal oxide nano-wire array, and metal oxide is TiO
2, ZnO.
2. memristor according to claim 1, is characterized in that, described bottom electrode is FTO or ITO electro-conductive glass, and its resistance is 10 Ω to 400 Ω, and its thickness is 200nm to 500nm, described in power on very metal electrode or conducting oxide electrode.
3. memristor according to claim 2, is characterized in that, described upper electrode material is one or more combinations in Pt, Au, Ti, W, Al, Ta metal electrode; Described conducting oxide electrode comprises ITO, IZO, FTO; Described top electrode thickness is 20nm to 500nm.
4. memristor according to claim 1, is characterized in that, described nano-wire array diameter is 80nm to 200nm, and length is 800nm to 3 μm.
5. based on a memory resistor preparation method for nanowire array structure, it is characterized in that, described preparation method comprises the following steps:
One, first will on substrate on prepare bottom electrode, choose the commercial FTO electro-conductive glass that resistance is 50 Ω, and its size be cut into the small pieces of length × wide=2cm × 1cm;
Two, in FTO or ITO Conducting Glass, hydrothermal method is utilized to prepare monocrystalline metal oxide nano-wire array:
(1) the FTO Conducting Glass will crossed with ethanol purge, puts into ultrasonic cleaning instrument and cleans several minutes, then use deionized water rinsing, and dry up with nitrogen for subsequent use;
(2) be that 1:50:50 prepares 50ml solution by 98% butyl titanate, 36%-38% hydrochloric acid, water according to volume ratio; Solution is moved in hydrothermal reaction kettle, and FTO electro-conductive glass is inserted reactor; Reactor is placed in drying box and carries out hydro-thermal reaction, reaction temperature is 150
oc, the reaction time is 3-6 hour; Room temperature cools reactor naturally, takes out FTO substrate deionized water rinsing and removes Liquid Residue, namely obtain TiO
2monocrystal nano line array;
Three, by gas ion sputter process TiO
2nanometer linear array, induces its upper end to produce oxygen defect and disordering structure, and then forms change resistance layer; Described gas selects Ar or Ar/H
2or NH
3gas, at high-purity Ar/H
2in 97%/3% gas, utilize the reverse sputtering function of magnetron sputtering to TiO
2monocrystal nano line array processes, and wherein radio-frequency power is 30W, and the processing time is 5 minutes; To TiO
2monocrystal nano line array carries out backwash process, induction top layer, array upper end produce oxygen defect and micro-structural unordered, form resistance state transition layer;
Four, utilize macromolecular material PMMA to carry out array of packages to nano wire, PMMA is dissolved in acetone and prepares the solution that mass fraction is 0.32%, be spin-coated on nano-wire array surface and form uniform encapsulated layer; Heat steaming, electron beam evaporation or sputtering method is used to deposit top electrode at array top.
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| CN105405970A (en) * | 2015-11-27 | 2016-03-16 | 西安交通大学 | ITO nanowire network based resistive switch and preparation method thereof |
| CN105552224A (en) * | 2016-01-21 | 2016-05-04 | 山东科技大学 | Method for preparing memristor based on nanoscale single layer Bi (1-x) CaxFeO3-x/2 resistance variable film |
| CN105576121A (en) * | 2015-12-25 | 2016-05-11 | 山东科技大学 | Preparation method of flexible single-layer nano-film memristor |
| CN105576122A (en) * | 2015-12-25 | 2016-05-11 | 山东科技大学 | Preparation method of single-layer nano resistance film memristor |
| CN105591028A (en) * | 2016-01-21 | 2016-05-18 | 山东科技大学 | Preparation method of single-layer nano-film memristor using LTCC green tape as substrate |
| CN107331771A (en) * | 2017-06-28 | 2017-11-07 | 山西师范大学 | A kind of low energy consumption, multi-functional Multilayered Nanowires resistance-variable storing device |
| CN108281548A (en) * | 2018-02-07 | 2018-07-13 | 中南大学 | A kind of bipolarity bistable state memristor and preparation method thereof |
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| CN108878647A (en) * | 2018-06-29 | 2018-11-23 | 西南交通大学 | Device preparation method a kind of while that there is negative differential resistance and memristor function |
| CN109449288A (en) * | 2018-10-29 | 2019-03-08 | 集美大学 | Low-leakage current, the MgO nano wire RRAM of big resistance value ratio and its manufacturing method |
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| CN109920912A (en) * | 2019-03-28 | 2019-06-21 | 江苏师范大学 | A kind of bionical device of multi-functional cynapse and preparation method thereof |
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| US11141723B2 (en) | 2015-11-30 | 2021-10-12 | Newsouth Innovations Pty Limited | Method for improving catalytic activity |
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| CN109920912B (en) * | 2019-03-28 | 2023-02-03 | 江苏师范大学 | Multifunctional synapse bionic device and preparation method thereof |
| CN109920912A (en) * | 2019-03-28 | 2019-06-21 | 江苏师范大学 | A kind of bionical device of multi-functional cynapse and preparation method thereof |
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