CN104377168A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN104377168A CN104377168A CN201310359732.5A CN201310359732A CN104377168A CN 104377168 A CN104377168 A CN 104377168A CN 201310359732 A CN201310359732 A CN 201310359732A CN 104377168 A CN104377168 A CN 104377168A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- 239000002184 metal Substances 0.000 claims abstract description 51
- 230000004888 barrier function Effects 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 36
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 239000010410 layer Substances 0.000 claims description 92
- 239000000945 filler Substances 0.000 claims description 20
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 229910010041 TiAlC Inorganic materials 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000003475 lamination Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910010038 TiAl Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- Materials Engineering (AREA)
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- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a method for manufacturing a semiconductor device, and provides a method for forming a CMOS metal grid, wherein a new metal grid stack structure is adopted, a diffusion barrier layer is not required to be formed between a high-K grid insulating layer and an etching stop layer, Al diffusion can also be blocked, and the degradation of the high-K grid insulating layer and a PMOS grid work function control layer caused by metal atom diffusion is avoided; meanwhile, due to the fact that the diffusion barrier layer is omitted, the NMOS grid work function control layer in the NMOS area is closer to the high-K grid insulation layer, and therefore the NMOS work function can be effectively controlled. The metal grid electrode of the invention has simplified structure and reduced thickness, and is suitable for CMOS devices with high integration level and small size.
Description
Technical field
The present invention relates to method, semi-conductor device manufacturing method field, especially, relate to a kind of manufacture method of cmos device metal gates.
Background technology
Semiconductor integrated circuit technology after the technology node entering into 90nm characteristic size, maintain or improve transistor performance more and more challenging.After 90nm node, stress technique is used the performance improving device gradually.With it simultaneously, in manufacturing process, the high-K metal gate technology (HKMG) in rear grid technique (gate last) is also used gradually to tackle and constantly reduces along with device and the challenge that brings.The application of HKMG, while suppression Leakage Current, can guarantee the EOT(Effective Oxide Thickness of gate insulator).
Usually, the metal gate structure of cmos device and manufacture method following (can see secondary Fig. 8 (a) and 9(a)): on substrate, successively form high-K gate insulating barrier 31 successively, diffusion impervious layer 32(is generally TiN), etching stop layer 33(is generally TaN), PMOS gate work-function key-course 34(is generally TiN), then, the PMOS gate work-function key-course 34 covering NMOS area is removed; Then, form NMOS gate work-function key-course 35(successively and be generally TiAl), metallic filler layers 36(is generally TiN/Al lamination or TiN/W lamination); Carry out planarization, remove unnecessary stack material, thus the stack required for being formed.Wherein, the effect of diffusion impervious layer 32 is the deteriorations in order to stop metallic element diffusion in NMOS gate work-function key-course 35 and the high-K gate insulating barrier 31 that causes and PMOS gate work-function key-course 34.This shows, in the prior art, PMOS metal gate stack at least comprises high-K gate insulating barrier 31, diffusion impervious layer 32, etching stop layer 33, PMOS gate work-function key-course 34, NMOS gate work-function key-course 35, such 6 Rotating fields of metallic filler layers 36, and NMOS metal gate stack at least comprises high-K gate insulating barrier 31, diffusion impervious layer 32, etching stop layer 33, NMOS gate work-function key-course 35, such 5 Rotating fields of metallic filler layers 36, their structure is all comparatively complicated, and the number of plies is various.More disadvantageous situation is, along with device dimensions shrink, and the appearance of the stereochemical structure device such as such as FinFET, the size of metal gate stack is also more and more less, the depth-to-width ratio in the space of filling becomes large, make sandwich construction, the conventional metals stack that thickness is larger has problems in forming process, see accompanying drawing 1, wherein be formed with the structure sheaf 2 holding gate recess on substrate 1, structure sheaf 2 is generally interlayer dielectric layer in planar CMOS device, adjacent semiconductor fin (Fin) is generally in FinFET, especially for FinFET, because semiconductor fin height is higher, such as be generally 25-40nm, the gate height covering fin is generally 25-75nm, therefore, the height on the sti structure surface between the gate surface distance fin at fin top is 50-115nm, and fin pitch is less, be generally 30-50nm, FinFET structure embodies rugged three-dimensional surface, especially when gate CDs is less than 35nm, often occur that the structure of larger depth-to-width ratio needs to fill grid, therefore, when forming metal gate stack 3, often form cavity 4, this will have a strong impact on device performance, even cause component failure.
Therefore, need to provide a kind of new CMOS metal gate structure and technique, be applicable to high integration, undersized cmos device, above-mentioned defect can be overcome, guarantee device performance and normally work.
Summary of the invention
For Problems existing in CMOS metal gates filling process, the present invention proposes a kind of semiconductor making method, adopt new metal gate stack structure and material to overcome the problems of the prior art.
The invention provides a kind of method, semi-conductor device manufacturing method, wherein, comprise the steps:
There is provided Semiconductor substrate, this Semiconductor substrate forms sti structure, described sti structure is by NMOS area and PMOS area isolation;
Gate recess is formed in described NMOS area and described PMOS area;
Form high-K gate insulating barrier successively, etching stop layer, NMOS gate work-function key-course, wherein, described NMOS gate work-function key-course material is TiAlC, and thickness is 0.1-5nm;
Remove the described NMOS gate work-function key-course being positioned at described PMOS area;
Form PMOS gate work-function key-course;
Plated metal packed layer, fills completely by described gate recess;
Carry out CMP, remove the described metallic filler layers beyond described gate recess, described PMOS gate work-function key-course, described NMOS gate work-function key-course, described etching stop layer and described high-K gate insulating barrier, in described gate recess, form metal gate stack.
According to an aspect of the present invention, the technique forming NMOS gate work-function key-course is ALD.
According to an aspect of the present invention, the Al atom content in described NMOS gate work-function key-course material TiAlC is not more than 50%.
According to an aspect of the present invention, diffusion impervious layer is not formed between described high-K gate insulating barrier and described etching stop layer.
According to an aspect of the present invention, after removal is positioned at the step of described NMOS gate work-function key-course of described PMOS area, the described etching stop layer being positioned at described PMOS area is removed completely, make in the described metal gate stack of described PMOS area, described PMOS gate work-function key-course directly contacts described high-K gate insulating barrier.
According to an aspect of the present invention, after removal is positioned at the step of described NMOS gate work-function key-course of described PMOS area, the described etching stopping layer segment being positioned at described PMOS area is removed, make in the described metal gate stack of described PMOS area, the described etching stop layer of residual fraction thickness between described PMOS gate work-function key-course and described high-K gate insulating barrier, its thickness is 0.1-3nm.
According to an aspect of the present invention, described gate recess is between FinFET structure cmos device adjacent semiconductor fin, or described gate recess is positioned among the interlayer dielectric layer of planar structure cmos device.
According to an aspect of the present invention, described PMOS gate work-function key-course is individual layer TiN.
In addition, the invention provides a kind of semiconductor device, it comprises:
Semiconductor substrate, the sti structure in this Semiconductor substrate, and the NMOS area of being isolated by described sti structure and PMOS area;
Described NMOS area and described PMOS area have metal gate stack respectively;
The metal gate stack of described NMOS from bottom to top comprises successively: high-K gate insulating barrier, etching stop layer, NMOS gate work-function key-course, PMOS gate work-function key-course, metallic filler layers; The metal gate stack of described PMOS from bottom to top comprises successively: high-K gate insulating barrier, etching stop layer, PMOS gate work-function key-course, metallic filler layers;
Wherein, described NMOS gate work-function key-course material is TiAlC, and thickness is 0.1-5nm.
According to an aspect of the present invention, the Al atom content in described NMOS gate work-function key-course material TiAlC is not more than 50%.
According to an aspect of the present invention, in the metal gate stack of described NMOS area and described PMOS area, between described high-K gate insulating barrier and described etching stop layer, there is not diffusion impervious layer.
According to an aspect of the present invention, described PMOS gate work-function key-course is individual layer TiN.
The invention has the advantages that: in CMOS metal gates formation process, have employed new metal gate stack structure, be specially the NMOS gate work-function key-course that have employed TiAlC material, its Al atom content NMOS more of the prior art gate work-function key-course is less, and, NMOS gate work-function key-course is optionally eliminated in PMOS area, therefore, do not need between high-K gate insulating barrier and etching stop layer, form diffusion impervious layer to go to stop that Al spreads, and fundamentally avoid the deterioration of high-K gate insulating barrier and the PMOS gate work-function key-course caused due to metallic atom diffusion, like this, the designs simplification of metal gate stack, thickness reduces, simultaneously, owing to eliminating diffusion impervious layer, at the NMOS gate work-function key-course of NMOS area more close to high-K gate insulating barrier, thus can more effectively control NMOS work function, also by the reduced thickness of NMOS gate work-function key-course, thus the less stack of thickness can be obtained on this basis.In sum, metal gate structure of the present invention simplifies, and thickness reduces, and is applicable to high integration, undersized cmos device, can overcome fill process in prior art and occur the defect in cavity, guarantee device performance and normally work.
Accompanying drawing explanation
In Fig. 1 prior art, metal gate stack fills the schematic diagram occurring cavity;
Fig. 2-7 the present invention forms the process flow diagram of metal gate stack;
Metal gate stack structure (b) of Fig. 8-9 NMOS and PMOS of the present invention and the contrast of prior art metal gate stack structure (a).
Embodiment
Below, by the specific embodiment shown in accompanying drawing, the present invention is described.But should be appreciated that, these describe just exemplary, and do not really want to limit the scope of the invention.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring concept of the present invention.
The invention provides a kind of method, semi-conductor device manufacturing method, particularly a kind of method for the formation of CMOS metal gates.Below, see accompanying drawing 2-9, method, semi-conductor device manufacturing method provided by the invention will be described in detail.
First, see accompanying drawing 2, provide Semiconductor substrate 10, form sti structure 13 over the semiconductor substrate 10, NMOS area 11 and PMOS area 12 are isolated by sti structure 13, and, be formed with gate recess 16 respectively in NMOS area 11 and PMOS area 12.In the diagram of the present embodiment, have employed the CMOS of planar structure, but the present invention more advantageously can be used to comprise in the CMOS of FinFET structure.Substrate 10 also comprises source and drain areas 14 and interlayer dielectric layer 15.In the cmos device of planar structure, gate recess 16 is formed among interlayer dielectric layer 15, concrete generation type: existing different MOS regions over the substrate 10 form dummy gate electrode (Dummy Gate) and dummy gate electrode insulating barrier (all not shown), dummy gate electrode is generally polysilicon gate, dummy gate electrode insulating barrier is generally insulating layer of silicon oxide, then, the parts such as the source and drain areas of MOS transistor are formed; Adopt interlayer dielectric layer 15 cover dummy gate electrode and carry out planarization, thus expose dummy gate electrode; Afterwards, remove dummy gate electrode and dummy gate electrode insulating barrier, form gate recess 16.And in the cmos device of FinFET structure, gate recess between adjacent semiconductor fin, concrete formation process and planar structure cmos device gate recess formation process similar, repeat no more herein.
Because method of the present invention is applied in the cmos circuit of superintegrated plane and FinFET structure, width for the gate recess 16 holding metal gates and high K gate insulation layer (HKMG) is very little, such as at 10-35nm, filling difficulty strengthens, especially in FinFET structure cmos circuit, the degree of depth of gate recess 16 and width can reach 50-115nm and 10-35nm respectively, its filling difficulty is larger, like this, conventional H KMG structure and technique is adopted to fill gate recess 16, there will be empty situation (such as the situation of accompanying drawing 1), therefore, the present invention proposes new HKMG structure and formation method.Meanwhile, although it should be noted that the diagram being employed herein planar structure CMOS, the present invention is same and be more advantageously can apply to fill in the larger FinFET structure cmos circuit of difficulty with gate recess; Simultaneously, device architecture in diagram is only rough schematic view, can also include but not limited in cmos device of the present invention: the conventional components of the cmos device such as LDD, grid curb wall, source and drain areas contact, and the relative size relation that in schematic diagram, each parts show do not mean that their actual size ratios.
Then, see accompanying drawing 3, on interface oxide layer (not shown), high-K gate insulating barrier 21 is formed successively, etching stop layer 22, NMOS gate work-function key-course 23.High-K gate insulating barrier 21 is selected from one deck or multilayer: the Al of one of material beneath or combination formation
2o
3, HfO
2, comprise HfSiO
x, HfSiON, HfAlO
x, HfTaO
x, HfLaO
x, HfAlSiO
xand HfLaSiO
xone of at least at interior hafnium base high K dielectric material, comprise ZrO
2, La
2o
3, LaAlO
3, TiO
2, or Y
2o
3one of at least at interior rare earth based high K dielectric material.The thickness of high-K gate insulating barrier 21 is 0.5-20nm, and be preferably 1-10nm, depositing operation is such as ALD, CVD.The material of etching stop layer 22 is TaN, and its thickness range is 0.1-5nm.Different from the structure of prior art, in the present invention, high-K gate insulating barrier 21 and etching stop layer 22 do not form diffusion impervious layer (such as TiN), and concrete reason will describe in detail subsequently.In the present invention, the material of NMOS gate work-function key-course 23 is TiAlC, relative in prior art adopt TiAl, the Al content of TiAlC is lower, and such as, Al atom content is not more than 50%.Adopt ALD process deposits NMOS gate work-function key-course 24, can accurately control its thickness, its thickness is 0.1-5nm, preferably controls at 1-2nm.And the NMOS gate work-function key-course thickness of employing TiAl of the prior art is usually at more than 5nm, be greater than thickness of the present invention.Therefore, the thickness of whole stack can be reduced.
Then, see accompanying drawing 4, the NMOS gate work-function key-course 23 being positioned at PMOS area 12 is removed.Mask exposure can be passed through, expose the NMOS gate work-function key-course 23 being positioned at PMOS area 12, and cover the NMOS gate work-function key-course 23 being positioned at NMOS area 11, removed the NMOS gate work-function key-course 23 being positioned at PMOS area 12 by etching technics, specifically can adopt dry method, wet etching.Etching technics stops on etching stop layer 22, and subsequently, can not remove or partly remove or all remove etching stop layer 22, wherein, taking-up etching stop layer 22 can reduce the thickness of whole stack further at least partly.When all removing etching stop layer 22, in the stack of PMOS area, the PMOS gate work-function key-course 24 formed subsequently will directly contact high-K gate insulating barrier 21.When part removes etching stop layer 22, in the stack of PMOS area, the etching stop layer 22 of residual fraction thickness between the PMOS gate work-function key-course 24 formed subsequently and high-K gate insulating barrier 21, its thickness is 0.1-3nm.
Then, see accompanying drawing 5, form PMOS gate work-function key-course 24, its material is TiN, and thickness is 0.1-5nm, adopts ALD mode to deposit, for regulating the gate work-function of PMOS.
Then, see accompanying drawing 6, plated metal packed layer 25, fills completely by gate recess 16.Metallic filler layers 25 is generally TiN/Al lamination or TiN/W lamination, and depositing operation is CVD, and thickness is determined according to the pattern of gate recess 16, and its thickness needs to fill gate recess 16 completely.Because metallic filler layers 25 is close to PMOS gate work-function key-course 24, TiN in lamination can be served as by PMOS gate work-function key-course 24, also namely in the one step of deposition PMOS gate work-function key-course 24, individual layer TiN is formed as PMOS gate work-function key-course 24, PMOS gate work-function key-course 24 also can as the lower floor TiN in metallic filler layers 25 lamination simultaneously, eliminate the step forming TiN in prior art in metallic filler layers 25, and reduce the thickness of whole stack.
Then see accompanying drawing 7, carry out CMP, remove metallic filler layers 25, PMOS gate work-function key-course 24, NMOS gate work-function key-course 23, etching stop layer 22 and the high-K gate insulating barrier 21 beyond gate recess 16, in gate recess, form NMOS metal gate stack 20 and PMOS metal gate stack 30 respectively.This step CMP with the surface of interlayer dielectric layer 15 for terminal.
Thus, the metal gate stack of cmos device is obtained.See Fig. 8 and Fig. 9, be the contrast of stack of the prior art and stack of the present invention respectively, Fig. 8 is the situation of NMOS, and Fig. 9 is the situation of PMOS, and (a) figure is stack of the prior art, and (b) figure is stack of the present invention.Specifically, in prior art, NMOS metal gate stack is high-K gate insulating barrier 31, diffusion impervious layer 32, etching stop layer 33, NMOS gate work-function key-course 35, metallic filler layers 36, PMOS metal gate stack is high-K gate insulating barrier 31, diffusion impervious layer 32, etching stop layer 33, PMOS gate work-function key-course 34, NMOS gate work-function key-course 35, metallic filler layers 36; And in the present invention, NMOS metal gate stack 20 is high-K gate insulating barrier 21, etching stop layer 22, NMOS gate work-function key-course 23, PMOS gate work-function key-course 24, metallic filler layers 25; PMOS metal gate stack 30 is high-K gate insulating barrier 21, etching stop layer 22, PMOS gate work-function key-course 24, metallic filler layers 25, and wherein, etching stop layer 22 is segment thickness alternatively or is completely removed.Present invention employs the NMOS gate work-function key-course 23 of TiAlC material, because the NMOS gate work-function key-course of its Al atom content TiAl more of the prior art material is less, and, NMOS gate work-function key-course is optionally eliminated in PMOS area, therefore, do not need between high-K gate insulating barrier and etching stop layer, form diffusion impervious layer to go to stop that Al spreads, and fundamentally avoid the deterioration of high-K gate insulating barrier and the PMOS gate work-function key-course caused due to metallic atom diffusion, like this, the structure of whole metal gate stack (comprising NMOS and PMOS) is simplified, thickness also reduces, especially for PMOS stack, after removing the NMOS gate work-function key-course on it, thickness will decline to a great extent, simultaneously, owing to eliminating diffusion impervious layer in prior art, at the NMOS gate work-function key-course 23 of NMOS area more close to high-K gate insulating barrier 21, thus can more effectively control NMOS work function, and on this basis, also by the reduced thickness of NMOS gate work-function key-course 23, thus the less stack of thickness can be obtained, in addition, because metallic filler layers 25 is close to PMOS gate work-function key-course 24, the forming step of TiN in metallic filler layers 25 can be saved, on the one hand Simplified flowsheet, also reduce stack thickness on the one hand.In sum, the present invention is relative to prior art, eliminate the NMOS gate work-function key-course of diffusion impervious layer and PMOS area, further, have employed the NMOS gate work-function key-course that thickness is thinner, this makes the designs simplification of metal gate stack, thickness reduces, be applicable to high integration, undersized cmos device, fill process in prior art can be overcome and occur the defect in cavity, guarantee device performance and normally work.
With reference to embodiments of the invention, explanation is given to the present invention above.But these embodiments are only used to the object illustrated, and are not intended to limit the scope of the invention.Scope of the present invention is by claims and equivalents thereof.Do not depart from the scope of the present invention, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications all should fall within the scope of the present invention.
Claims (12)
1. a method, semi-conductor device manufacturing method, is characterized in that, comprises the steps:
There is provided Semiconductor substrate, this Semiconductor substrate forms sti structure, described sti structure is by NMOS area and PMOS area isolation;
Gate recess is formed in described NMOS area and described PMOS area;
Form high-K gate insulating barrier successively, etching stop layer, NMOS gate work-function key-course, wherein, described NMOS gate work-function key-course material is TiAlC, and thickness is 0.1-5nm;
Remove the described NMOS gate work-function key-course being positioned at described PMOS area;
Form PMOS gate work-function key-course;
Plated metal packed layer, fills completely by described gate recess;
Carry out CMP, remove the described metallic filler layers beyond described gate recess, described PMOS gate work-function key-course, described NMOS gate work-function key-course, described etching stop layer and described high-K gate insulating barrier, in described gate recess, form metal gate stack.
2. method according to claim 1, is characterized in that, the technique forming NMOS gate work-function key-course is ALD.
3. method according to claim 1, is characterized in that, the Al atom content in described NMOS gate work-function key-course material TiAlC is not more than 50%.
4. method according to claim 1, is characterized in that, does not form diffusion impervious layer between described high-K gate insulating barrier and described etching stop layer.
5. method according to claim 1, it is characterized in that, after removal is positioned at the step of described NMOS gate work-function key-course of described PMOS area, the described etching stop layer being positioned at described PMOS area is removed completely, make in the described metal gate stack of described PMOS area, described PMOS gate work-function key-course directly contacts described high-K gate insulating barrier.
6. method according to claim 1, it is characterized in that, after removal is positioned at the step of described NMOS gate work-function key-course of described PMOS area, the described etching stopping layer segment being positioned at described PMOS area is removed, make in the described metal gate stack of described PMOS area, the described etching stop layer of residual fraction thickness between described PMOS gate work-function key-course and described high-K gate insulating barrier, its thickness is 0.1-3nm.
7. method according to claim 1, is characterized in that, described gate recess is between FinFET structure cmos device adjacent semiconductor fin, or described gate recess is positioned among the interlayer dielectric layer of planar structure cmos device.
8. method according to claim 1, is characterized in that, described PMOS gate work-function key-course is individual layer TiN.
9. a semiconductor device, is characterized in that comprising:
Semiconductor substrate, the sti structure in this Semiconductor substrate, and the NMOS area of being isolated by described sti structure and PMOS area;
Described NMOS area and described PMOS area have metal gate stack respectively;
The metal gate stack of described NMOS from bottom to top comprises successively: high-K gate insulating barrier, etching stop layer, NMOS gate work-function key-course, PMOS gate work-function key-course, metallic filler layers; The metal gate stack of described PMOS from bottom to top comprises successively: high-K gate insulating barrier, etching stop layer, PMOS gate work-function key-course, metallic filler layers;
Wherein, described NMOS gate work-function key-course material is TiAlC, and thickness is 0.1-5nm.
10. device according to claim 9, is characterized in that, the Al atom content in described NMOS gate work-function key-course material TiAlC is not more than 50%.
11. devices according to claim 9, is characterized in that, in the metal gate stack of described NMOS area and described PMOS area, there is not diffusion impervious layer between described high-K gate insulating barrier and described etching stop layer.
12. devices according to claim 9, is characterized in that, described PMOS gate work-function key-course is individual layer TiN.
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