CN104347405B - A kind of manufacture method of igbt - Google Patents
A kind of manufacture method of igbt Download PDFInfo
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- CN104347405B CN104347405B CN201310346631.4A CN201310346631A CN104347405B CN 104347405 B CN104347405 B CN 104347405B CN 201310346631 A CN201310346631 A CN 201310346631A CN 104347405 B CN104347405 B CN 104347405B
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000009792 diffusion process Methods 0.000 claims abstract description 40
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 238000002347 injection Methods 0.000 claims abstract description 13
- 239000007924 injection Substances 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 122
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000005260 corrosion Methods 0.000 claims description 7
- 230000007797 corrosion Effects 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 3
- 238000009751 slip forming Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 238000002156 mixing Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
Abstract
The present invention provides a kind of manufacture method of igbt, and it includes：The wafer with obverse and reverse is provided, wherein wafer includes the Semiconductor substrate of the first conduction type, the base layer of the second conduction type formed based on Semiconductor substrate in the face side of wafer and multiple grooves from the front of base layer through base layer to the Semiconductor substrate；First conductive type impurity is injected to form the first conductivity type implanted region in the bottom outside of groove to the Semiconductor substrate below base layer by groove；Carry out high temperature and push away trap so that injection region impurity diffusion that the bottom outside of adjacent two grooves is formed and blending with high compared with the concentration of the first conductive type impurity of Semiconductor substrate in base layer the first conduction type diffusion layer formed below, the wherein concentration of the first conductive type impurity of diffusion layer.Because the manufacture method is compatible with existing common process, and technique is simple, efficiency high, without special high energy ion implantation facility.
Description
【Technical field】
The present invention relates to semiconductor design and manufacturing technology field, more particularly to a kind of igbt
（Insulated Gate Bipolar Transistor, abbreviation IGBT）Manufacture method.
【Background technology】
IGBT is by BJT（Bipolar Junction Transistor, bipolar junction transistor）And MOSFET
（Metal-Oxide-Semiconductor-Field-Effect-Transistor, metal oxide semiconductor field effect transistor
Pipe）The compound full-control type voltage driven type power semiconductor of composition, has MOSFET high input impedance concurrently and the low of BJT is led
Advantage of both logical pressure drop, there is the features such as working frequency is high, and control circuit is simple, and current density is high, and on-state is forced down, extensively
Applied to Power Control field.
Due to Vce (sat) (colelctor electrode-emitter stage saturation voltage drop) be igbt as power device the most
One of important parameter, it directly determines the power consumption of igbt, therefore, is ensureing other parameters satisfaction requirement
In the case of, reducing Vce (sat) as far as possible turns into the top priority of exploitation igbt.Traditional groove-shaped insulation
Grid bipolar transistor is reduced by a series of limitations of manufacture craft in the case where ensureing the precondition of the parameters such as breakdown reverse voltage
Vce (sat) means are limited, such as, simple increase colelctor electrode Implantation Energy dosage not only requires too high to capacity of equipment, together
When its adjust leeway it is also very small.
It refer to shown in Fig. 1, it is a kind of groove-shaped igbt of new structure of the prior art.With
Traditional groove-shaped igbt is compared, and it adds n type diffused layer in the lower section of positive Pbody (P bases) layer 20
60 ", the hole injection efficiency of back side P+ colelctor electrodes 110 can greatly be increased by increasing this Rotating fields, this new in same depth
The groove-shaped igbt of type structure is higher than the carrier density of traditional groove-shaped igbt
Go out many, in the case of ensureing that Eoff (turn-off power loss) is not increased, can effectively reduce Vce (sat).But existing skill
In art, the conventional thinking of increase n type diffused layer 60 " is to utilize high energy ion implantation, and this needs extra expensive device, so as to add
Process costs, and because process exploitation window is too small, the problem of causing actual production menu difficult in maintenance；And the method system
The border of n type diffused layer 60 " and the Pbody layers 20 obtained is not easily controlled, and causes threshold voltage（Vth）Easily fluctuation.
Therefore, it is necessary to a kind of improved technical scheme is provided to overcome above mentioned problem.
【The content of the invention】
It is an object of the invention to provide a kind of manufacture method of igbt, and it can be realized in insulated gate
The diffusion layer of base layer the first conduction type formed below of second conduction type of bipolar transistor, due to the manufacture method with
Existing common process is compatible, and technique is simple, efficiency high, without special high energy ion implantation facility.
In order to solve the above problems, the present invention provides a kind of manufacture method of igbt, and it includes：There is provided
Wafer with obverse and reverse, wherein the wafer is included the Semiconductor substrate of the first conduction type, partly led based on described
Body substrate runs through in the base layer of the second conduction type of the face side formation of the wafer and from the front of the base layer
The base layer to the Semiconductor substrate multiple grooves；By the groove to the semiconductor below the base layer
Substrate injects the first conductive type impurity to form the first conductivity type implanted region in the bottom outside of the groove；Carry out high temperature
Trap is pushed away so that injection region impurity diffusion that the bottom outside of adjacent two grooves is formed and blending with the base layer
It is square into the first conduction type diffusion layer, wherein the concentration of the first conductive type impurity of the diffusion layer semiconductor lining
The concentration of first conductive type impurity at bottom is high.
In a preferred embodiment, by controlling the high temperature to push away time of trap to ensure the base layer and diffusion
Layer is not overlapping.
In a preferred embodiment, first conduction type is N-type, and second conduction type is p-type, described
Semiconductor substrate is N-type Semiconductor substrate, and the base layer is Pbody layers, and the first conduction type diffusion layer spreads for N+ types
Layer；The Semiconductor substrate includes being located at the first interarea of homonymy with the front of the wafer and is located at the reverse side of the wafer
Second interarea of homonymy.
In a preferred embodiment, the wafer with obverse and reverse that provides includes：There is provided has the first master
Face and the N-type Semiconductor substrate of the second interarea；Pbody layers are formed in the first interarea side of the Semiconductor substrate；Formed with
Hard mask is deposited on first interarea of the Semiconductor substrate of Pbody layers；Groove is selectively etched on the hard mask
Corrosion window；Trench etching is carried out by the corrosion window, to form the first interarea from the Pbody layers through described
Pbody layers to Semiconductor substrate multiple grooves；Sacrificial oxide layer is formed on the groove inner surface of groove, wherein by described sacrificial
Domestic animal oxide layer injects the first conductive type impurity to the bottom of the groove.
In a preferred embodiment, after the N+ types diffusion layer is formd, the manufacture method also includes：
The front of wafer formed with N+ type diffusion layers continuously forms the remaining Facad structure of the igbt；Formed
The reverse side of the wafer of the Facad structure of the igbt continuously forms the reverse side of the igbt
Structure.
In a preferred embodiment, it is described continuously formed in the front of the wafer formed with N+ type diffusion layers it is described absolutely
The remaining Facad structure of edge grid bipolar transistor includes：Remove the hard mask and sacrificial oxide layer；In the inside of the groove
Upper formation grid oxic horizon；Polysilicon gate is formed in the groove；Optionally from the first interarea of the Pbody layers to
The N+ active areas formed in the Pbody layers on the outside of the groove；Formed on the first interarea of the Semiconductor substrate
Cover the groove and part covers the interlayer dielectric of the N+ active areas；The shape on the first interarea of the Semiconductor substrate
Into the emitter stage for covering the interlayer dielectric.
In a preferred embodiment, the wafer in the Facad structure for forming the igbt
The inverse layer structure that reverse side continuously forms the igbt includes：In the second interarea side shape of the Semiconductor substrate
Into the semiconductor layer of the second conduction type, then it is formed on the second interarea of the Semiconductor substrate and the described second conduction
Second main electrode of the semiconductor layer electrical contact of type.
Compared with prior art, the manufacture method of the igbt in the present invention, it leads to after groove is made
Cross the groove to inject in the channel bottom and spread the first conductive type impurity, so as in the base layer of the second conduction type
The diffusion layer of first conduction type formed below, of concentration compared with Semiconductor substrate of the first conductive type impurity of the diffusion layer
The concentration of one conductive type impurity is high.Because the manufacture method is compatible with existing common process, and technique is simple, efficiency high,
Without special high energy ion implantation facility.
【Brief description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, it can also be obtained according to these accompanying drawings other
Accompanying drawing.Wherein：
Fig. 1 is the profilograph of igbt of the prior art；
Fig. 2 is the flow chart of the manufacture method of the igbt of the present invention in one embodiment；
Fig. 3 to Figure 11 corresponds to the profilograph of wafer for each manufacturing process in the flow chart shown in Fig. 2.
【Embodiment】
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is further detailed explanation.
" one embodiment " or " embodiment " referred to herein refers to may be included at least one implementation of the present invention
Special characteristic, structure or characteristic." in one embodiment " that different places occur in this manual not refers both to same
Individual embodiment, nor the single or selective embodiment mutually exclusive with other embodiment.
The manufacture method of igbt in the present invention is after groove is made, by groove injection simultaneously
The first conductive type impurity is spread, with the diffusion layer of the base layer of the second conduction type the first conduction type formed below.
It refer to shown in Fig. 2, the manufacture method 200 of its igbt for the present invention in one embodiment
Flow chart.The manufacture method 200 of the igbt comprises the following steps.
Step 210, there is provided there is the wafer of obverse and reverse, wherein, the wafer includes the half of the first conduction type
The base layer 20 of conductor substrate 10, the second conduction type formed based on the Semiconductor substrate 10 in the face side of the wafer
And selectively run through the base layer 20 to multiple grooves of the Semiconductor substrate 10 from the front of the base layer 20
30。
In one embodiment, the step 210 provides semiconductor crystal wafer 300 as shown in Figure 3, it is assumed that described first leads
Electric type is N-type, and second conduction type is p-type, and now the Semiconductor substrate of first conduction type is the half of N-type
Conductor substrate 10, the base layer of second conduction type is Pbody layers 20.Wherein described Semiconductor substrate 10 include with it is described
The front of wafer is located at the first interarea 1S1 of homonymy and is located at the second interarea 1S2 of homonymy with the reverse side of the wafer.
Semiconductor crystal wafer 300 in Fig. 3 can be made based on following technique, be specially：Prepare have the first interarea 1S1 and
Second interarea 1S2 N-type Semiconductor substrate 10；Pbody layers 20 are formed in the first interarea 1S1 sides of the Semiconductor substrate 10；
Hard mask 40 is deposited on the first interarea 1S1 of the Semiconductor substrate 10 formed with Pbody layers 20；It is enterprising in the hard mask 40
Row trench（Groove）Layer photoetching, hard mask corrosion, to etch the corrosion window of groove 30；Carried out by the corrosion window
Trench corrodes, to form the first interarea 1S1 from the Pbody layers 20 through the Pbody layers 20 to Semiconductor substrate 10
Groove 30；Sacrificial oxide layer 30a is formed on the groove inner surface of groove 30.
Step 220, fitted by the groove 30 to the implantation concentration of Semiconductor substrate 10 positioned at the lower section of base layer 20
In the first conductive type impurity, with the bottom outside of the groove 30 formed the first conductivity type implanted region 60a.
In one embodiment, step 220 carries out front phosphorus injection as shown in figure 4, using existing mask protection（That is N
Type impurity injects）, to form N+ types injection region 60a in the bottom outside of groove 30.Due to the front of semiconductor crystal wafer 300
Other parts inject on hard mask 40, there is N-type impurity injection in the only region of groove 30；And the main points of the step exist
In it is ensured that the dosage of N-type impurity injection concentrates on channel bottom.
Step 230, carry out high temperature and push away trap so that the injection region 60a impurity diffusions on the outside of two adjacent channel bottoms are simultaneously
Blend, so as in the base layer 20 diffusion layer 60 formed below.First conductive type impurity of the diffusion layer 60 it is dense
The concentration of first conductive type impurity of the degree Semiconductor substrate 10 is high.
In one embodiment, step 230 pushes away trap as shown in figure 5, carrying out high temperature so that N+ types injection region 60a impurity expands
Dissipate, so that the N-type injection region diffusion on the outside of each channel bottom converges, to expand in the Pbody layers 20 N+ types formed below
Dissipate layer 60.In a preferred embodiment, Pbody layers 20 can be ensured by controlling pushing away the trap time for N+ types injection region 60a
With N+ types diffusion layer 60 overlapping, i.e., Pbody layers 20 and the N+ types diffusion layer in the vertical or between be separated with N-type and partly lead
Body substrate 10, two layers do not connect.Push away the trap time specifically, described and need to calculate by analog simulation, consider p-type and N-type
Diffusion velocity, to ensure that Pbody layers 20 and N+ types diffusion layer 60 be not overlapping.The N+ types diffusion layer 60 is used as carrier layer
(CS layers), its increase can effectively reduce Vce (sat).The trap time can be pushed away by control, make the base layer 20 and N+
Type diffusion layer 60 is not overlapping effectively to solve Pbody layers 20 and N+ types diffusion layer 60 interacts and causes threshold voltage
The problem of Vth is difficult to control.
As can be seen that it is that may be implemented in the second conduction type of igbt by step 210 to step 230
The first conduction type diffusion layer 60 formed below of base layer 20.
Hereinafter, it is the subsequent step of manufacture igbt.
Step 240, after the base layer 20 diffusion layer 60 formed below, remove hard in the Semiconductor substrate 10
Mask 40 and sacrificial oxide layer 30a, grid oxic horizon 50 is formed on the inwall of the groove 30, obtains crystalline substance as shown in Figure 6
Circle.
Step 250, across the grid oxic horizon 50, polysilicon gate 80 is formed in the groove 30.
In one embodiment, in step 250, the depositing polysilicon on the first interarea 1S1 of the Semiconductor substrate 10,
Structure by photoetching, etching technics as shown in fig. 7, then remove the polysilicon of the wafer upper surface, to form polysilicon gate
Pole 80.
Step 260, optionally formed from the first interarea of base layer 20 into the base layer 20 and be located at the groove
The active area 70 of first conduction type in 30 outsides.
In one embodiment, ion implanting window is obtained by photoetching and etching, then carries out N-type impurity and inject to be formed
N+ active areas 70, obtain wafer as shown in Figure 8, and wherein 80a is photoresist.
Step 270, formed on the first interarea 1S1 of the Semiconductor substrate 10 and cover the groove 30 and part covering
The interlayer dielectric 90 of the active area 70, as shown in Figure 9.Specifically, photoresist 80a can be removed first, the crystalline substance is etched away
Oxide layer on circle, interlayer insulator die layer is then formed over the semiconductor substrate 10, can also be referred to as dielectric layer, pass through afterwards
Photoetching, etching obtain the layer insulation mould 90 shown in Fig. 9.
Step 280, formed on the first interarea 1S1 of the Semiconductor substrate 10 and cover the of the interlayer dielectric 90
One main electrode 100.
In one embodiment, step 270 is as shown in Figure 10, is formed and covered on the first interarea of the Semiconductor substrate 10
The metal emitting 100 of the interlayer dielectric 90 is covered, the emitter stage 100 and Pbody layers 20 and N+ active areas 70 make electrical contact with.
In actual applications, after step 280 and before step 290, it is also necessary to form user's protection in the front of wafer
Passivation layer (not shown).
Step 240- steps 280 are to continuously form the insulated gate bipolar in the front of the wafer formed with N+ type diffusion layers
The process of the remaining Facad structure of transistor.
Step 290, the semiconductor layer of the second conduction type is formed in the second interarea 1S2 sides of the Semiconductor substrate 10
110, the semiconductor layer with second conduction type is then formed on the second interarea 1S2 of the Semiconductor substrate 10
Second main electrode 120 of 110 electrical contacts, as shown in Figure 10.In the embodiment shown in fig. 11, the half of second conduction type
Conductor layer 110 is P+ collector layers 110, and second main electrode is metal collector 120.
Step 290 is described to be continuously formed in the reverse side of the wafer for the Facad structure for forming the igbt
The process of the inverse layer structure of igbt.
Wherein, the "+" in N-, N+, P+ represents that doping concentration is high, and "-" represents that doping concentration is low.
As can be seen that the generation type and process that focus on N+ types diffusion layer 60 of the present invention, other knots in IGBT
The formation of structure can perform with reference to normal manufacturing process.
Compared with prior art, the present invention in igbt manufacture method, its after obtained groove 30,
Injected by the groove 30 and spread the first conductive type impurity of high concentration, so as under the second conduction type base layer 20
It is square into the first conduction type diffusion layer 60；And the trap time can be pushed away by control, make the base layer 20 and diffusion layer 60
It is not overlapping.Because the manufacture method is compatible with existing common process, and technique is simple, efficiency high, without special high energy
Facility is injected, therefore, process costs can be substantially reduced；And effectively solve Pbody layers and n type diffused layer interacts
The problem of causing threshold voltage to be difficult to control.
Hereinbefore it is situated between by taking the manufacture method of the insulated gate bipolar transistor of non-punch (NPT) structure as an example
Continue, it is obvious that the manufacture method can be applicable to manufacture field termination（FS）Type insulated gate bipolar transistor, it is only necessary to will walk
Rapid 220 and 230 appropriate make an addition in the common manufacturing method of FS type insulated gate bipolar transistors.
In the above-described embodiments, using first conduction type as N-type, second conduction type be p-type exemplified by carry out
Introduce, in the embodiment of other changes, it is also possible that the first conduction type is p-type, second conduction type is N-type,
The Semiconductor substrate 10 of P-type is now used, the base layer 20 is N-type base layer, and the second main electrode 120 is emitter stage, first
Main electrode 100 is that colelctor electrode, concrete structure and principle are similar to middle igbt above, is not being repeated here.
It is pointed out that any change that one skilled in the art is done to the embodiment of the present invention
All without departing from the scope of claims of the present invention.Correspondingly, the scope of claim of the invention is also not merely limited to
In previous embodiment.
Claims (3)
1. a kind of manufacture method of igbt, it is characterised in that it includes：
The N-type Semiconductor substrate with the first interarea and the second interarea is provided, N-type is the first conduction type；
Pbody layers are formed in the first interarea side of the Semiconductor substrate, the Pbody layers are base layer, and p-type is second conductive
Type；
Hard mask is deposited on the first interarea of the Semiconductor substrate formed with Pbody layers；
The corrosion window of groove is selectively etched on the hard mask；
Trench etching is carried out by the corrosion window, with formed from the first interarea of the Pbody layers through the Pbody layers to
Multiple grooves of Semiconductor substrate；
Sacrificial oxide layer is formed on the groove inner surface of groove；
First conductive type impurity is injected with described to the Semiconductor substrate below the base layer by the groove
The bottom outside of groove forms the first conductivity type implanted region, wherein being noted by the sacrificial oxide layer to the bottom of the groove
Enter the first conductive type impurity；
Carry out high temperature push away trap so that injection region impurity diffusion that the bottom outside of adjacent two grooves is formed and blend with
Base layer the first conduction type diffusion layer formed below, wherein the concentration of the first conductive type impurity of the diffusion layer compared with
The concentration of first conductive type impurity of the Semiconductor substrate is high, and the first conduction type diffusion layer is N+ type diffusion layers,
The remaining Facad structure of the igbt is continuously formed in the front of the wafer formed with N+ type diffusion layers；
The semiconductor layer of the second conduction type is formed in the second interarea side of the Semiconductor substrate, is then served as a contrast in the semiconductor
The second main electrode with the electrical contact of the semiconductor layer of second conduction type is formed on second interarea at bottom.
2. manufacture method according to claim 1, it is characterised in that by controlling the high temperature to push away time of trap to ensure
The base layer and diffusion layer be not overlapping.
3. manufacture method according to claim 1, it is characterised in that it is described in the wafer formed with N+ type diffusion layers just
The remaining Facad structure that face continuously forms the igbt includes：
Remove the hard mask and sacrificial oxide layer；
Grid oxic horizon is formed on the inside of the groove；
Polysilicon gate is formed in the groove；
The N+ optionally formed from the first interarea of the Pbody layers into the Pbody layers on the outside of the groove has
Source region；
The interlayer for covering the groove and partly covering the N+ active areas is formed on the first interarea of the Semiconductor substrate
Dielectric film；
The emitter stage for covering the interlayer dielectric is formed on the first interarea of the Semiconductor substrate.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5751024A (en) * | 1995-03-14 | 1998-05-12 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
| CN102299172A (en) * | 2010-06-23 | 2011-12-28 | 三菱电机株式会社 | Power semiconductor device |
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|---|---|---|---|---|
| JP4823435B2 (en) * | 2001-05-29 | 2011-11-24 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP5564161B2 (en) * | 2007-05-08 | 2014-07-30 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
| JP2009218543A (en) * | 2008-02-15 | 2009-09-24 | Toshiba Corp | Semiconductor device |
| US8735249B2 (en) * | 2011-05-25 | 2014-05-27 | Great Power Semiconductor Corp. | Trenched power semiconductor device and fabrication method thereof |
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| US5751024A (en) * | 1995-03-14 | 1998-05-12 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
| CN102299172A (en) * | 2010-06-23 | 2011-12-28 | 三菱电机株式会社 | Power semiconductor device |
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