CN104331293A - N-order data fitting method and N-order data fitting device based on FPGA - Google Patents
N-order data fitting method and N-order data fitting device based on FPGA Download PDFInfo
- Publication number
- CN104331293A CN104331293A CN201410625753.1A CN201410625753A CN104331293A CN 104331293 A CN104331293 A CN 104331293A CN 201410625753 A CN201410625753 A CN 201410625753A CN 104331293 A CN104331293 A CN 104331293A
- Authority
- CN
- China
- Prior art keywords
- rank
- matrix
- dimension array
- data fitting
- order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000011159 matrix material Substances 0.000 claims abstract description 79
- 238000003491 array Methods 0.000 claims abstract description 6
- 238000004364 calculation method Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 7
- 238000012360 testing method Methods 0.000 claims description 7
- 230000008901 benefit Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 238000013461 design Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 3
- 238000010998 test method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012067 mathematical method Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to an N-order data fitting method and an N-order data fitting device based on an FPGA (field programmable gate array), wherein the N-order data fitting method comprises the following steps: step S100, defining two one-dimensional arrays; step S200, respectively initializing storage signals in two one-dimensional arrays; step S300, calculating an N-order matrix according to the two one-dimensional arrays; and step S400, calculating a fitting coefficient through the N-order matrix. The method realizes the solution of the fitting coefficient of the N-order data, and obtains the fitting curve which has the advantages of high fitting success rate and high accuracy.
Description
Technical field
The invention belongs to data processing field, particularly relate to a kind of N rank data fitting method based on FPGA and N rank data fitting device.
Background technology
Along with the develop rapidly of electronic science and technology, modern electronic product almost penetrates into the every field of society, has effectively promoted the development of social productive forces and the raising of social informatization degree.Especially the appearance of FPGA, very large dirigibility is brought to the design of digital display circuit, traditional Design of Digital System can only design circuit board, systemic-function is realized by designing and make hardware circuit, and new method for designing utilizes eda tool, adopt programming device, realize systemic-function, with software replace hardware by software program design chips.So not only can realize multiple digital logic system function by chip design, and due to the dirigibility of pin definitions, significantly reduce workload and the difficulty of circuit design and board design, thus effectively enhance design.
In the experiment of every field, experiment and exploration usually can produce a large amount of data.Certainly, want the rule knowing that it changes, just need to carry out curve fitting to these measurement data.Curve, is commonly called as and draws curve, is a kind of representation available data being substituted into a numerical expression through mathematical method.Science and engineering problem can by such as sampling, the method such as experiment obtains some discrete data, according to these data, people often wish to obtain a continuous print function (namely curve) or more the discrete equation of crypto set and given data match, this process is just called data fitting.Data fitting is different from the concept of data interpolating, data volume handled by it is large and can not ensure that each data point does not have error, so the function requiring some matchings to obtain is strictly irrational by each data point, interpolating function then must pass through each data point.In practical problems, correctly can disclose the relation between some variable by observation data, and then correct inherent law and the essential attribute being familiar with things, so adopt data fitting to be more added with realistic meaning, people study also deeply continuous it.
Now, carrying out Function Fitting to experimental data value observes its Changing Pattern to obtain the key problem that information model is many engineering fields.In addition, in order to adapt in the world of this diversification, in order to meet the requirement of various application, for various approximating method improvement and research also never stopped.
Summary of the invention
The object of this invention is to provide a kind of N rank data fitting method based on FPGA, to solve the technical matters solved N rank fitting coefficient.
In order to solve the problems of the technologies described above, the invention provides a kind of N rank data fitting method based on FPGA, comprising the steps:
Step S100, defines two one-dimension array.
Step S200, distinguishes initialization to the signal of depositing in two one-dimension array.
Step S300, calculates N rank matrix according to two one-dimension array.
Step S400, goes out fitting coefficient by N rank matrix computations.
Preferably, the method defining two one-dimension array in described step S100 comprises: define respectively two one-dimension array X and Y, and also definition is used for some M signals that each element is temporarily deposited in the matrix of N rank simultaneously.
Preferably, in described step S200, the initialized method of the signal in one-dimension array is comprised: give initial value to for the element depositing signal in the matrix of N rank, and give certain numerical value to each element in X and Y in two one-dimension array.
Preferably, the method calculating N rank matrix according to two one-dimension array in described step S300 comprises: calculate each element in the matrix of N rank according to described two one-dimension array X and Y, to obtain N rank matrix, the result of calculation by described two one-dimension array X and Y gives corresponding M signal respectively.
Preferably, the method going out fitting coefficient by N rank matrix computations in described step S400 comprises: described N rank matrix goes out fitting coefficient by division calculation.
Preferably, described data fitting method also comprises: step S500, obtains N exponent number according to matched curve according to fitting coefficient by least square method.
Preferably, described data fitting method also comprises: step S600, carries out emulation testing, to detect the degree of accuracy of matching to the matched curve obtained.
Preferably, described N exponent number certificate fits to single order data fitting, the method for this single order data fitting, namely
In described step S100, definition is used for some M signals that each element is temporarily deposited in first order matrix; And the initialized method of signal comprises in described step S200: step S210, arranges second-order matrix, and carry out imparting initial value to for the element deposited in this second-order matrix; Step S220, gives certain numerical value to 8 elements in the Y of the X in two one-dimension array; And described step S300 obtains first order matrix, and described step S400 is that first order matrix goes out fitting coefficient by division calculation.
Preferably, described N exponent number is according to fitting to second order data matching, the method for this second order data matching, and namely in described step S100, definition is used for some M signals that each element is temporarily deposited in second-order matrix; And the initialized method of signal comprises in described step S200: step S210 ', arranges third-order matrix, and carry out imparting initial value to for the element deposited in this third-order matrix; Step S220 ', gives certain numerical value to 6 elements in X and Y in two one-dimension array; And described step S300 obtains second-order matrix, and described step S400 is that second-order matrix goes out fitting coefficient by division calculation.
Another aspect, present invention also offers a kind of N rank data fitting device based on FPGA, to solve N exponent number according to the technical matters of carrying out matching.
In order to solve the problems of the technologies described above, a kind of N rank data fitting device based on FPGA, comprising:
Port definition module, for definition signal input, output port; To define arrays module, for defining two one-dimension array; N rank matrix computations module, for calculating N rank matrix according to two one-dimension array; Fitting coefficient computing module, goes out fitting coefficient by N rank matrix computations.
The invention has the beneficial effects as follows, present invention achieves N exponent number solving according to fitting coefficient, and obtain matched curve, this matched curve has and fits to the advantage that power is high, degree of accuracy is high.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described.
Fig. 1 shows the process flow diagram of N rank of the present invention data fitting method;
Fig. 2 shows the process flow diagram of single order data fitting method;
Fig. 3 shows the process flow diagram of second order data approximating method;
Fig. 4 shows the theory diagram of the N rank data fitting device based on FPGA.
Embodiment
In conjunction with the accompanying drawings, the present invention is further detailed explanation.These accompanying drawings are the schematic diagram of simplification, only basic structure of the present invention are described in a schematic way, and therefore it only shows the formation relevant with the present invention.
Embodiment 1
Fig. 1 shows the process flow diagram of N rank of the present invention data fitting method.
As shown in Figure 1, a kind of N rank data fitting method based on FPGA, comprises the steps:
Step S100, defines two one-dimension array.
Step S200, distinguishes initialization to the signal of depositing in two one-dimension array.
Step S300, calculates N rank matrix according to two one-dimension array.
Step S400, goes out fitting coefficient by N rank matrix computations.
Wherein, the method defining two one-dimension array in described step S100 comprises: define respectively two one-dimension array X and Y, and also definition is used for some M signals that each element is temporarily deposited in the matrix of N rank simultaneously.Optionally, described one-dimension array X can be expressed as temperature data, and one-dimension array Y can be expressed as voltage data.
In described step S200, the initialized method of the signal in one-dimension array is comprised: give initial value to for the element depositing signal in the matrix of N rank, and give certain numerical value to each element in X and Y in two one-dimension array.
The method calculating N rank matrix according to two one-dimension array in described step S300 comprises: calculate each element in the matrix of N rank according to described two one-dimension array X and Y, to obtain N rank matrix, the result of calculation by described two one-dimension array X and Y gives corresponding M signal respectively.Concrete, M signal can be used for depositing the summing value of each element in one-dimension array.
The method going out fitting coefficient by N rank matrix computations in described step S400 comprises: described N rank matrix goes out fitting coefficient by division calculation.
Described data fitting method also comprises: step S500, obtains N exponent number according to matched curve according to fitting coefficient by least square method.
Described data fitting method also comprises: step S600, carries out emulation testing to the matched curve obtained.
Embodiment 2
Fig. 2 shows the process flow diagram of single order data fitting method.
The present embodiment is on embodiment 1 basis, realizes the embodiment of single order data fitting.
Described N exponent number is according to fitting to single order data fitting, and the method for this single order data fitting comprises:
Described step S110, definition is used for some M signals that each element is temporarily deposited in first order matrix; And the initialized method of signal comprises in described step S200:
Step S210, arranges second-order matrix, and carries out imparting initial value to for the element deposited in this second-order matrix.
Step S220, gives certain numerical value to the element of 8 in X, the Y in one-dimension array.
And described step S310 obtains first order matrix, and described step S410 is that first order matrix goes out fitting coefficient by division calculation.
Concrete implementation step comprises:
Step (one), definition input/output port: this part defines input port clk in the entity of program, and rst is STD_LOGIC type, and output port a, b are STD_LOGIC_VECTOR type.
Step (two), defines two one-dimension array and intermediate variable: the effect of this module defines accordingly to one-dimension array X and Y exactly, and is defined in some M signals that each element in second-order matrix temporarily deposits; And signal initialization: carry out giving initial value and giving certain numerical value to the element of 8 in one digit number group XY for the elemental signals deposited in second-order matrix to what arrange.Initialization effectively avoids and occurs that emulation makes mistakes, and does not have the problem of Output rusults.
Step (three), calculate second-order matrix module: this module utilizes multiplication in VHDL language, each matrix element in the compute matrix equations such as plus-minus method and forced type transfer functions conv_integer, and the result of calculating is assigned to defines M signal, and when signal definition, figure place should be mated.
Step (four), division routine module: this module utilizes and subtracts the division that ratio juris achieves 14 signed integers, calls this module, achieve solving of fitting coefficient in master routine.
Step (five), test procedure module: this module is mainly used in the emulation testing to master routine, simplifies the test signal number of master routine, and has carried out optimum configurations to clock signal clk and enable signal rst.
Embodiment 3
Fig. 3 shows the process flow diagram of second order data approximating method.
The present embodiment is on embodiment 1 basis, realizes the embodiment of second order data matching.
Described N exponent number is according to fitting to second order data matching, and the method for this second order data matching comprises:
Described step S110 ', definition is used for some M signals that each element is temporarily deposited in second-order matrix; And the initialized method of signal comprises in described step S200:
Step S210 ', arranges third-order matrix, and carries out imparting initial value to for the element deposited in this third-order matrix.
Step S220 ', gives certain numerical value to the element of 6 in X, the Y in one-dimension array.
And described step S310 ', obtain second-order matrix, and described step S410 ', for second-order matrix goes out fitting coefficient by division calculation.
Concrete implementation step comprises:
Step (one), definition input/output port: this part mainly defines input port clk exactly in the entity of master routine, and rst is STD_LOGIC type, output port a2, and a1, a0 are STD_LOGIC_VECTOR type.
Step (two), definition one-dimension array and intermediate variable and the initialization to signal: these two partial actions are identical with single order data fitting, the element number distinguished in the number of signals and one-dimension array X and Y being to define is different, and the XY arranged in second order is 6 elements.
Step (three), calculate third-order matrix and module of inverting thereof: this module utilizes multiplication in VHDL language, plus-minus method etc. calculate each matrix element in third-order matrix equation, and the result of calculating is assigned to defines M signal, and the coupling of figure place during caution signal definition, then utilize adjoint matrix to ask the inverse matrix of former third-order matrix, in the process, also need to call the clearing that dividing module realizes last coefficient results.
Step (four), division routine module: this module utilizes and subtracts the division that ratio juris achieves 99 signed integers, calls this module, realize the formula with digital simulation coefficient that solves of three rank inverse matrixs in master routine.
Step (five), test procedure module: this module is mainly used in the emulation testing to master routine, simplifies the test signal number of master routine, and has carried out optimum configurations to clock signal clk and enable signal rst.
Embodiment 4
Fig. 4 shows the theory diagram of the N rank data fitting device based on FPGA.
On the basis of above-described embodiment 1 to 3, a kind of N rank data fitting device based on FPGA, comprising: port definition module, for definition signal input, output port; To define arrays module, for defining two one-dimension array; N rank matrix computations module, for calculating N rank matrix according to two one-dimension array; Fitting coefficient computing module, goes out fitting coefficient by N rank matrix computations.
With above-mentioned according to desirable embodiment of the present invention for enlightenment, by above-mentioned description, relevant staff in the scope not departing from this invention technological thought, can carry out various change and amendment completely.The technical scope of this invention is not limited to the content on instructions, must determine its technical scope according to right.
Claims (10)
1., based on a N rank data fitting method of FPGA, comprise the steps:
Step S100, defines two one-dimension array;
Step S200, distinguishes initialization to the signal of depositing in two one-dimension array;
Step S300, calculates N rank matrix according to two one-dimension array;
Step S400, goes out fitting coefficient by N rank matrix computations.
2. the N rank data fitting method based on FPGA according to claim 1, is characterized in that, the method defining two one-dimension array in described step S100 comprises:
Define respectively two one-dimension array X and Y, also definition is used for some M signals that each element is temporarily deposited in the matrix of N rank simultaneously.
3. the N rank data fitting method based on FPGA according to claim 2, it is characterized in that, in described step S200, the initialized method of the signal in one-dimension array is comprised: give initial value to for the element depositing signal in the matrix of N rank, and give certain numerical value to each element in X and Y in two one-dimension array.
4. the N rank data fitting method based on FPGA according to claim 3, is characterized in that, the method calculating N rank matrix according to two one-dimension array in described step S300 comprises:
Calculate each element in the matrix of N rank according to described two one-dimension array X and Y, to obtain N rank matrix, the result of calculation by described two one-dimension array X and Y gives corresponding M signal respectively.
5. the N rank data fitting method based on FPGA according to claim 4, is characterized in that, the method going out fitting coefficient by N rank matrix computations in described step S400 comprises: described N rank matrix goes out fitting coefficient by division calculation.
6. according to claim 1 or 5 based on the N rank data fitting method of FPGA, it is characterized in that, described N rank data fitting method also comprises:
Step S500, obtains N exponent number according to matched curve according to fitting coefficient by least square method.
7. the N rank data fitting method based on FPGA according to claim 6, it is characterized in that, described data fitting method also comprises:
Step S600, carries out emulation testing to the matched curve obtained.
8. the N rank data fitting method based on FPGA according to claim 5, is characterized in that, described N exponent number certificate fits to single order data fitting, the method for this single order data fitting, namely
In described step S100, definition is used for some M signals that each element is temporarily deposited in first order matrix; And
In described step S200, the initialized method of signal comprises:
Step S210, arranges second-order matrix, and carries out imparting initial value to for the element deposited in this second-order matrix;
Step S220, gives certain numerical value to 8 elements in the Y of the X in two one-dimension array;
And described step S300 obtains first order matrix, and
Described step S400 is that first order matrix goes out fitting coefficient by division calculation.
9. the N rank data fitting method based on FPGA according to claim 5, is characterized in that, described N exponent number certificate fits to second order data matching, the method for this second order data matching, namely
In described step S100, definition is used for some M signals that each element is temporarily deposited in second-order matrix; And
In described step S200, the initialized method of signal comprises:
Step S210 ', arranges third-order matrix, and carries out imparting initial value to for the element deposited in this third-order matrix;
Step S220 ', gives certain numerical value to 6 elements in X and Y in two one-dimension array;
And described step S300 obtains second-order matrix, and
Described step S400 is that second-order matrix goes out fitting coefficient by division calculation.
10., based on a N rank data fitting device of FPGA, it is characterized in that, comprising:
Port definition module, for definition signal input, output port;
To define arrays module, for defining two one-dimension array;
N rank matrix computations module, for calculating N rank matrix according to two one-dimension array;
Fitting coefficient computing module, goes out fitting coefficient by N rank matrix computations.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410625753.1A CN104331293A (en) | 2014-11-07 | 2014-11-07 | N-order data fitting method and N-order data fitting device based on FPGA |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410625753.1A CN104331293A (en) | 2014-11-07 | 2014-11-07 | N-order data fitting method and N-order data fitting device based on FPGA |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104331293A true CN104331293A (en) | 2015-02-04 |
Family
ID=52406027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410625753.1A Pending CN104331293A (en) | 2014-11-07 | 2014-11-07 | N-order data fitting method and N-order data fitting device based on FPGA |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104331293A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080071492A1 (en) * | 2006-09-20 | 2008-03-20 | Samsung Electronics Co., Ltd. | Method, apparatus, and medium for calibrating compass sensor in consideration of magnetic environment and method, apparatus, and medium for measuring azimuth using the compass sensor calibration method, apparatus, and medium |
CN102759633A (en) * | 2012-07-05 | 2012-10-31 | 上海交通大学 | Real-time rotating speed detection module of servo motor based on FPGA (Field Programmable Gate Array) |
US20130185097A1 (en) * | 2010-09-07 | 2013-07-18 | The Board Of Trustees Of The Leland Stanford Junior University | Medical scoring systems and methods |
CN103514615A (en) * | 2012-06-22 | 2014-01-15 | 通用电气公司 | Method and apparatus for iterative reconstruction |
-
2014
- 2014-11-07 CN CN201410625753.1A patent/CN104331293A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080071492A1 (en) * | 2006-09-20 | 2008-03-20 | Samsung Electronics Co., Ltd. | Method, apparatus, and medium for calibrating compass sensor in consideration of magnetic environment and method, apparatus, and medium for measuring azimuth using the compass sensor calibration method, apparatus, and medium |
US20130185097A1 (en) * | 2010-09-07 | 2013-07-18 | The Board Of Trustees Of The Leland Stanford Junior University | Medical scoring systems and methods |
CN103514615A (en) * | 2012-06-22 | 2014-01-15 | 通用电气公司 | Method and apparatus for iterative reconstruction |
CN102759633A (en) * | 2012-07-05 | 2012-10-31 | 上海交通大学 | Real-time rotating speed detection module of servo motor based on FPGA (Field Programmable Gate Array) |
Non-Patent Citations (2)
Title |
---|
MIKE STRICKLAND: "FPGA协处理的进展", 《今日电子》 * |
彭滢: "基于BSDE的期权定价并行算法研究", 《中国博士学位论文全文数据库 基础科学辑》 * |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Janer et al. | Fully parallel stochastic computation architecture | |
CN105589677A (en) | Systolic structure matrix multiplier based on FPGA (Field Programmable Gate Array) and implementation method thereof | |
CN103837741A (en) | Equal-precision frequency testing system based on FPGA and design method thereof | |
CN104615808B (en) | A kind of test method and reference model device of hardware computation component to be tested | |
Of et al. | The all-floating boundary element tearing and interconnecting method | |
CN104504205A (en) | Parallelizing two-dimensional division method of symmetrical FIR (Finite Impulse Response) algorithm and hardware structure of parallelizing two-dimensional division method | |
CN106385311B (en) | A kind of chaos signal generator of the ignorant simplified system of compound based on FPGA | |
Jiang et al. | Asymptotic waveform evaluation with higher order poles | |
CN104331293A (en) | N-order data fitting method and N-order data fitting device based on FPGA | |
CN107808021B (en) | CFD-based fluid device resistance calculation method | |
CN112836454A (en) | Integrated circuit simulation method and system | |
CN102662917B (en) | Design method of positive-definite Hermite matrix Cholesky decomposition high-speed systolic array | |
US8775496B1 (en) | Circuits and methods for calculating a cholesky decomposition of a matrix | |
Venkataramani et al. | Model-based hardware design | |
CN104809297A (en) | Electromagnetic force density transferring method used among special-shaped grids in magnetic field-structure field coupling calculation | |
CN108536954A (en) | A kind of high-precision Lattice Boltzmann Method based on intersection point interruption gal the Liao Dynasty gold | |
CN103323063A (en) | Ultrasonic flow meter and time difference measuring method thereof | |
Moeller | Field programmable gate arrays for radar front-end digital signal processing | |
Sanyal et al. | An improved combined architecture of the four FDCT algorithms | |
García et al. | Meshless methods with application to liquid composite molding simulation | |
CN104392079A (en) | Equal-chord length curve dividing algorithm of equal margin dividing method | |
Kansa et al. | Fully and sparsely supported radial basis functions | |
Wang et al. | Crank-Nicolson scheme and its error estimates for backward stochastic differential equations | |
CN102253924A (en) | Method for realizing root extraction arithmetic on hardware and root extraction arithmetic device | |
CN103699729A (en) | Modulus multiplier |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150204 |
|
RJ01 | Rejection of invention patent application after publication |