CN102253924A - Method for realizing root extraction arithmetic on hardware and root extraction arithmetic device - Google Patents
Method for realizing root extraction arithmetic on hardware and root extraction arithmetic device Download PDFInfo
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- CN102253924A CN102253924A CN2011102153756A CN201110215375A CN102253924A CN 102253924 A CN102253924 A CN 102253924A CN 2011102153756 A CN2011102153756 A CN 2011102153756A CN 201110215375 A CN201110215375 A CN 201110215375A CN 102253924 A CN102253924 A CN 102253924A
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Abstract
The invention provides a novel method which does not occupy large storage space and can realize root extraction arithmetic on hardware and a root extraction arithmetic device capable of realizing the method. The method comprises the steps of: by adopting a bitwise approaching method, firstly establishing an all-zero register as an intermediate-value register for inputting the nth root value of data; and secondly, determining the initial value of a register variable i, setting the ith bit of the intermediate-value register as 1, and ensuring the nth power of the value of the initialized intermediate-value register is larger than the original input data; then gradually setting up the low order of the intermediate-value register, performing nth power arithmetic on the set value, and comparing an nth power arithmetic result with input data, so as to adjust the setting of the intermediate-value register; and ending the root extraction arithmetic until i is subtracted to zero or the nth power arithmetic result is equal to the input data, and taking the value of the intermediate-value register at the time as the root extraction arithmetic result.
Description
Technical field
The invention belongs to the computing and the data processing technique of hardware platform.
Background technology
Addition subtraction multiplication and division and extracting operation are the most basic computings during science calculating and engineering are used, and they are widely used in repeatedly many fields such as equation solution, mathematical modeling, Error Calculation, data encryption, numerical analysis, probability statistics, Flame Image Process and signal Processing.Computing about integer and floating number has regulation in VLSI (VLSI (very large scale integrated circuit)) standard.Some calculating have realized in FPGA (field programmable gate array).
Though extracting operation is frequent not as addition subtraction multiplication and division uses, yet its calculates relative complex, processing speed is starkly lower than other computings, therefore with FPGA realize fast when n be the comparison difficulty more than or equal to 3 n root computing.At present, find the solution the input data square root algorithm (opening 2 root computings) be suggested multiple, such as Newton iteration method, SRT-redundant arithmetic, nonredundancy algorithm, cordic algorithm etc.These algorithms are comparative maturity, and successfully applies in the hardware circuit design, and it is fast convenient to realize.But if calculate n the root (n is more than or equal to 3) of input data, use above-mentioned algorithm will become very complicated, hardware is realized difficulty and suitable trouble.
Certainly, at present also there are some additive methods to be used to calculate n root of data, calculate such as method by software, but the calculating of this higher level lanquage need be got finger, decoding etc. and be carried out many times multiplication and additive operation then, carry out the chronic of one time n time root calculating, do not reach the two-forty standard of hardware counting circuit.Another is used always, is exactly look-up table.Concrete grammar be exactly will be opened the n power data as the address, the result of its n time root is stored among the ROM as the content of corresponding address.Like this, when quilt of input is opened the data of n root, ROM is inquired about as the address with these data, the result who obtains is exactly its n power root.The employing look-up table needs n root table of prior acquisition and it is stored among the ROM, though this way does not need to calculate, also have following shortcoming: (1) memory capacity is huge.Such as n the root computing that will realize 32bit input data, those 32 powers that just need 2 are the ROM of 4G address space.(2) the processing time-delay is bigger.The time delay that is used to inquire about is bigger, directly causes the clock frequency of digital display circuit to reduce.(3) table look-up for jumbo, it is difficult in maintenance.Mainly be because when needs change n root rounding method, must change the content of high capacity ROM, needed workload is huge.(4) reusability is not high.When needs n power root knot really was accurate to decimal, the capacity of ROM and look-up table content all will be made modification accordingly.
Summary of the invention
Technical matters to be solved by this invention is, provide a kind of new, need not take a large amount of storage spaces, the extracting operation device that can realize the method for extracting operation and realize this method on hardware.
The hardware implementation method of extracting operation may further comprise the steps:
Step 3, processing module are controlled the multiplying module according to the size of n the value in the middle value register are carried out the computing of n power, and the multiplying module exports the result to scratch-pad register, enters step 4 again;
Step 4, comparer are relatively imported the value in the data register and the size of the value in the scratch-pad register, and comparative result is fed back to processing module, enter step 5 again;
Step 5, processing module are provided with the intermediate value register according to comparative result: when the value of input in the data register during greater than the value in the scratch-pad register, renewal i is i-1, and the i bit that scratch-pad register is set is 1, enters step 7 again; When the value of input in the data register during less than the value in the scratch-pad register, resetting the i bit is 0, and upgrading i again is i-1, and it is 1 that the i bit is set, and enters step 7 again; When the value of input in the data register equals value in the scratch-pad register, enter step 8;
Step 7, processing module judge whether i is 0, in this way, then enters step 8, as not, then return step 3;
Step 8, processing module control intermediate value register input to the value of current storage in the result register, and this extracting operation finishes.
Concrete, in the step 2, processing module is determined the initial value of intermediate value register variable i, the value that should guarantee the intermediate value register after the initialization after carrying out the computing of n power greater than the value of input data register.
The present invention adopts approximatioss by turn, the register of opening up one complete 0 earlier is as the intermediate value register of n power root of input data, determine the initial value of a register variable i again, and the i position of putting the intermediate value register is 1, and the n power of value of guaranteeing the intermediate value register after the initialization is greater than original input data.The low level of intermediate value register is set afterwards gradually, and the value after will being provided with is carried out the computing of n power, n power operation result and input data are compared, thereby adjust the setting of intermediate value register, up to i be kept to 0 or n power operation result equal to import data, extracting operation finishes, with the value in this moment intermediate value register as the extracting operation result.
Further, can also guarantee to want in the reality precision that reaches by the result being kept several decimal places.In the step 4, as needs the extracting operation result is accurate to decimal place l, then processing module is controlled comparer earlier the value in the input data register is done shift left operation, and the l that moves to left * n position obtains importing the value after moving to left in the data register; Comparer is relatively imported the value after moving to left in the data register and the size of the value in the scratch-pad register again, and comparative result is fed back to processing module, enters step 5 again.
Realize the extracting operation device of said method, comprise input data register, processing module, intermediate value register, scratch-pad register, evolution result register, multiplying module, comparer;
Described input data register is used to store the data of the pending n of opening power computing, and described n is the positive integer more than or equal to 3;
Described processing module when being used for initialization, is determined the initial value of intermediate value register variable i, described variable i is the i bit of intermediate value register, the i bit of initialization intermediate value register is 1, and all the other bits are 0, and initialization triggers the multiplying module after setting completed; Control the multiplying module according to the size of n and carry out the computing of n power;
According to comparative result the intermediate value register is set, when the value of input in the data register during greater than the value in the scratch-pad register, renewal i is i-1, the i bit that scratch-pad register is set is 1, judge again whether i is 0, in this way, then control the intermediate value register value of current storage is inputed in the result register, as not, then trigger the multiplying module; When the value of input in the data register during less than the value in the scratch-pad register, resetting the i bit is 0, upgrading i again is i-1, it is 1 that the i bit is set, judge again whether i is 0, in this way, then control the intermediate value register value of current storage is inputed in the result register, as not, then trigger the multiplying module; When the value of input in the data register equals value in the scratch-pad register, directly control the intermediate value register value of current storage is exported in the result register;
Described intermediate value register, the intermediate value that is used to store extracting operation;
Described multiplying module is used for the value of middle value register is carried out the computing of n power, exports the result to scratch-pad register, and trigger comparator;
Described scratch-pad register is used to store intermediate value and carries out n power calculated result;
Described comparer is used for relatively importing the value of data register and the size of the value in the scratch-pad register, and comparative result is fed back to processing module;
Described result register, the result who is used to store extracting operation.
Further, processing module is used for, and when the extracting operation result is set to be accurate to decimal place l, then processing module control comparer is done shift left operation to the value in the input data register;
Described comparer is used for, and the value of input in the data register done shift left operation, and the l that moves to left * n position obtains importing the value after moving to left in the data register, relatively imports the value after moving to left in the data register and the size of the value in the scratch-pad register.
The invention has the beneficial effects as follows, calculating by hardware can be saved a large amount of computing times, simple, resource occupation is few and quick and precisely, can be according to the actual needs the result of n power root be kept needed decimal digits to guarantee certain precision.
Description of drawings
Fig. 1 is an extracting operation device synoptic diagram;
Fig. 2 is the intermediate computations register synoptic diagram of embodiment;
Fig. 3 is the extracting operation process flow diagram of embodiment;
Fig. 4 carries out 3,4,5,6 power computings respectively for the multiplying module to the value of middle counter register pipelined circuit figure;
Fig. 5 asks the modelsim emulation of cube root to the input data for embodiment.
Embodiment
This enforcement realizes based on FPGA, establishes the signless integer that the input data that need calculating n power root are 16bit, and n is the integer greater than 3 in the present embodiment.Though it is 1 or 2 situation that method of the present invention also goes for n, use this moment this programme not have a computing advantage.Input data and evolution result of calculation all are stored in the middle of the register of 16bit.
The extracting operation device as shown in Figure 1, the extracting operation device comprises input data register, processing module, intermediate value register, scratch-pad register, evolution result register, multiplying module, comparer; Processing module links to each other with the control end of input data register, intermediate value register, multiplying module, comparer respectively; The output terminal of input data register links to each other with an input end of comparer; An output terminal of intermediate value register links to each other with the input end of multiplying module, an output terminal of intermediate value register links to each other with the input end of result register, the output terminal of multiplying module links to each other with the input end of scratch-pad register, and the output terminal of scratch-pad register connects another input end of comparer; The output terminal of comparer links to each other with an input end of processing module.
The storage extracting operation intermediate value intermediate value register r as shown in Figure 2, it is divided into integral part and fraction part.We determine the initial value of register variable i earlier in approaching calculation process, progressively determine i position, the i-1 position of r then ... arrive r at last the 0th.So again the value of register r is outputed to the evolution result register, just obtained the n power root of former input data.The result that this example is provided with n power root keep low 4 as fraction part, a high position is an integral part.The extracting operation process is as shown in Figure 3:
I, input data register receive the 16bit data m of input;
II, processing module are opened up the intermediate value register r of a 16bit complete 0, with its intermediate computations register as the n power root of storage input data m, processing module is simply judged affiliated scope on the m numerical value then, the decimal digits that really keeps according to n power root knot is determined the initial value of register variable i simultaneously, puts the i position r[i of r]=1.Such as, we are boundary with 1023, m simply divides to the 16bit data.As needs m is opened root 5 times, then earlier judge that whether m is greater than 1023.If m＞1023, because (2
4)
5=2
20＞2
16＞m, and the result keep low 4 as fraction part, so we are decided to be 4+4=8 with the i initial value; If m≤1023, because (2
2)
5=210=1024＞m is so we are decided to be 4+2=6 with the i initial value.Here the basis of determining the i initial value is exactly to make to remove decimal place in register r i position 1, it is done 5 power computings after, it is worth necessarily greater than m.We just can begin from high to low from initial bit like this, determine the bit of register r successively, and until the 0th, and the above high position of initial bit is 0.Determine different i values according to the numerical range of m, purpose is to need the number of bits determined among the intermediate value register r in order to reduce, and so just can save some operation times.
III, processing module to register r be provided with finish after, the value among the register r (intermediate value) is inputed to the multiplying module does the computing of n power, and operation result is stored among the scratch-pad register q.The multiplying module needs the value n power among the counter register r.Fig. 4 (a) has provided the pipelined circuit figure that intermediate value is carried out 3 power computings, used 2 multipliers to carry out computing, earlier 2 identical intermediate values are inputed to first multiplier and carry out the multiplying first time, the result of multiplying for the first time and 1 intermediate value input to second multiplier and carry out multiplying second time again, and the result of the multiplying second time is 3 power operation results; Fig. 4 (b) carries out the pipelined circuit figure of 4 power computings to intermediate value, need use 2 multipliers, earlier 2 identical intermediate values are inputed to first multiplier and carry out the multiplying first time, the result of multiplying for the first time is as 2 inputs of second multiplier again, and the result of multiplying for the second time is 4 power operation results; In like manner, Fig. 4 (c), (d) have provided the pipelined circuit figure that intermediate value is carried out 5,6 power computings respectively; Other calculate intermediate values repeatedly side circuit diagram structure all can and the like obtain, also can use other those skilled in the art's habitual circuit structure to realize.In the flow line circuit that the n power of underway value of multiplying module calculates, used multiplier number also determines that according to the n value n is big more, and used multiplier is also many more.But, if the n power that calculates intermediate value without streamline work, whole multiplying module only needs a multiplier to get final product, and the output of multiplier is constantly fed back to input end again, and then can realize the computing of n power equally;
After IV, multiplying module calculate the n power value of intermediate value, the result is stored into after the scratch-pad register q, processing module control comparer is the value and the size of importing data m of scratch-pad register q relatively, because low 4 is fraction part among the register r, and input data m is the signless integer of 16bit, for correct comparison, processing module 4 * n position that at first m should be moved to left obtains m ', then m ' is compared with the n power value (value of scratch-pad register q) of intermediate value, and comparative result is returned processing module;
V, as the value q＞m ' of middle result register, processing module is put r[i]=0, upgrade i=i-1, r[i be set again]=1, judge again whether current i is 0, in this way, processing module outputs to result register with the value among the current intermediate value register r, and current intermediate value is the n power root of input data m, low 4 decimal places for keeping, as not, then return step IV;
As the value q＜m ' of middle result register, processing module keeps r[i]=1 constant, upgrade i=i-1, r[i is set again]=1; Judge whether current i is 0, in this way, processing module outputs to result register with the value among the current intermediate value register r again, and current intermediate value is the n power root of input data m, and low 4 decimal places for keeping as not, are then returned Step II I;
As the value q=m ' of middle result register, processing module outputs to result register with the value among the current intermediate value register r, and current intermediate value is the n power root of input data m, low 4 decimal places for keeping.
By above-mentioned implementation process, we just can calculate the n power root of the 16bit signless integer of input, and low 4 of result is left decimal place, have guaranteed certain precision.
Fig. 5 calculates 3 power root modelsim analogous diagram of input 16bit signless integer for present embodiment.This emulation adopts the nonpipeline mode in order to save hardware resource, so the multiplying module has only used a multiplier to realize the n power computing of intermediate value register.If will adopt pipeline system, then can use a plurality of multipliers, increase hardware spending, but the evolution result can be according to each clock period streamline output.Last two paths of signals line among the figure, the 2nd row din reciprocal is the decimal system form of input 16bit signless integer, last column root_out is the decimal system form of output 3 power roots.Because low four is decimal place, thus with the value of root_out divided by the 16 3 power roots that can obtain importing data, guaranteed the precision of 4 bit positions.Because this emulation is that the boundary has carried out simple division to input data m with 1023, so ask the calculating time-delay of cube root different to the data of different range.Can see from analogous diagram, be 32 clock period to the calculating time-delay of carrying out a cube root computing greater than 1023 data, and simulation clock is 10ns, so time-delay is 320ns.And the calculating of carrying out a cube root computing smaller or equal to 1023 data is delayed time is 26 clock period, and simulation clock is 10ns, so time-delay is 260ns.If according to the actual requirements input data m is carried out more detailed partition, will save more computing time.Obviously as seen, compare other n root account form, the advantage that obviously have simply fast, resource occupation is few.
Extracting operation method and extracting operation device that the present invention proposes, characteristics fast and accurately with hardware computing, implement simple, resource occupation is few, and can guarantee certain precision by actual demand, particularly when n the root that carries out big data quantity calculated, comparing existing extracting operation method had remarkable advantages.
Claims (8)
1. the hardware implementation method of extracting operation is characterized in that, may further comprise the steps:
Step 1, the pending data of opening the computing of n power of input data register storage enter step 2 again, and described n is the positive integer more than or equal to 3;
Step 2, processing module are determined the initial value of intermediate value register variable i, and described variable i is the i bit of intermediate value register; The i bit of initialization intermediate value register is 1, and all the other bits are 0, enter step 3 again;
Step 3, processing module are controlled the multiplying module according to the size of n the value in the middle value register are carried out the computing of n power, and the multiplying module exports the result to scratch-pad register, enters step 4 again;
Step 4, comparer are relatively imported the value in the data register and the size of the value in the scratch-pad register, and comparative result is fed back to processing module, enter step 5 again;
Step 5, processing module are provided with the intermediate value register according to comparative result: when the value of input in the data register during greater than the value in the scratch-pad register, renewal i is i-1, and the i bit that scratch-pad register is set again is 1, enters step 7 again; When the value of input in the data register during less than the value in the scratch-pad register, resetting the i bit is 0, and renewal i is i-1, and it is 1 that the i bit is set again, enters step 7 again; When the value of input in the data register equals value in the scratch-pad register, enter step 8;
Step 7, processing module judge whether i is 0, in this way, then enters step 8, as not, then return step 3;
Step 8, processing module are controlled the value input results register of intermediate value register with current storage, and this extracting operation finishes.
2. the hardware implementation method of extracting operation according to claim 1, it is characterized in that, in the step 2, when processing module is determined the initial value of intermediate value register variable i, guarantee value in the intermediate value register after the initialization value after carrying out the computing of n power greater than the input data register.
3. the hardware implementation method of extracting operation according to claim 1, it is characterized in that, in the step 4, when the extracting operation result is set to be accurate to decimal place l, then processing module is controlled comparer earlier the value in the input data register is done shift left operation, and the l that moves to left * n position obtains importing the value after moving to left in the data register; The value after comparer is relatively imported and moved to left in the data register and the size of the value in the scratch-pad register, and comparative result fed back to processing module, enter step 5 again.
4. the extracting operation device is characterized in that, comprises input data register, processing module, intermediate value register, scratch-pad register, evolution result register, multiplying module, comparer;
Described input data register is used to store the data of the pending n of opening power computing, and described n is the positive integer more than or equal to 3;
Described processing module when being used for initialization, is determined the initial value of intermediate value register variable i, described variable i is the i bit of intermediate value register, the i bit of initialization intermediate value register is 1, and all the other bits are 0, and initialization triggers the multiplying module after setting completed; Control the multiplying module according to the size of n and carry out the computing of n power;
According to comparative result the intermediate value register is set, when the value of input in the data register during greater than the value in the scratch-pad register, renewal i is i-1, the i bit that scratch-pad register is set again is 1, judge again whether i is 0, in this way, then control the value input results register of intermediate value register current storage, as not, then trigger the multiplying module; When the value of input in the data register during less than the value in the scratch-pad register, resetting the i bit is 0, upgrading i again is i-1, it is 1 that the i bit is set, judge again whether i is 0, in this way, then control the intermediate value register value of current storage is inputed in the result register, as not, then trigger the multiplying module; When the value of input in the data register equals value in the scratch-pad register, directly control the value input results register of intermediate value register with current storage;
Described intermediate value register, the intermediate value that is used to store extracting operation;
Described multiplying module is used for the value of middle value register is carried out the computing of n power, exports the result to scratch-pad register, and trigger comparator;
Described scratch-pad register is used to store intermediate value and carries out n power calculated result;
Described comparer is used for relatively importing the value of data register and the size of the value in the scratch-pad register, and comparative result is fed back to processing module;
Described evolution result register, the result who is used to store extracting operation.
5. as extracting operation device as described in the claim 4, it is characterized in that, described processing module, when being used for determining the initial value of intermediate value register variable i, the value that guarantees the intermediate value register after the initialization after carrying out the computing of n power greater than the value of input data register.
6. as extracting operation device as described in the claim 4, it is characterized in that processing module is used for, when the extracting operation result is set to be accurate to decimal place l, then processing module control comparer is done shift left operation to the value in the input data register;
Described comparer is used for, and the value of input in the data register done shift left operation, and the l that moves to left * n position obtains importing the value after moving to left in the data register, relatively imports the value after moving to left in the data register and the size of the value in the scratch-pad register again.
7. as extracting operation device as described in the claim 4, it is characterized in that described multiplying module is the flow line circuit that the multiplier more than 2 or 2 is formed.
8. as extracting operation device as described in the claim 4, it is characterized in that described multiplying module is made of a multiplier.
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| CN111078187A (en) * | 2019-11-28 | 2020-04-28 | 南京大学 | Method for solving arbitrary root of square aiming at single-precision floating point number and solver thereof |
| CN113761451A (en) * | 2020-06-05 | 2021-12-07 | 扬智科技股份有限公司 | Method and device for square root |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111078187A (en) * | 2019-11-28 | 2020-04-28 | 南京大学 | Method for solving arbitrary root of square aiming at single-precision floating point number and solver thereof |
| CN111078187B (en) * | 2019-11-28 | 2021-05-28 | 南京大学 | Method for solving arbitrary root of square aiming at single-precision floating point number and solver thereof |
| CN113761451A (en) * | 2020-06-05 | 2021-12-07 | 扬智科技股份有限公司 | Method and device for square root |
| CN113761451B (en) * | 2020-06-05 | 2024-04-16 | 扬智科技股份有限公司 | Method and apparatus for square root taking |
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