CN104320122A - Digital output buffer and control method thereof - Google Patents
Digital output buffer and control method thereof Download PDFInfo
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- CN104320122A CN104320122A CN201410314231.XA CN201410314231A CN104320122A CN 104320122 A CN104320122 A CN 104320122A CN 201410314231 A CN201410314231 A CN 201410314231A CN 104320122 A CN104320122 A CN 104320122A
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Abstract
The invention discloses a digital output buffer and a control method thereof. The digital output buffer comprises a time sequence generator, an integrator, a residual current detector, an energy accumulator, an inductor L, a load capacitor CL, a first switching tube SW1, a second switching tube SW2 and a third switching tube SW3, wherein the energy accumulator, the inductor L, the load capacitor CL, the first switching tube SW1, the second switching tube SW2 and the third switching tube SW3 construct a main circuit of the digital output buffer; and the integrator and the residual current detector construct a negative feedback circuit of the digital output buffer. Through adoption of the digital output buffer and the control method thereof, the power consumption of the digital output buffer can be effectively lowered.
Description
Technical field
The present invention relates to output buffer technical field, particularly relate to a kind of digital output buffer and control method thereof.
Background technology
Along with the rising of digital signal frequency, need to consume a large amount of power when digital output buffer carries out output buffering to data.Therefore, be necessary to design a kind of digital output buffer reducing power consumption.
China Patent Publication No. CN103269217, publication date on August 28th, 2013, the name of invention is called output buffer, this application case discloses a kind of output buffer, it comprises first and second transistor and autobias circuit, the first transistor has control electrode, couples the input electrode of output and output electrode, transistor seconds has control electrode, couples the input electrode of the output electrode of the first transistor and couple the output electrode of reference voltage, and autobias circuit couples the control electrode of output and the first transistor.Its weak point is, the power consumption of this output buffer is larger.
Summary of the invention
The object of the invention is to overcome the larger technical problem of existing digital output buffer power consumption, provide a kind of digital output buffer and the control method thereof that can reduce power consumption.
In order to solve the problem, the present invention is achieved by the following technical solutions:
A kind of digital output buffer of the present invention, comprise clock generator, integrator, aftercurrent detector, accumulator, inductance L, load capacitance CL, first switching tube SW1, second switch pipe SW2 and the 3rd switching tube SW3, described accumulator one end ground connection, the described accumulator other end is electrically connected with first conduction terminal of the 3rd switching tube SW3, second conduction terminal of described 3rd switching tube SW3 is electrically connected with inductance L one end, the top crown of the described inductance L other end and load capacitance CL, first conduction terminal of the first switching tube SW1 and the first conduction terminal electrical connection of second switch pipe SW2, the bottom crown of described electric capacity CL and the second conduction terminal all ground connection of second switch pipe SW2, second conduction terminal of described first switching tube SW1 is electrically connected with power vd D, the control end of described first switching tube SW1, the control end of second switch pipe SW2 and the control end of the 3rd switching tube SW3 are electrically connected with clock generator respectively, two test sides of described aftercurrent detector are electrically connected with first conduction terminal of the 3rd switching tube SW3 and the second conduction terminal respectively, the described output of aftercurrent detector is electrically connected with the input of integrator, the output of described integrator is electrically connected with the second input of clock generator, the first input end of described clock generator is the signal input part of digital output buffer.
In the technical program, accumulator, inductance L, load capacitance CL, first switching tube SW1, second switch pipe SW2 and the 3rd switching tube SW3 constitutes the main circuit of digital output buffer, its function is by controlling the first switching tube SW1, second switch pipe SW2, 3rd switching tube SW3 control LC vibration is nondestructively moved the electric charge on accumulator on load capacitance CL according to input signal Din, or the electric charge on CL is nondestructively moved on accumulator according to input signal Din, conversion from low level to high level can be realized and from high level to low level conversion like this at delivery outlet Dout.Accumulator can electricity consumption appearance or voltage source realization.First switching tube SW1 and second switch pipe SW2 realizes the reinforcement to the level of digital output Dout, and Dout is maintained in the high level of low-resistance and the low level of low-resistance.
At input signal Din from low transition to high level, jump in low level process by high level again, digital output buffer work is divided into T1, T2, T3 and T4 four-stage, and clock generator controls the first switching tube SW1, second switch pipe SW2 and the 3rd switching tube SW3 works.
When input signal Din is from low transition to high level, enter T1 interval, 3rd switching tube SW3 conducting, first switching tube SW1 and second switch pipe SW2 disconnects, the electric charge stored in accumulator is supplied to inductance L via the 3rd switching tube SW3, because inductance L and load capacitance CL form series resonant circuit, load capacitance CL is filled with voltage due to resonance, the voltage of its top crown can free oscillation to VDD.Interval at T1, the electric current in inductance L to the forward increases from 0, and after peaking, at the voltage oscillation of load capacitance CL top crown to peak, in inductance L, electric current gets back to 0 again.
Then enter T2 interval, the electric current in inductance L gets back to 0 point, is the end point in T1 interval, is the starting point in T2 interval simultaneously.First switching tube SW1 conducting, second switch pipe SW2 and the 3rd switching tube SW3 disconnects, and power vd D is enhanced to the top crown of load capacitance CL by the first switching tube SW1, and the voltage of the top crown of load capacitance CL reaches VDD, and delivery outlet Dout exports high level.
When input signal Din jumps to low level from high level, enter T3 interval, the 3rd switching tube SW3 conducting, the first switching tube SW1 and second switch pipe SW2 disconnects.Electric charge on load capacitance CL is via inductance L, and the 3rd switching tube SW3 is reclaimed by accumulator.This process, the voltage on load capacitance CL is from VDD free oscillation to 0, and the electric current in inductance L oppositely increases to maximum point from 0, then gets back to 0 again.
Then enter T4 interval, the electric current in inductance L gets back to 0 point, is the end point in T3 interval, is the starting point in T4 interval simultaneously.Second switch pipe SW2 conducting, the first switching tube SW1 and the 3rd switching tube SW3 disconnects.Load capacitance CL top crown is enhanced to GND via second switch pipe SW2, delivery outlet Dout output low level.
Integrator and aftercurrent detector constitute the negative-feedback circuit of digital output buffer.Because T1 stage and T3 stage need the electric current in inductance L just to terminate 0 time, thus reduce power consumption, avoid the aftercurrent higher-order of oscillation in inductance L to produce circuit noise.Therefore the duration in clock generator control T1 stage and T3 stage is very important.
The T1 stage is identical with the duration in T3 stage, is all time T.Clock generator is using the numerical value of time value corresponding for the Dsgm value that the up-to-date integrator received exports as time T.Integrator exports Dsgm value and comprises the following steps: integrator arranges an initial value to Dsgm in advance, the corresponding T time value of this initial value, at the end of clock generator controls the 3rd switching tube SW3 conducting T time, aftercurrent detector detects the aftercurrent in inductance L, export Dcmp value to integrator, the direction of Dcmp value reaction aftercurrent, or the direction of Dcmp value reaction aftercurrent and size, integrator carries out integration to Dsgm initial value and the Dcmp value received, obtain up-to-date Dsgm value, and this Dsgm value is outputted to clock generator.Clock generator determines corresponding time value according to this Dsgm value received, and using the value of this time value as time T.
As preferably, described a kind of digital output buffer also comprises detector for error, data processor and frequency divider, the output of described integrator is also electrically connected with the input of detector for error, the output of described detector for error is electrically connected with the input of data processor, the output of described data processor is electrically connected with the second input of frequency divider, the first input end of described frequency divider is electrically connected with the first input end of clock generator, the output of described frequency divider and the clock signal input terminal of detector for error, the clock signal input terminal of integrator and the clock signal input terminal electrical connection of aftercurrent detector.
Detector for error, data processor and frequency divider constitute another negative-feedback circuit of digital output buffer.Detector for error receives the Dsgm value that integrator exports, and calculate the error value E rr of the Dsgm value received, error value E rr is input to data processor by detector for error, data processor calculates the frequency division multiple Fsel of frequency divider according to error value E rr, and frequency division multiple Fsel is sent to frequency divider, frequency divider carries out frequency division according to frequency division multiple Fsel to input signal Din, exports the clock signal clk of respective frequencies to detector for error, integrator and aftercurrent detector.Aftercurrent detector sum-product intergrator is all that clock signal clk triggers.If clock signal clk highest frequency work always, so whole circuit power consumption is comparatively large, if clock signal clk low-limit frequency work always, so whole circuit anti-interference ability is weak, and corresponding speed is slow.Not only the negative-feedback circuit of detector for error, data processor and frequency divider composition makes digital output buffer save power consumption but also have stronger antijamming capability.
As preferably, described accumulator is electric capacity or voltage source.
A kind of digital output buffer control method of the present invention, comprises the following steps:
S1: clock generator reads input signal Din, when input signal Din by low transition to high level time, then perform step S2, when input signal Din by high level saltus step to low level time, then perform step S4;
S2: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1 and second switch pipe SW2 and disconnects T time;
At the end of the S3:T time, clock generator controls the first switching tube SW1 conducting, controls second switch pipe SW2 and the 3rd switching tube SW3 and disconnects;
S4: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1 and second switch pipe SW2 and disconnects T time;
At the end of the S5:T time, time schedule controller control second switch pipe SW2 conducting, controls the first switching tube SW1 and the 3rd switching tube SW3 disconnects;
Clock generator is using the numerical value of time value corresponding for the Dsgm value that the up-to-date integrator received exports as time T, integrator exports Dsgm value and comprises the following steps: integrator arranges an initial value to Dsgm in advance, the corresponding time value of this initial value, namely this time value is the initial value of time T, terminate when clock generator controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, aftercurrent detector detects the aftercurrent in inductance L, export Dcmp value to integrator, the direction of Dcmp value reaction aftercurrent, or the direction of Dcmp value reaction aftercurrent and size, integrator carries out integration to Dsgm initial value and all Dcmp values received, obtain up-to-date Dsgm value, and this Dsgm value is exported.
As preferably, detector for error receives the Dsgm value that integrator exports, and calculate the error value E rr of the Dsgm value received, error value E rr is input to data processor by detector for error, data processor calculates the frequency division multiple Fsel of frequency divider according to error value E rr, and frequency division multiple Fsel is sent to frequency divider, frequency divider carries out frequency division according to frequency division multiple Fsel to input signal Din, exports the clock signal clk of respective frequencies to detector for error, integrator and aftercurrent detector.
As preferably, the method that described detector for error calculates error value E rr comprises the following steps: the N number of Dsgm value received recently is averaged by detector for error, obtains mean value Dref, then according to formula Err=c* (Dsgm-Dref), c is constant, calculates error value E rr.
As preferably, the method that described data processor calculates frequency division multiple Fsel comprises the following steps: data processor is positive constant according to formula F sel=Fsel0+a*|Err|, Fsel0, and a is positive coefficient, calculates the value of frequency division multiple Fsel.Fsel Serial regulation frequency divider output frequency.Linear algorithm, less error E rr correspond to less frequency divider output frequency, correspond to less circuit power consumption, but its adjustment speed is slower; Larger error E rr correspond to larger frequency divider output frequency, correspond to larger circuit power consumption, but its adjustment speed is faster.Its advantage controls simply.
As preferably, the method that described data processor calculates frequency division multiple Fsel comprises the following steps: data processor is positive constant according to formula F sel=Fsel0+b*e^|Err|, Fsel0, and b is positive coefficient, calculates the value of frequency division multiple Fsel.The advantage of exponentiation algorithm is in error | when Err| is in a big way, whole circuit working economizes power consumption in very low frequency, quiet; After error is comparatively large, increase Fsel fast, circuit work frequency rises fast, and the adjustment speed of circuit increases fast, and the power of circuitry consumes increases fast simultaneously.
As preferably, the method that described data processor calculates frequency division multiple Fsel comprises the following steps: data processor adopts sigma-delta algorithm, according to single order Z territory expression formula: Fsel (Z)=Err (Z)+(1-1/Z) * E (Z), E (Z) is quantizing noise, calculates the value of frequency division multiple Fsel.The output of Fsel (Z) is minimum can be exported as two states, can simplify the design of frequency divider like this.Algorithm adopts the advantage of sigma-delta to be the design that can simplify frequency divider, shortcoming introduces quantizing noise, but sigma-delta algorithm itself noise can be shifted onto front end, like this by Substrate coupling, the noise that power supply is coupled near the signal frequency point in system can be ignored.
Substantial effect of the present invention is: the power consumption effectively reducing digital output buffer, ensure that digital output buffer has stronger antijamming capability, avoids the aftercurrent higher-order of oscillation in inductance L to produce circuit noise simultaneously.
Accompanying drawing explanation
Fig. 1 is that a kind of circuit theory of the present invention connects block diagram;
Fig. 2 is the structural representation of detector for error;
Fig. 3 is a kind of workflow diagram of the present invention;
Fig. 4 is the control signal sequential chart of a work period of the present invention.
In figure: 1, clock generator, 2, integrator, 3, aftercurrent detector, 4, accumulator, 5, detector for error, 6, data processor, 7, frequency divider, 8, error op device, 9, dynamic reference maker.
Embodiment
Below by embodiment, and by reference to the accompanying drawings, technical scheme of the present invention is described in further detail.
Embodiment: a kind of digital output buffer of the present invention, as shown in Figure 1, comprise clock generator 1, integrator 2, aftercurrent detector 3, accumulator 4, detector for error 5, data processor 6, frequency divider 7, inductance L, load capacitance CL, first switching tube SW1, second switch pipe SW2 and the 3rd switching tube SW3, accumulator 4 one end ground connection, accumulator 4 other end is electrically connected with first conduction terminal of the 3rd switching tube SW3, second conduction terminal of the 3rd switching tube SW3 is electrically connected with inductance L one end, the top crown of the inductance L other end and load capacitance CL, first conduction terminal of the first switching tube SW1 and the first conduction terminal electrical connection of second switch pipe SW2, the bottom crown of electric capacity CL and the second conduction terminal all ground connection of second switch pipe SW2, second conduction terminal of the first switching tube SW1 is electrically connected with power vd D, the control end of the first switching tube SW1, the control end of second switch pipe SW2 and the control end of the 3rd switching tube SW3 are electrically connected with clock generator 1 respectively, two test sides of aftercurrent detector 3 are electrically connected with first conduction terminal of the 3rd switching tube SW3 and the second conduction terminal respectively, the output of aftercurrent detector 3 is electrically connected with the input of integrator 2, the output of integrator 2 is electrically connected with the input of the second input of clock generator 1 and detector for error 5, the first input end of clock generator 1 is the signal input part of digital output buffer, the output of detector for error 5 is electrically connected with the input of data processor 6, the output of data processor 6 is electrically connected with the second input of frequency divider 7, the first input end of frequency divider 7 is electrically connected with the first input end of clock generator 1, the output of frequency divider 7 and the clock signal input terminal of detector for error 5, the clock signal input terminal of integrator 2 and the clock signal input terminal electrical connection of aftercurrent detector 3.
Accumulator, inductance L, load capacitance CL, first switching tube SW1, second switch pipe SW2 and the 3rd switching tube SW3 constitutes the main circuit of digital output buffer, its function is by controlling the first switching tube SW1, second switch pipe SW2, 3rd switching tube SW3 control LC vibration is nondestructively moved the electric charge on accumulator on load capacitance CL according to input signal Din, or the electric charge on CL is nondestructively moved on accumulator according to input signal Din, conversion from low level to high level can be realized and from high level to low level conversion like this at delivery outlet Dout.Accumulator is electric capacity.First switching tube SW1 and second switch pipe SW2 realizes the reinforcement to the level of digital output Dout, and Dout is maintained in the high level of low-resistance and the low level of low-resistance.
As shown in Figure 4, at input signal Din from low transition to high level, jump in low level process by high level again, digital output buffer work is divided into T1, T2, T3 and T4 four-stage, and clock generator controls the first switching tube SW1, second switch pipe SW2 and the 3rd switching tube SW3 works.
When input signal Din is from low transition to high level, enter T1 interval, 3rd switching tube SW3 conducting, first switching tube SW1 and second switch pipe SW2 disconnects, the electric charge stored in accumulator is supplied to inductance L via the 3rd switching tube SW3, because inductance L and load capacitance CL form series resonant circuit, load capacitance CL is filled with voltage due to resonance, the voltage of its top crown can free oscillation to VDD.Interval at T1, the electric current in inductance L to the forward increases from 0, and after peaking, at the voltage oscillation of load capacitance CL top crown to peak, in inductance L, electric current gets back to 0 again.
Then enter T2 interval, the electric current in inductance L gets back to 0 point, is the end point in T1 interval, is the starting point in T2 interval simultaneously.First switching tube SW1 conducting, second switch pipe SW2 and the 3rd switching tube SW3 disconnects, and power vd D is enhanced to the top crown of load capacitance CL by the first switching tube SW1, and the voltage of the top crown of load capacitance CL reaches VDD, and delivery outlet Dout exports high level.
When input signal Din jumps to low level from high level, enter T3 interval, the 3rd switching tube SW3 conducting, the first switching tube SW1 and second switch pipe SW2 disconnects.Electric charge on load capacitance CL is reclaimed by accumulator via inductance L, the 3rd switching tube SW3.This process, the voltage on load capacitance CL is from VDD free oscillation to 0, and the electric current in inductance L oppositely increases to maximum point from 0, then gets back to 0 again.
Then enter T4 interval, the electric current in inductance L gets back to 0 point, is the end point in T3 interval, is the starting point in T4 interval simultaneously.Second switch pipe SW2 conducting, the first switching tube SW1 and the 3rd switching tube SW3 disconnects.Load capacitance CL top crown is enhanced to GND via second switch pipe SW2, delivery outlet Dout output low level.
Integrator and aftercurrent detector constitute the negative-feedback circuit of digital output buffer.Because T1 stage and T3 stage need the electric current in inductance L just to terminate 0 time, thus reduce power consumption, avoid the aftercurrent higher-order of oscillation in inductance L to produce circuit noise.Therefore the duration in clock generator control T1 stage and T3 stage is very important.
The T1 stage is identical with the duration in T3 stage, is all time T.Clock generator is using the numerical value of time value corresponding for the Dsgm value that the up-to-date integrator received exports as time T.Integrator exports Dsgm value and comprises the following steps: integrator arranges an initial value to Dsgm in advance, the corresponding T time value of this initial value, at the end of clock generator controls the 3rd switching tube SW3 conducting T time, aftercurrent detector detects the aftercurrent in inductance L, export Dcmp value to integrator, the direction of Dcmp value reaction aftercurrent, or the direction of Dcmp value reaction aftercurrent and size, integrator carries out integration to Dsgm initial value and the Dcmp value received, obtain up-to-date Dsgm value, and this Dsgm value is outputted to clock generator.Clock generator determines corresponding time value according to this Dsgm value received, and using the value of this time value as time T.
Detector for error, data processor and frequency divider constitute another negative-feedback circuit of digital output buffer.Detector for error receives the Dsgm value that integrator exports, and calculate the error value E rr of the Dsgm value received, error value E rr is input to data processor by detector for error, data processor calculates the frequency division multiple Fsel of frequency divider according to error value E rr, and frequency division multiple Fsel is sent to frequency divider, frequency divider carries out frequency division according to frequency division multiple Fsel to input signal Din, exports the clock signal clk of respective frequencies to detector for error, integrator and aftercurrent detector.Aftercurrent detector sum-product intergrator is all that clock signal clk triggers.If clock signal clk highest frequency work always, so whole circuit power consumption is comparatively large, if clock signal clk low-limit frequency work always, so whole circuit anti-interference ability is weak, and corresponding speed is slow.Not only the negative-feedback circuit of detector for error, data processor and frequency divider composition makes digital output buffer save power consumption but also have stronger antijamming capability.
As shown in Figure 2, detector for error 5 comprises error op device 8 and dynamic reference maker 9, the input of dynamic reference maker 9 is electrically connected with the output of integrator 2, the output of dynamic reference maker 9 is electrically connected with the first input end of error op device 8, second input of error op device 8 is electrically connected with the output of integrator 2, the output of error op device 8 is electrically connected with the input of data processor 6, and the clock signal input terminal of error op device 8 and the clock signal input terminal of dynamic reference maker 9 are electrically connected with the output of frequency divider 7.Dynamic reference maker 9, according to the characteristic of input Dsgm value, extracts reference signal information Dref, the temporal information of current over-zero in this reference signal Dref reflection inductance L, and it compares with Dsgm value and produces output error value Err.
A kind of digital output buffer control method of the present invention, is applicable to above-mentioned a kind of digital output buffer, comprises the following steps:
S1: clock generator reads input signal Din, when input signal Din by low transition to high level time, then perform step S2, when input signal Din by high level saltus step to low level time, then perform step S4;
S2: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1 and second switch pipe SW2 and disconnects T time;
The electric charge stored in accumulator is supplied to inductance L via the 3rd switching tube SW3, and because inductance L and load capacitance CL form series resonant circuit, load capacitance CL is filled with voltage due to resonance, the voltage of its top crown can free oscillation to VDD.This process, the electric current in inductance L to the forward increases from 0, and after peaking, at the voltage oscillation of load capacitance CL top crown to peak, in inductance L, electric current gets back to 0 again.
At the end of the S3:T time, clock generator controls the first switching tube SW1 conducting, controls second switch pipe SW2 and the 3rd switching tube SW3 and disconnects;
Power vd D is enhanced to the top crown of load capacitance CL by the first switching tube SW1, and the voltage of the top crown of load capacitance CL reaches VDD, and delivery outlet Dout exports high level.
S4: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1 and second switch pipe SW2 and disconnects T time;
Electric charge on load capacitance CL is reclaimed by accumulator via inductance L, the 3rd switching tube SW3.This process, the voltage on load capacitance CL is from VDD free oscillation to 0, and the electric current in inductance L oppositely increases to maximum point from 0, then gets back to 0 again.
At the end of the S5:T time, time schedule controller control second switch pipe SW2 conducting, controls the first switching tube SW1 and the 3rd switching tube SW3 disconnects;
Load capacitance CL top crown is enhanced to GND via second switch pipe SW2, delivery outlet Dout output low level.
Clock generator is using the numerical value of time value corresponding for the Dsgm value that the up-to-date integrator received exports as time T, integrator exports Dsgm value and comprises the following steps: integrator arranges an initial value to Dsgm in advance, the corresponding time value of this initial value, namely this time value is the initial value of time T, terminate when clock generator controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, aftercurrent detector detects the aftercurrent in inductance L, export Dcmp value to integrator, the direction of Dcmp value reaction aftercurrent, or the direction of Dcmp value reaction aftercurrent and size, integrator carries out integration to Dsgm initial value and all Dcmp values received, obtain up-to-date Dsgm value, and this Dsgm value is exported.
Detector for error receives the Dsgm value that integrator exports, and calculate the error value E rr of the Dsgm value received, error value E rr is input to data processor by detector for error, data processor calculates the frequency division multiple Fsel of frequency divider according to error value E rr, and frequency division multiple Fsel is sent to frequency divider, frequency divider carries out frequency division according to frequency division multiple Fsel to input signal Din, exports the clock signal clk of respective frequencies to detector for error, integrator and aftercurrent detector.
The workflow of digital output buffer, as shown in Figure 3.
The method that detector for error calculates error value E rr comprises the following steps: the N number of Dsgm value received recently is averaged by detector for error, obtain mean value Dref, then according to formula Err=c* (Dsgm-Dref), c is constant, calculates error value E rr.
The method that data processor calculates frequency division multiple Fsel comprises the following steps: data processor is positive constant according to formula F sel=Fsel0+a*|Err|, Fsel0, and a is positive coefficient, calculates the value of frequency division multiple Fsel.Fsel Serial regulation frequency divider output frequency.Linear algorithm, less error E rr correspond to less frequency divider output frequency, correspond to less circuit power consumption, but its adjustment speed is slower; Larger error E rr correspond to larger frequency divider output frequency, correspond to larger circuit power consumption, but its adjustment speed is faster.Its advantage controls simply.
The method that data processor calculates frequency division multiple Fsel also realizes by following steps: data processor is positive constant according to formula F sel=Fsel0+b*e^|Err|, Fsel0, and b is positive coefficient, calculates the value of frequency division multiple Fsel.The advantage of exponentiation algorithm is in error | when Err| is in a big way, whole circuit working economizes power consumption in very low frequency, quiet; After error is comparatively large, increase Fsel fast, circuit work frequency rises fast, and the adjustment speed of circuit increases fast, and the power of circuitry consumes increases fast simultaneously.
The method that data processor calculates frequency division multiple Fsel also realizes by following steps: data processor adopts sigma-delta algorithm, according to single order Z territory expression formula: Fsel (Z)=Err (Z)+(1-1/Z) * E (Z), E (Z) is quantizing noise, calculates the value of frequency division multiple Fsel.The output of Fsel (Z) is minimum can be exported as two states, can simplify the design of frequency divider like this.Algorithm adopts the advantage of sigma-delta to be the design that can simplify frequency divider, shortcoming introduces quantizing noise, but sigma-delta algorithm itself noise can be shifted onto front end, like this by Substrate coupling, the noise that power supply is coupled near the signal frequency point in system can be ignored.
Claims (9)
1. a digital output buffer, it is characterized in that: comprise clock generator (1), integrator (2), aftercurrent detector (3), accumulator (4), inductance L, load capacitance CL, first switching tube SW1, second switch pipe SW2 and the 3rd switching tube SW3, described accumulator (4) one end ground connection, described accumulator (4) other end is electrically connected with first conduction terminal of the 3rd switching tube SW3, second conduction terminal of described 3rd switching tube SW3 is electrically connected with inductance L one end, the top crown of the described inductance L other end and load capacitance CL, first conduction terminal of the first switching tube SW1 and the first conduction terminal electrical connection of second switch pipe SW2, the bottom crown of described electric capacity CL and the second conduction terminal all ground connection of second switch pipe SW2, second conduction terminal of described first switching tube SW1 is electrically connected with power vd D, the control end of described first switching tube SW1, the control end of second switch pipe SW2 and the control end of the 3rd switching tube SW3 are electrically connected with clock generator (1) respectively, two test sides of described aftercurrent detector (3) are electrically connected with first conduction terminal of the 3rd switching tube SW3 and the second conduction terminal respectively, the output of described aftercurrent detector (3) is electrically connected with the input of integrator (2), the output of described integrator (2) is electrically connected with the second input of clock generator (1), the first input end of described clock generator (1) is the signal input part of digital output buffer.
2. a kind of digital output buffer according to claim 1, it is characterized in that: also comprise detector for error (5), data processor (6) and frequency divider (7), the output of described integrator (2) is also electrically connected with the input of detector for error (5), the output of described detector for error (5) is electrically connected with the input of data processor (6), the output of described data processor (6) is electrically connected with the second input of frequency divider (7), the first input end of described frequency divider (7) is electrically connected with the first input end of clock generator (1), the output of described frequency divider (7) and the clock signal input terminal of detector for error (5), the clock signal input terminal of integrator (2) and the clock signal input terminal electrical connection of aftercurrent detector (3).
3. a kind of digital output buffer according to claim 1 and 2, is characterized in that: described accumulator (4) is electric capacity or voltage source.
4. a digital output buffer control method, is characterized in that, comprises the following steps:
S1: clock generator reads input signal Din, when input signal Din by low transition to high level time, then perform step S2, when input signal Din by high level saltus step to low level time, then perform step S4;
S2: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1 and second switch pipe SW2 and disconnects T time;
At the end of the S3:T time, clock generator controls the first switching tube SW1 conducting, controls second switch pipe SW2 and the 3rd switching tube SW3 and disconnects;
S4: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1 and second switch pipe SW2 and disconnects T time;
At the end of the S5:T time, time schedule controller control second switch pipe SW2 conducting, controls the first switching tube SW1 and the 3rd switching tube SW3 disconnects;
Clock generator is using the numerical value of time value corresponding for the Dsgm value that the up-to-date integrator received exports as time T, integrator exports Dsgm value and comprises the following steps: integrator arranges an initial value to Dsgm in advance, the corresponding time value of this initial value, namely this time value is the initial value of time T, terminate when clock generator controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, aftercurrent detector detects the aftercurrent in inductance L, export Dcmp value to integrator, the direction of Dcmp value reaction aftercurrent, or the direction of Dcmp value reaction aftercurrent and size, integrator carries out integration to Dsgm initial value and all Dcmp values received, obtain up-to-date Dsgm value, and this Dsgm value is exported.
5. a kind of digital output buffer control method according to claim 4, it is characterized in that, further comprising the steps of: detector for error receives the Dsgm value that integrator exports, and calculate the error value E rr of the Dsgm value received, error value E rr is input to data processor by detector for error, data processor calculates the frequency division multiple Fsel of frequency divider according to error value E rr, and frequency division multiple Fsel is sent to frequency divider, frequency divider carries out frequency division according to frequency division multiple Fsel to input signal Din, export the clock signal clk of respective frequencies to detector for error, integrator and aftercurrent detector.
6. a kind of digital output buffer control method according to claim 5, it is characterized in that, the method that described detector for error calculates error value E rr comprises the following steps: the N number of Dsgm value received recently is averaged by detector for error, obtain mean value Dref, then according to formula Err=c* (Dsgm-Dref), c is constant, calculates error value E rr.
7. a kind of digital output buffer control method according to claim 5 or 6, it is characterized in that, the method that described data processor calculates frequency division multiple Fsel comprises the following steps: data processor is according to formula F sel=Fsel0+a*|Err|, Fsel0 is positive constant, a is positive coefficient, calculates the value of frequency division multiple Fsel.
8. a kind of digital output buffer control method according to claim 5 or 6, it is characterized in that, the method that described data processor calculates frequency division multiple Fsel comprises the following steps: data processor is according to formula F sel=Fsel0+b*e^|Err|, Fsel0 is positive constant, b is positive coefficient, calculates the value of frequency division multiple Fsel.
9. a kind of digital output buffer control method according to claim 5 or 6, it is characterized in that, the method that described data processor calculates frequency division multiple Fsel comprises the following steps: data processor adopts sigma-delta algorithm, according to single order Z territory expression formula: Fsel (Z)=Err (Z)+(1-1/Z) * E (Z), E (Z) is quantizing noise, calculates the value of frequency division multiple Fsel.
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| CN101047378A (en) * | 2006-03-29 | 2007-10-03 | 川崎微电子股份有限公司 | Output buffer circuit and system including the output buffer circuit |
| CN101453207A (en) * | 2007-12-06 | 2009-06-10 | 奇景光电股份有限公司 | Operational amplifier |
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| US20040189354A1 (en) * | 2003-03-25 | 2004-09-30 | Oki Electric Industry Co., Ltd. | Differential current driver and data transmission method |
| CN101047378A (en) * | 2006-03-29 | 2007-10-03 | 川崎微电子股份有限公司 | Output buffer circuit and system including the output buffer circuit |
| CN101453207A (en) * | 2007-12-06 | 2009-06-10 | 奇景光电股份有限公司 | Operational amplifier |
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