CN104393865A - Rapid-starting digital output buffer and control method thereof - Google Patents
Rapid-starting digital output buffer and control method thereof Download PDFInfo
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- CN104393865A CN104393865A CN201410386970.XA CN201410386970A CN104393865A CN 104393865 A CN104393865 A CN 104393865A CN 201410386970 A CN201410386970 A CN 201410386970A CN 104393865 A CN104393865 A CN 104393865A
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Abstract
The invention discloses a rapid-starting digital output buffer and a control method thereof. The digital output buffer comprises a time sequence generator, a capacitor mismatch detector, a capacitor array controller, a switched capacitor array, a current detector, an inductor L, a load capacitor CL, a first switch tube SW1, a second switch tube SW2, a third switch tube SW3, a fourth switch tube SW4 and a fifth switch tube SW5. The time sequence generator, the switched capacitor array, the inductor L, the load capacitor CL, the first switch tube SW1, the second switch tube SW2, the third switch tube SW3, the fourth switch tube SW4 and the fifth switch tube SW5 form a main circuit; the current detector provides negative feedback for the main circuit; and the capacitor mismatch detector and the capacitor array controller form a control circuit capable of quickly starting the switched capacitor array. The rapid-starting digital output buffer and the control method thereof reduce the power consumption of the digital output buffer; and the digital output buffer can be started quickly, and has extremely quick response capability on the change of the load capacitor.
Description
Technical field
The present invention relates to digital output buffer technical field, particularly relate to a kind of startup digital output buffer and control method thereof fast.
Background technology
Along with the rise of transducer, between transducer and main frame, wire signal transmission situation becomes increasingly complex.In some super low-power consumption application scenarios, the transducer most of the time is all be in holding state, in very short time, only complete a sensing and data output.Data are exported by digital output buffer by transducer, along with the rising of digital signal frequency, need to consume a large amount of power when digital output buffer carries out output buffering to data.Therefore, be necessary to design a kind of digital output buffer reducing power consumption.
China Patent Publication No. CN103269217, publication date on August 28th, 2013, the name of invention is called output buffer, this application case discloses a kind of output buffer, it comprises first and second transistor and autobias circuit, the first transistor has control electrode, couples the input electrode of output and output electrode, transistor seconds has control electrode, couples the input electrode of the output electrode of the first transistor and couple the output electrode of reference voltage, and autobias circuit couples the control electrode of output and the first transistor.Its weak point is, the power consumption of this output buffer is larger.
Summary of the invention
The object of the invention is to overcome the larger technical problem of existing digital output buffer power consumption, provide a kind of quick startup digital output buffer and the control method thereof that can reduce power consumption.
In order to solve the problem, the present invention is achieved by the following technical solutions:
One of the present invention starts digital output buffer fast, comprise clock generator, capacitance mismatch detector, capacitor array controller, switched capacitor array, current probe, inductance L, load capacitance CL, first switching tube SW1, second switch pipe SW2, 3rd switching tube SW3, 4th switching tube SW4 and the 5th switching tube SW5, first conduction terminal of described switched capacitor array and first conduction terminal of the 3rd switching tube SW3, first conduction terminal of the 4th switching tube SW4 and the first conduction terminal electrical connection of the 5th switching tube SW5, second conduction terminal of the 4th switching tube SW4 is electrically connected with power vd D, second conduction terminal of the 5th switching tube SW5 and the second conduction terminal all ground connection of switched capacitor array, second conduction terminal of the 3rd switching tube SW3 is electrically connected with inductance L one end, the top crown of the inductance L other end and load capacitance CL, first conduction terminal of the first switching tube SW1, first conduction terminal of second switch pipe SW2 and the test side electrical connection of capacitance mismatch detector, the bottom crown of described load capacitance CL and the second conduction terminal all ground connection of second switch pipe SW2, second conduction terminal of described first switching tube SW1 is electrically connected with power vd D, the output of capacitance mismatch detector is electrically connected with the input of capacitor array controller, capacitor array controller is also electrically connected with the control end of switched capacitor array, the control end of described first switching tube SW1, the control end of second switch pipe SW2, the control end of the 3rd switching tube SW3, the control end of the 4th switching tube SW4, the control end of the 5th switching tube SW5, capacitance mismatch detector and current probe are electrically connected with clock generator respectively, two test sides of described current probe are electrically connected with first conduction terminal of the 3rd switching tube SW3 and the second conduction terminal respectively, the input of described clock generator is the signal input part of digital output buffer, the top crown of described load capacitance CL is the signal output part of digital output buffer.
In the technical program, clock generator, switched capacitor array, inductance L, load capacitance CL, first switching tube SW1, second switch pipe SW2, 3rd switching tube SW3, 4th switching tube SW4 and the 5th switching tube SW5 constitutes the main body circuit starting digital output buffer fast, its function is by controlling the first switching tube SW1, second switch pipe SW2, 3rd switching tube SW3, 4th switching tube SW4 and the 5th switching tube SW5 control LC vibration is nondestructively moved the electric charge on switched capacitor array on load capacitance CL according to input signal Din, and the top crown of load capacitance CL is enhanced to the voltage of power vd D, or the electric charge on CL is nondestructively moved on switched capacitor array according to input signal Din, and the top crown of load capacitance CL is enhanced to ground, conversion from low level to high level can be realized at delivery outlet Dout like this and strengthen and strengthen from high level to low level conversion, achieve the data lossless buffered-display driver from Din to Dout.
First switching tube SW1 and second switch pipe SW2 realizes the reinforcement to the level of digital output Dout, and Dout is maintained in the high level of low-resistance or the low level of low-resistance.4th switching tube SW4 and the 5th switching tube SW5 realizes the reinforcement to the level of the first conduction terminal of switched capacitor array, and the first conduction terminal of switched capacitor array is maintained in the high level of low-resistance or the low level of low-resistance.
At input signal Din from low transition to high level, jump in low level process by high level again, the work of quick startup digital output buffer is divided into T1, T2, T3 and T4 four-stage, and clock generator controls the first switching tube SW1, second switch pipe SW2, the 3rd switching tube SW3, the 4th switching tube SW4 and the 5th switching tube SW5 and works.
When input signal Din is from low transition to high level, enter T1 interval, 3rd switching tube SW3 conducting, first switching tube SW1, second switch pipe SW2, the 4th switching tube SW4 and the 5th switching tube SW5 disconnect, the electric charge stored in switched capacitor array is supplied to inductance L via the 3rd switching tube SW3, because inductance L and load capacitance CL form series resonant circuit, load capacitance CL is filled with voltage due to resonance, the voltage of its top crown can free oscillation to VDD.Interval at T1, the electric current in inductance L to the forward increases from 0, and after peaking, at the voltage oscillation of load capacitance CL top crown to peak, in inductance L, electric current gets back to 0 again.
Then enter T2 interval, the electric current in inductance L gets back to 0 point, is the end point in T1 interval, is the starting point in T2 interval simultaneously.First switching tube SW1, the 5th switching tube SW5 conducting, second switch pipe SW2, the 3rd switching tube SW3 and the 4th switching tube SW4 disconnect, the top crown of load capacitance CL is enhanced to VDD via the first switching tube SW1, the voltage of the top crown of load capacitance CL reaches VDD, delivery outlet Dout exports high level, first conduction terminal of switched capacitor array is enhanced to GND via the 5th switching tube SW5, and the first conduction terminal of switched capacitor array maintains low level.
When input signal Din jumps to low level from high level, enter T3 interval, the 3rd switching tube SW3 conducting, the first switching tube SW1, second switch pipe SW2, the 4th switching tube SW4 and the 5th switching tube SW5 disconnect.Electric charge on load capacitance CL is via inductance L, and the 3rd switching tube SW3 is reclaimed by switched capacitor array.This process, the voltage on load capacitance CL is from VDD free oscillation to 0, and the electric current in inductance L oppositely increases to maximum point from 0, then gets back to 0 again.
Then enter T4 interval, the electric current in inductance L gets back to 0 point, is the end point in T3 interval, is the starting point in T4 interval simultaneously.Second switch pipe SW2 and the 4th switching tube SW4 conducting, the first switching tube SW1, the 3rd switching tube SW3 and the 5th switching tube SW5 disconnect.Load capacitance CL top crown is enhanced to GND via second switch pipe SW2, delivery outlet Dout output low level, and the first conduction terminal of switched capacitor array is enhanced to VDD via the 4th switching tube SW4, and the first conduction terminal of switched capacitor array maintains high level.
Current probe provides negative feedback to main body circuit, owing to terminating when T1 stage and T3 stage need the electric current in inductance L just to become 0, thus reduces power consumption, avoids the aftercurrent higher-order of oscillation in inductance L to produce circuit noise simultaneously.Therefore the duration in clock generator control T1 stage and T3 stage is very important.
The T1 stage is identical with the duration in T3 stage, is all time T.The initial value of time T is provided with in advance in clock generator, terminate when clock generator controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, current probe detects the aftercurrent in inductance L, export Dcmp value to clock generator, the direction of Dcmp value reaction aftercurrent, or Dcmp value reacts direction and the size of aftercurrent, and clock generator is according to the numerical value of the Dcmp value regulation time T received.When 3rd switching tube SW3 disconnects, if current probe has detected that aftercurrent flows to load capacitance CL from inductance L, then time T value has increased, if current probe has detected that aftercurrent flows to inductance L from load capacitance CL, then time T value reduces.
Capacitance mismatch detector and capacitor array controller constitute the auxiliary control circuit of quick start switch capacitor array.Interval at T2, terminate when clock generator controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, simultaneously before the first switching tube SW1, the 5th switching tube SW5 conducting, capacitance mismatch detector detects the voltage V of load capacitance CL top crown, the size of comparative voltage V and power supply vdd voltage, and comparative result is sent to capacitor array controller, capacitor array controller is according to the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received.If voltage V equals power supply vdd voltage, then in switched capacitor array, the on off operating mode of each switched-capacitor circuit is constant; If voltage V is less than power supply vdd voltage, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is increased; If voltage V is greater than power supply vdd voltage, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is reduced.
Interval at T4, terminate when clock generator controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, simultaneously before second switch pipe SW2, the 4th switching tube SW4 conducting, capacitance mismatch detector detects the voltage V of load capacitance CL top crown, the size of comparative voltage V and 0, and comparative result is sent to capacitor array controller, capacitor array controller is according to the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received.If voltage V equals 0, then in switched capacitor array, the on off operating mode of each switched-capacitor circuit is constant; If voltage V is less than 0, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is reduced; If voltage V is greater than 0, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is increased.
The effective capacitance amount Ca of switched capacitor array and the capacity of load capacitance CL is made by the on off operating mode adjusting each switched-capacitor circuit in real time, thus do not need to use huge storage capacitor, need not charge for a long time to huge storage capacitor in order to circuit sets up, save power consumption, simultaneously owing to can start fast the charging interval of the switched capacitor array less digital output buffer that makes.
As preferably, described capacitance mismatch detector comprises data processing module and voltage detection module, the test side of described voltage detection module is electrically connected with the top crown of load capacitance CL, the data output end of described voltage detection module is electrically connected with the input of data processing module, and described data processing module is also electrically connected with clock generator and capacitor array controller respectively.Voltage detection module detects the voltage of load capacitance CL top crown, and data processing module processes the data that voltage detection module detects, and carries out information exchange with clock generator and capacitor array controller.
As preferably, described switched capacitor array comprises the switched-capacitor circuit of several parallel connections, the switch module that described switched-capacitor circuit comprises capacitor and controls by electric capacity array control unit, described capacitor and switch module series connection, the control end of described switch module is electrically connected with capacitor array controller.Capacitor array controller controls the break-make of this switched-capacitor circuit by the switch module in each switched-capacitor circuit, is adjusted the effective capacitance amount Ca of switched capacitor array by the turn-on and turn-off controlling each switched-capacitor circuit.
The control method of a kind of quick startup digital output buffer of the present invention, comprises the following steps:
S1: clock generator reads input signal Din, when input signal Din by low transition to high level time, then perform step S2, when input signal Din by high level saltus step to low level time, then perform step S4;
S2: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1, second switch pipe SW2, the 4th switching tube SW4 and the 5th switching tube SW5 and disconnects T time;
At the end of the S3:T time, clock generator controls second switch pipe SW2, 3rd switching tube SW3 and the 4th switching tube SW4 disconnects, control capacitance mismatch detector detects the voltage V of load capacitance CL top crown when the 3rd switching tube SW3 disconnects, after detection completes, clock generator controls the first switching tube SW1 and the 5th switching tube SW5 conducting, the size of capacitance mismatch detector comparative voltage V and power supply vdd voltage, and comparative result is sent to capacitor array controller, capacitor array controller is according to the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received, make the effective capacitance amount Ca of switched capacitor array and the capacity of load capacitance CL,
S4: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1, second switch pipe SW2, the 4th switching tube SW4 and the 5th switching tube SW5 and disconnects T time;
At the end of the S5:T time, time schedule controller controls the first switching tube SW1, the 3rd switching tube SW3 and the 5th switching tube SW5 and disconnects, and controls second switch pipe SW2 and the 4th switching tube SW4 conducting;
The initial value of time T is provided with in advance in clock generator, terminate when clock generator controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, current probe detects the aftercurrent in inductance L, export Dcmp value to clock generator, the direction of Dcmp value reaction aftercurrent, or Dcmp value reacts direction and the size of aftercurrent, and clock generator is according to the numerical value of the Dcmp value regulation time T received.
As preferably, described clock generator comprises the following steps according to the method for the numerical value of the Dcmp value regulation time T received: clock generator is provided with a Dsgm value corresponding with time value, the time value that the initial value of Dsgm value is corresponding is the initial value of time T, clock generator carries out integration to Dsgm value and the Dcmp value that receives, obtain up-to-date Dsgm value, using the up-to-date numerical value of time value corresponding for this up-to-date Dsgm value as time T.
As preferably, in described step S3, capacitor array controller comprises the following steps according to the method for the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received: if voltage V equals power supply vdd voltage, then in switched capacitor array, the on off operating mode of each switched-capacitor circuit is constant; If voltage V is less than power supply vdd voltage, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is increased; If voltage V is greater than power supply vdd voltage, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is reduced.
As preferably, described step S5 comprises the following steps: at the end of T time, time schedule controller controls the first switching tube SW1, 3rd switching tube SW3 and the 5th switching tube SW5 disconnects, capacitance mismatch detector detects the voltage V of load capacitance CL top crown when the 3rd switching tube SW3 disconnects, after detection completes, clock generator controls second switch pipe SW2 and the 4th switching tube SW4 conducting, the size of capacitance mismatch detector comparative voltage V and 0, and comparative result is sent to capacitor array controller, capacitor array controller is according to the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received, make the effective capacitance amount Ca of switched capacitor array and the capacity of load capacitance CL.
As preferably, in described step S5, capacitor array controller comprises the following steps according to the method for the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received: if voltage V equals 0, then in switched capacitor array, the on off operating mode of each switched-capacitor circuit is constant; If voltage V is less than 0, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is reduced; If voltage V is greater than 0, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is increased.
Substantial effect of the present invention is: (1) effectively reduces the power consumption of digital output buffer.(2) start fast, at once set up stable transfer path, the change simultaneously for load capacitance has the responding ability be exceedingly fast.(3) the aftercurrent higher-order of oscillation in inductance L is avoided to produce circuit noise.(4) have employed electric capacity matching technique, be exactly effective from first data of transmission, and adopt bulky capacitor, in process of establishing, the integrality of data can be destroyed, and just meeting is effective long time data.(5) because the electric capacity in switched capacitor array is all small capacitances, therefore easily switched capacitor array can be integrated into chip internal.
Accompanying drawing explanation
Fig. 1 is that a kind of circuit theory of the present invention connects block diagram;
Fig. 2 is that the circuit theory of capacitance mismatch detector connects block diagram;
Fig. 3 is the control signal sequential chart of a work period of the present invention;
Fig. 4 is electric capacity of the present invention coupling sequential chart.
In figure: 1, clock generator, 2, capacitance mismatch detector, 3, capacitor array controller, 4, switched capacitor array, 5, current probe, 6, data processing module, 7, voltage detection module, 8, capacitor, 9, switch module.
Embodiment
Below by embodiment, and by reference to the accompanying drawings, technical scheme of the present invention is described in further detail.
Embodiment: one of the present invention starts digital output buffer fast, as shown in Figure 1, comprise clock generator 1, capacitance mismatch detector 2, capacitor array controller 3, switched capacitor array 4, current probe 5, inductance L, load capacitance CL, first switching tube SW1, second switch pipe SW2, 3rd switching tube SW3, 4th switching tube SW4 and the 5th switching tube SW5, first conduction terminal of switched capacitor array 4 and first conduction terminal of the 3rd switching tube SW3, first conduction terminal of the 4th switching tube SW4 and the first conduction terminal electrical connection of the 5th switching tube SW5, second conduction terminal of the 4th switching tube SW4 is electrically connected with power vd D, second conduction terminal of the 5th switching tube SW5 and the second conduction terminal all ground connection of switched capacitor array 4, second conduction terminal of the 3rd switching tube SW3 is electrically connected with inductance L one end, the top crown of the inductance L other end and load capacitance CL, first conduction terminal of the first switching tube SW1, first conduction terminal of second switch pipe SW2 and the test side electrical connection of capacitance mismatch detector 2, the bottom crown of load capacitance CL and the second conduction terminal all ground connection of second switch pipe SW2, second conduction terminal of the first switching tube SW1 is electrically connected with power vd D, the output of capacitance mismatch detector 2 is electrically connected with the input of capacitor array controller 3, capacitor array controller 3 is also electrically connected with the control end of switched capacitor array 4, the control end of the first switching tube SW1, the control end of second switch pipe SW2, the control end of the 3rd switching tube SW3, the control end of the 4th switching tube SW4, the control end of the 5th switching tube SW5, capacitance mismatch detector 2 and current probe 5 are electrically connected with clock generator 1 respectively, two test sides of current probe 5 are electrically connected with first conduction terminal of the 3rd switching tube SW3 and the second conduction terminal respectively, the input of clock generator 1 is the signal input part of digital output buffer, the top crown of load capacitance CL is the signal output part of digital output buffer.
As shown in Figure 2, capacitance mismatch detector 2 comprises data processing module 6 and voltage detection module 7, the test side of voltage detection module 7 is electrically connected with the top crown of load capacitance CL, the data output end of voltage detection module 7 is electrically connected with the input of data processing module 6, and data processing module 6 is also electrically connected with clock generator 1 and capacitor array controller 3 respectively.Data processing module 6 is two-way integrator, control by clock generator 1, voltage detection module 7 detects the voltage of load capacitance CL top crown, and the data that data processing module 6 pairs of voltage detection module 7 detect process, and result is sent to capacitor array controller 3.
Switched capacitor array 4 comprises the switched-capacitor circuit of several parallel connections, the switch module 9 that switched-capacitor circuit comprises capacitor 8 and controls by electric capacity array control unit 3, capacitor 8 and switch module 9 are connected, and the control end of switch module 9 is electrically connected with capacitor array controller 3.Capacitor array controller 3 controls the break-make of this switched-capacitor circuit by the switch module 9 in each switched-capacitor circuit, is adjusted the effective capacitance amount Ca of switched capacitor array 4 by the turn-on and turn-off controlling each switched-capacitor circuit.
Clock generator 1, switched capacitor array 4, inductance L, load capacitance CL, first switching tube SW1, second switch pipe SW2, 3rd switching tube SW3, 4th switching tube SW4 and the 5th switching tube SW5 constitutes the main body circuit starting digital output buffer fast, its function is by controlling the first switching tube SW1, second switch pipe SW2, 3rd switching tube SW3, 4th switching tube SW4 and the 5th switching tube SW5 control LC vibration is nondestructively moved the electric charge on switched capacitor array 4 on load capacitance CL according to input signal Din, and the top crown of load capacitance CL is enhanced to the voltage of power vd D, or the electric charge on CL is nondestructively moved on switched capacitor array 4 according to input signal Din, and the top crown of load capacitance CL is enhanced to ground, conversion from low level to high level can be realized at delivery outlet Dout like this and strengthen and strengthen from high level to low level conversion, achieve the data lossless buffered-display driver from Din to Dout.
First switching tube SW1 and second switch pipe SW2 realizes the reinforcement to the level of digital output Dout, and Dout is maintained in the high level of low-resistance or the low level of low-resistance.4th switching tube SW4 and the 5th switching tube SW5 realizes the reinforcement to the level of the first conduction terminal of switched capacitor array 4, and the first conduction terminal of switched capacitor array 4 is maintained in the high level of low-resistance or the low level of low-resistance.
As shown in Figure 3, at input signal Din from low transition to high level, jump in low level process by high level again, the work of quick startup digital output buffer is divided into T1, T2, T3 and T4 four-stage, and clock generator 1 controls the first switching tube SW1, second switch pipe SW2, the 3rd switching tube SW3, the 4th switching tube SW4 and the 5th switching tube SW5 and works.
When input signal Din is from low transition to high level, enter T1 interval, 3rd switching tube SW3 conducting, first switching tube SW1, second switch pipe SW2, the 4th switching tube SW4 and the 5th switching tube SW5 disconnect, the electric charge stored in switched capacitor array 4 is supplied to inductance L via the 3rd switching tube SW3, because inductance L and load capacitance CL form series resonant circuit, load capacitance CL is filled with voltage due to resonance, the voltage of its top crown can free oscillation to VDD.Interval at T1, the electric current in inductance L to the forward increases from 0, and after peaking, at the voltage oscillation of load capacitance CL top crown to peak, in inductance L, electric current gets back to 0 again.
Then enter T2 interval, the electric current in inductance L gets back to 0 point, is the end point in T1 interval, is the starting point in T2 interval simultaneously.First switching tube SW1, the 5th switching tube SW5 conducting, second switch pipe SW2, the 3rd switching tube SW3 and the 4th switching tube SW4 disconnect, the top crown of load capacitance CL is enhanced to VDD via the first switching tube SW1, the voltage of the top crown of load capacitance CL reaches VDD, delivery outlet Dout exports high level, first conduction terminal of switched capacitor array 4 is enhanced to GND via the 5th switching tube SW5, and the first conduction terminal of switched capacitor array 4 maintains low level.
When input signal Din jumps to low level from high level, enter T3 interval, the 3rd switching tube SW3 conducting, the first switching tube SW1, second switch pipe SW2, the 4th switching tube SW4 and the 5th switching tube SW5 disconnect.Electric charge on load capacitance CL is via inductance L, and the 3rd switching tube SW3 is reclaimed by switched capacitor array 4.This process, the voltage on load capacitance CL is from VDD free oscillation to 0, and the electric current in inductance L oppositely increases to maximum point from 0, then gets back to 0 again.
Then enter T4 interval, the electric current in inductance L gets back to 0 point, is the end point in T3 interval, is the starting point in T4 interval simultaneously.Second switch pipe SW2 and the 4th switching tube SW4 conducting, the first switching tube SW1, the 3rd switching tube SW3 and the 5th switching tube SW5 disconnect.Load capacitance CL top crown is enhanced to GND via second switch pipe SW2, delivery outlet Dout output low level, and the first conduction terminal of switched capacitor array 4 is enhanced to VDD via the 4th switching tube SW4, and the first conduction terminal of switched capacitor array 4 maintains high level.
Current probe 5 provides negative feedback to main body circuit, owing to terminating when T1 stage and T3 stage need the electric current in inductance L just to become 0, thus reduces power consumption, avoids the aftercurrent higher-order of oscillation in inductance L to produce circuit noise simultaneously.Therefore the duration in clock generator 1 control T1 stage and T3 stage is very important.
The T1 stage is identical with the duration in T3 stage, is all time T.The initial value of time T is provided with in advance in clock generator 1, terminate when clock generator controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, current probe 5 detects the aftercurrent in inductance L, export Dcmp value to clock generator, the direction of Dcmp value reaction aftercurrent, or Dcmp value reacts direction and the size of aftercurrent, and clock generator 1 is according to the numerical value of the Dcmp value regulation time T received.When 3rd switching tube SW3 disconnects, if current probe 5 has detected that aftercurrent flows to load capacitance CL from inductance L, then time T value has increased, if current probe 5 has detected that aftercurrent flows to inductance L from load capacitance CL, then time T value reduces.
Capacitance mismatch detector 2 and capacitor array controller 3 constitute the auxiliary control circuit of quick start switch capacitor array 4.Switched capacitor array 4 comprises capacitor C
1, C
2c
n, capacitor C
ncapacitance C
n=A × 2
n-1, n=1,2,3 ..., A is constant.
As shown in Figure 4, interval at T2, terminate when clock generator 1 controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, simultaneously before the first switching tube SW1, the 5th switching tube SW5 conducting, voltage detection module 7 detects the voltage V of load capacitance CL top crown, the size of data processing module 6 comparative voltage V and power supply vdd voltage, and comparative result is sent to capacitor array controller 3, capacitor array controller 3 is according to the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array 4 received.If voltage V equals power supply vdd voltage, the numerical value Ctrl that data processing module 6 outputs to capacitor array controller 3 remains unchanged, then in switched capacitor array 4, the on off operating mode of each switched-capacitor circuit is constant, and effective capacitance amount Ca remains unchanged; If voltage V is less than power supply vdd voltage, the numerical value Ctrl that data processing module 6 outputs to capacitor array controller 3 increases, then adjust the on off operating mode of respective switch condenser network in switched capacitor array 4, effective capacitance amount Ca increases; If voltage V is greater than power supply vdd voltage, the numerical value Ctrl that data processing module 6 outputs to capacitor array controller 3 reduces, then adjust the on off operating mode of respective switch condenser network in switched capacitor array 4, effective capacitance amount Ca reduces.
Terminate when clock generator 1 controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, simultaneously before second switch pipe SW2, the 4th switching tube SW4 conducting, voltage detection module 7 detects the voltage V of load capacitance CL top crown, the size of data processing module 6 comparative voltage V and 0, and comparative result is sent to capacitor array controller 3, capacitor array controller 3 is according to the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array 4 received.If voltage V equals 0, the numerical value Ctrl that data processing module 6 outputs to capacitor array controller 3 remains unchanged, then in switched capacitor array 4, the on off operating mode of each switched-capacitor circuit is constant, and effective capacitance amount Ca remains unchanged; If voltage V is less than 0, the numerical value Ctrl that data processing module 6 outputs to capacitor array controller 3 reduces, then adjust the on off operating mode of respective switch condenser network in switched capacitor array 4, effective capacitance amount Ca reduces; If voltage V is greater than 0, the numerical value Ctrl that data processing module 6 outputs to capacitor array controller 3 increases, then adjust the on off operating mode of respective switch condenser network in switched capacitor array 4, effective capacitance amount Ca increases.
The effective capacitance amount Ca of switched capacitor array 4 and the capacity of load capacitance CL is made by the on off operating mode adjusting each switched-capacitor circuit in real time, thus do not need to use huge storage capacitor, need not charge for a long time to huge storage capacitor in order to circuit sets up, save power consumption, simultaneously owing to can start fast the charging interval of the switched capacitor array 4 less digital output buffer that makes.
The control method of a kind of quick startup digital output buffer of the present invention, is applicable to above-mentioned one and starts digital output buffer fast, comprise the following steps:
S1: clock generator reads input signal Din, when input signal Din by low transition to high level time, then perform step S2, when input signal Din by high level saltus step to low level time, then perform step S4;
S2: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1, second switch pipe SW2, the 4th switching tube SW4 and the 5th switching tube SW5 and disconnects T time;
The electric charge stored in switched capacitor array is supplied to inductance L via the 3rd switching tube SW3, and because inductance L and load capacitance CL form series resonant circuit, load capacitance CL is filled with voltage due to resonance, the voltage of its top crown can free oscillation to VDD.This process, the electric current in inductance L to the forward increases from 0, and after peaking, at the voltage oscillation of load capacitance CL top crown to peak, in inductance L, electric current gets back to 0 again.
At the end of the S3:T time, clock generator controls second switch pipe SW2, 3rd switching tube SW3 and the 4th switching tube SW4 disconnects, control capacitance mismatch detector detects the voltage V of load capacitance CL top crown when the 3rd switching tube SW3 disconnects, after detection completes, clock generator controls the first switching tube SW1 and the 5th switching tube SW5 conducting, the size of capacitance mismatch detector comparative voltage V and power supply vdd voltage, and comparative result is sent to capacitor array controller, capacitor array controller is according to the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received, make the effective capacitance amount Ca of switched capacitor array and the capacity of load capacitance CL,
The top crown of load capacitance CL is enhanced to VDD via the first switching tube SW1, the voltage of the top crown of load capacitance CL reaches VDD, delivery outlet Dout exports high level, first conduction terminal of switched capacitor array is enhanced to GND via the 5th switching tube SW5, and the first conduction terminal of switched capacitor array maintains low level.
S4: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1, second switch pipe SW2, the 4th switching tube SW4 and the 5th switching tube SW5 and disconnects T time;
Electric charge on load capacitance CL is via inductance L, and the 3rd switching tube SW3 is reclaimed by switched capacitor array 4.This process, the voltage on load capacitance CL is from VDD free oscillation to 0, and the electric current in inductance L oppositely increases to maximum point from 0, then gets back to 0 again.
At the end of the S5:T time, time schedule controller controls the first switching tube SW1, 3rd switching tube SW3 and the 5th switching tube SW5 disconnects, capacitance mismatch detector detects the voltage V of load capacitance CL top crown when the 3rd switching tube SW3 disconnects, after detection completes, clock generator controls second switch pipe SW2 and the 4th switching tube SW4 conducting, the size of capacitance mismatch detector comparative voltage V and 0, and comparative result is sent to capacitor array controller, capacitor array controller is according to the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received, make the effective capacitance amount Ca of switched capacitor array and the capacity of load capacitance CL,
Load capacitance CL top crown is enhanced to GND via second switch pipe SW2, delivery outlet Dout output low level, and the first conduction terminal of switched capacitor array is enhanced to VDD via the 4th switching tube SW4, and the first conduction terminal of switched capacitor array maintains high level.
The initial value of time T is provided with in advance in clock generator, terminate when clock generator controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, current probe detects the aftercurrent in inductance L, export Dcmp value to clock generator, the direction of Dcmp value reaction aftercurrent, or Dcmp value reacts direction and the size of aftercurrent, and clock generator is according to the numerical value of the Dcmp value regulation time T received.
When 3rd switching tube SW3 disconnects, if current probe has detected that aftercurrent flows to load capacitance CL from inductance L, then time T value has increased, if current probe has detected that aftercurrent flows to inductance L from load capacitance CL, then time T value reduces.
Clock generator comprises the following steps according to the numerical value of the Dcmp value regulation time T received: clock generator is provided with a Dsgm value corresponding with time value, the time value that the initial value of Dsgm value is corresponding is the initial value of time T, clock generator carries out integration to Dsgm value and the Dcmp value that receives, obtain up-to-date Dsgm value, using the up-to-date numerical value of time value corresponding for this up-to-date Dsgm value as time T.
In step S3, capacitor array controller comprises the following steps according to the method for the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received: if voltage V equals power supply vdd voltage, then in switched capacitor array, the on off operating mode of each switched-capacitor circuit is constant; If voltage V is less than power supply vdd voltage, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance of switched capacitor array is increased; If voltage V is greater than power supply vdd voltage, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance of switched capacitor array is reduced.
In step S5, capacitor array controller comprises the following steps according to the method for the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received: if voltage V equals 0, then in switched capacitor array, the on off operating mode of each switched-capacitor circuit is constant; If voltage V is less than 0, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance of switched capacitor array is reduced; If voltage V is greater than 0, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance of switched capacitor array is increased.
Claims (8)
1. one kind starts digital output buffer fast, it is characterized in that: comprise clock generator (1), capacitance mismatch detector (2), capacitor array controller (3), switched capacitor array (4), current probe (5), inductance L, load capacitance CL, first switching tube SW1, second switch pipe SW2, 3rd switching tube SW3, 4th switching tube SW4 and the 5th switching tube SW5, first conduction terminal of described switched capacitor array (4) and first conduction terminal of the 3rd switching tube SW3, first conduction terminal of the 4th switching tube SW4 and the first conduction terminal electrical connection of the 5th switching tube SW5, second conduction terminal of the 4th switching tube SW4 is electrically connected with power vd D, second conduction terminal of the 5th switching tube SW5 and the second conduction terminal all ground connection of switched capacitor array (4), second conduction terminal of the 3rd switching tube SW3 is electrically connected with inductance L one end, the top crown of the inductance L other end and load capacitance CL, first conduction terminal of the first switching tube SW1, first conduction terminal of second switch pipe SW2 and the test side electrical connection of capacitance mismatch detector (3), the bottom crown of described load capacitance CL and the second conduction terminal all ground connection of second switch pipe SW2, second conduction terminal of described first switching tube SW1 is electrically connected with power vd D, the output of capacitance mismatch detector (2) is electrically connected with the input of capacitor array controller (3), capacitor array controller (3) is also electrically connected with the control end of switched capacitor array (4), the control end of described first switching tube SW1, the control end of second switch pipe SW2, the control end of the 3rd switching tube SW3, the control end of the 4th switching tube SW4, the control end of the 5th switching tube SW5, capacitance mismatch detector (2) and current probe (5) are electrically connected with clock generator (1) respectively, two test sides of described current probe (5) are electrically connected with first conduction terminal of the 3rd switching tube SW3 and the second conduction terminal respectively, the input of described clock generator (1) is the signal input part of digital output buffer, the top crown of described load capacitance CL is the signal output part of digital output buffer.
2. one according to claim 1 starts digital output buffer fast, it is characterized in that: described capacitance mismatch detector (2) comprises data processing module (6) and voltage detection module (7), the test side of described voltage detection module (7) is electrically connected with the top crown of load capacitance CL, the data output end of described voltage detection module (7) is electrically connected with the input of data processing module (6), and described data processing module (6) is also electrically connected with clock generator (1) and capacitor array controller (3) respectively.
3. one according to claim 1 and 2 starts digital output buffer fast, it is characterized in that: described switched capacitor array (4) comprises the switched-capacitor circuit of several parallel connections, the switch module (9) that described switched-capacitor circuit comprises capacitor (8) and controls by electric capacity array control unit (3), described capacitor (8) and switch module (9) series connection, the control end of described switch module (9) is electrically connected with capacitor array controller (3).
4. start a control method for digital output buffer fast, it is characterized in that, comprise the following steps:
S1: clock generator reads input signal Din, when input signal Din by low transition to high level time, then perform step S2, when input signal Din by high level saltus step to low level time, then perform step S4;
S2: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1, second switch pipe SW2, the 4th switching tube SW4 and the 5th switching tube SW5 and disconnects T time;
At the end of the S3:T time, clock generator controls second switch pipe SW2, 3rd switching tube SW3 and the 4th switching tube SW4 disconnects, control capacitance mismatch detector detects the voltage V of load capacitance CL top crown when the 3rd switching tube SW3 disconnects, after detection completes, clock generator controls the first switching tube SW1 and the 5th switching tube SW5 conducting, the size of capacitance mismatch detector comparative voltage V and power supply vdd voltage, and comparative result is sent to capacitor array controller, capacitor array controller is according to the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received, make the effective capacitance amount Ca of switched capacitor array and the capacity of load capacitance CL,
S4: clock generator controls the 3rd switching tube SW3 conducting T time, controls the first switching tube SW1, second switch pipe SW2, the 4th switching tube SW4 and the 5th switching tube SW5 and disconnects T time;
At the end of the S5:T time, time schedule controller controls the first switching tube SW1, the 3rd switching tube SW3 and the 5th switching tube SW5 and disconnects, and controls second switch pipe SW2 and the 4th switching tube SW4 conducting;
The initial value of time T is provided with in advance in clock generator, terminate when clock generator controls the 3rd switching tube SW3 conducting T time, namely when the 3rd switching tube SW3 disconnects, current probe detects the aftercurrent in inductance L, export Dcmp value to clock generator, the direction of Dcmp value reaction aftercurrent, or Dcmp value reacts direction and the size of aftercurrent, and clock generator is according to the numerical value of the Dcmp value regulation time T received.
5. the control method of a kind of quick startup digital output buffer according to claim 4, it is characterized in that, described clock generator comprises the following steps according to the method for the numerical value of the Dcmp value regulation time T received: clock generator is provided with a Dsgm value corresponding with time value, the time value that the initial value of Dsgm value is corresponding is the initial value of time T, clock generator carries out integration to Dsgm value and the Dcmp value that receives, obtain up-to-date Dsgm value, using the up-to-date numerical value of time value corresponding for this up-to-date Dsgm value as time T.
6. the control method of a kind of quick startup digital output buffer according to claim 4 or 5, it is characterized in that, in described step S3, capacitor array controller comprises the following steps according to the method for the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received: if voltage V equals power supply vdd voltage, then in switched capacitor array, the on off operating mode of each switched-capacitor circuit is constant; If voltage V is less than power supply vdd voltage, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is increased; If voltage V is greater than power supply vdd voltage, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is reduced.
7. the control method of a kind of quick startup digital output buffer according to claim 4 or 5, it is characterized in that, described step S5 comprises the following steps: at the end of T time, time schedule controller controls the first switching tube SW1, 3rd switching tube SW3 and the 5th switching tube SW5 disconnects, capacitance mismatch detector detects the voltage V of load capacitance CL top crown when the 3rd switching tube SW3 disconnects, after detection completes, clock generator controls second switch pipe SW2 and the 4th switching tube SW4 conducting, the size of capacitance mismatch detector comparative voltage V and 0, and comparative result is sent to capacitor array controller, capacitor array controller is according to the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received, make the effective capacitance amount Ca of switched capacitor array and the capacity of load capacitance CL.
8. the control method of a kind of quick startup digital output buffer according to claim 7, it is characterized in that, in described step S5, capacitor array controller comprises the following steps according to the method for the turn-on and turn-off of each switched-capacitor circuit in the data control switch capacitor array received: if voltage V equals 0, then in switched capacitor array, the on off operating mode of each switched-capacitor circuit is constant; If voltage V is less than 0, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is reduced; If voltage V is greater than 0, then adjusts the on off operating mode of respective switch condenser network in switched capacitor array, the effective capacitance amount Ca of switched capacitor array is increased.
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| PCT/CN2015/086398 WO2016019908A1 (en) | 2014-08-07 | 2015-08-07 | Quick-start digital output buffer and control method therefor |
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| WO2016019908A1 (en) * | 2014-08-07 | 2016-02-11 | 王玮冰 | Quick-start digital output buffer and control method therefor |
| CN106033962A (en) * | 2015-03-11 | 2016-10-19 | 杭州硅星科技有限公司 | Data transmitter having direct-current power function and data sending method |
| CN106033950A (en) * | 2015-03-11 | 2016-10-19 | 杭州硅星科技有限公司 | Multi-path rapid data transmitter and data transmitting method thereof |
| CN106033949A (en) * | 2015-03-11 | 2016-10-19 | 杭州硅星科技有限公司 | Quick data transmitter and data sending method |
| CN106647915A (en) * | 2016-12-05 | 2017-05-10 | 清华大学 | Low dropout regulator adopting digital circuit for compensating for capacitance |
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Also Published As
| Publication number | Publication date |
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| CN104393865B (en) | 2017-07-18 |
| WO2016019908A1 (en) | 2016-02-11 |
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