CN104317762A - Method for adaptively controlling transmitting and receiving directions of RS485 chip by aid of FPGA (field programmable gate array) - Google Patents
Method for adaptively controlling transmitting and receiving directions of RS485 chip by aid of FPGA (field programmable gate array) Download PDFInfo
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- CN104317762A CN104317762A CN201410587592.1A CN201410587592A CN104317762A CN 104317762 A CN104317762 A CN 104317762A CN 201410587592 A CN201410587592 A CN 201410587592A CN 104317762 A CN104317762 A CN 104317762A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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Abstract
The invention discloses a method for adaptively controlling transmitting and receiving directions of an RS485 chip by the aid of an FPGA (field programmable gate array). The method is mainly implemented by the aid of a data transmitting and receiving master control CPU (central processing unit), the adaptive direction control core FPGA, the RS485 chip and a peripheral circuit. The method includes enabling the FPGA and the RS485 chip to simultaneously receive TXD (transmit data) signals transmitted by the CPU, and transmitting RST (reset) signals transmitted by the FPGA to transmitting and receiving direction control pins of the RS485 chip; enabling the FPGA to quickly judge whether the RTS signals are high-level signals or low-level signals according to variation of level of the received TXD signals, enabling the RS485 chip to receive signals when the RTS signals are the low-level signals, and enabling the RS485 chip to transmit signals when the RTS signals are the high-level signals so as to control the transmitting and receiving directions of the RS485 chip. The method has the advantages that designs of hardware principles and improvement on existing hardware can be facilitated, algorithms of the FPGA are stable and reliable and are easy to implement, and accordingly the data communication stability and reliability of RS485 buses can be effectively guaranteed.
Description
Technical field
The invention belongs to digital communication technology field, be specifically related to the method for a kind of FPGA (i.e. field programmable gate array) adaptive control RS485 chip transmit-receive position.
Background technology
RS485 communication has a wide range of applications in the message exchange realizing main website and each master-salve station, and the direction of how control RS485 communication realizes RS485 to stablize communication the very important point.Mainly contain following several method can realize: (1) uses the I/O mouth of CPU to control, and the method driving force is strong, but need software cooperation; (2) CPU is had to be with RTS to control the transmit-receive position that directly can be used for control RS485 of pin (i.e. request send control pin), driving force by force and do not need software to coordinate, but not every CPU is with this function, and general this type pin is few, can be not enough when needs multiple serial communication time; (3) semiduplex RS485 transceiver is made to realize from transmission-receiving function, RTS signal is produced through phase inverter by TXD (data export and send) signal, on increasing between A, B end, pull down resistor coordinates realization simultaneously, method realizes simple, cost is low, but driving force is more weak, antijamming capability is inadequate; (4) on the basis of method (3) by the negative edge time delay of TXD before phase inverter, add driving force to a certain extent, but antijamming capability is still not all right under the condition of outside bad environments.
RS485 chip from transmitting-receiving be now commonplace usage, but this automatic controlling party to communication mechanism driving force weak, when bad environments serious interference, this communication modes can bring error code, causes miscommunication.
Summary of the invention
The main goal of the invention of the present invention is: in the system of existing band multi-serial ports communication, and for increasing the function of controls RS485 chip transmit-receive position or changing RS485 chip from transmitting-receiving is external control direction, the software can not changing existing stable CPU realizes.Circuit increases relatively independent FPGA circuit, realizes RS485 direction of communication control signal, software and hardware all relatively original system is independent, and fast and easy is improved, and can reach the object in the reliably control RS485 communication receiving/transmission direction from outside.
The present invention specifically adopts following technical scheme:
A kind of method of FPGA adaptive control RS485 chip transmit-receive position, it is characterized in that: complete need to provide in the Circuits System of Multi-serial port at one, FPGA is adopted to send the phase inverter of signal TXD as the data that CPU sends, the request to send signal RTS sending corresponding control RS485 chip transmit-receive position from I/O mouth after FPGA gives RS485 chip and sends enable pin, receives enable pin, realizes the control to RS485 chip transmit-receive position.
Said method comprising the steps of:
(1) that first carries out hardware connects to form Multi-serial port Circuits System, and the common I/O mouth of CPU sends TXD signal to the receiving end D of RS485 chip, and the transmitting terminal R of RS485 chip sends data reception signal RXD to the other common I/O mouth of CPU; Data transfer signal TXD is also sent to FPGA by CPU simultaneously, and the I/O mouth of FPGA sends request to send signal RTS to the transmission enable pin of RS485 chip, reception enable pin;
(2) after the Multi-serial port Circuits System described in step (1) powers on, by FPGA, the minimum pulse width of data transfer signal TXD is detected, by the list of inquiry baud rate, determine the baud rate of TXD signal, communicate afterwards and just produce transmitting-receiving control signal by this baud rate, and transmit data with the principle of work of zero propagation circuit;
(3) FPGA repeats the minimum pulse width inquiring about TXD signal, finds that communication baud rate changes, then starts reset, repeat step (2) if detect; Otherwise, enter normal mode of operation, when the TXD signal that FPGA receives is continuously high level, transmission enable pin from FPGA to RS485 chip R E, receive enable pin DE export request to send signal RTS for continue low level, now control RS485 chip is in accepting state, when bus there being differential data signals arrive differential data transmission interface A, B of RS485 chip, this differential signal directly can be received by CPU through the RXD channel between RS485 chip and CPU; Between RS485 chip and CPU, TXD channel has data to transmit, when the negative edge of the start bit of data-signal arrives, transmission enable pin from FPGA to RS485 chip R E, receive the RTS signal that enable pin DE exports and at once become high level, control RS485 chip is in transmission state, the stream compression of TXD channel is changed to differential pair signal and is sent in bus by RS485 chip differential data transmission interface A, B;
(4) when RS485 chip transmission of data, the change of FPGA Real-Time Monitoring TXD signal baud rate, when TXD signal baud rate changes, return step (2), repeat above-mentioned steps, relearn and correct baud rate is set, thus realizing by the control of FPGA to RS485 chip transmit-receive position.
In the present invention, the phase inverter receiving TXD is replaced with FPGA, the multichannel TXD signal sent from CPU is accessed the common I/O mouth of FPGA, corresponding RTS signal is gone out from I/O mouth after the operation of FPGA, the transmission direction of this signal being given RS485 controls pin, when TXD changes, namely RTS achieves and controls the transmit-receive position of RS485.
The present invention has following beneficial effect:
(1) stability of RS485 communication significantly can be promoted by the transmit-receive position of FPGA control RS485 communication;
(2) under the demand having multi-serial ports communication to design, on the basis of existing minimum system circuit, directly can supplement FPGA circuit, only need the software and hardware revising little primary circuit system, be easy to amendment.
Accompanying drawing explanation
Fig. 1 gives the hardware structure diagram of the part adopting the inventive method.
Fig. 2 gives the method flow diagram of FPGA adaptive control RS485 chip transmit-receive position of the present invention.
Fig. 3 is system when just powering on, and FPGA is to the judgement of TXD baud rate.
Fig. 4 is the generation of FPGA control signal RTS when normally working.
Fig. 5 is the state machine diagram of system.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The present invention utilizes RS485 to realize from the principle of transmission circuit.The method is applicable to be with and sends standard RS485 chip that is enable and reception ena-bung function.In Fig. 1 RS485 chip R E, DE pin represent respectively send enable and receive enable pin; D represents the output terminal of driver; R represents the output terminal of chip; A, B represent the differential signal end receiving and send respectively.RS485 is realized by control TXD signal from transmission-receiving function, and TXD signal is in high level when data is received, receives direction controlling pin by after TXD signal inversion, makes RS485 chip be in accepting state, has signal just can realize receiving.When transmission data bit is low, TXD signal is for high after anti-phase, and RS485 chip is in transmission state, and the data of transmission are exactly 0; When transmission data bit is high, TXD signal is low after anti-phase, and RS485 chip is in accepting state, do not send data, but there is upper pull down resistor at the reception of RS485 chip and transmission differential signal end A, B two ends, and receiving end thinks have high level to send over, what receive is just height.
Fig. 2 is the method flow diagram of FPGA adaptive control RS485 chip transmit-receive position of the present invention, and the present invention adopts the method for FPGA adaptive control RS485 chip transmit-receive position specifically to comprise the following steps:
Step 1: that first carries out hardware connects to form Multi-serial port Circuits System.As the signal wiring graph of a relation that Fig. 1 is FPGA adaptive control RS485 chip transmit-receive position method of the present invention, the common I/O mouth of CPU goes out TXD signal to the TXD receiving end of RS485 chip, and the transmitting terminal of RS485 chip sends RXD signal to the I/O mouth of CPU; TXD signal be sent the RTS signal of corresponding control RS485 chip transmit-receive position to the common I/O mouth of FPGA, FPGA to the transmission enable pin of RS485 chip, reception enable pin simultaneously.
Step 2: this Multi-serial port Circuits System powers on and after resetting, the minimum pulse width of FPGA to the TXD signal sent here detects, and by inquiring about conventional baud rate list, analyzes multiple pulse, the baud rate of conjecture signal.Fig. 3 is at the beginning of system electrification, and FPGA judges the baud rate of TXD signal, now if any data transmission, for preventing losing number, by first with the principle of work of zero propagation circuit, by data transmission.As shown in Figure 3, be that RTS signal is in transmission state, now sends 0 when TXD signal is 0, when TXD signal is 1, RTS signal is still high, sends 1, after time delay 30uS, RTS signal becomes low, and now RS485 chip is in accepting state, and the pull-up resistor in outer portion makes the data of transmission be still 1.If the time that TXD is 1 is less than 30uS, to be then continuously transmission state constant for RTS.
Step 3: once baud rate is determined, when there being signal to send here again, just produces transmitting-receiving control signal according to this baud rate.FPGA repeats the minimum pulse width inquiring about TXD signal, and the baud rate determined in step 2, then start reset, repeats step 2; If the baud rate determined in step 2, then enter normal mode of operation, when the TXD signal that FPGA receives is continuously high level, RTS signal is for continuing low level, and now control RS485 chip is in accepting state, has data just can directly to receive; When TXD channel has data to transmit, when the negative edge of start bit arrives, RTS signal becomes high level at once, and now RS485 chip is in transmission state, can by tape verifying position or the data flow of not tape verifying position to take over party.Fig. 4 is that baud rate identification completes, and after pulsewidth has judged, RTS, transmits the data stream of TXD for the cycle with whole frame.As shown in Figure 4, after RTS detects the start bit of TXD, the state of rapid control RS485 sends for continuing, in a complete cycle, the data stream transmitting of TXD is gone out, if the data stream tape verifying position received, just one-period, if not tape verifying position, RTS meeting automatic time delay bit, ensures transmission data integrity.
Step 4: when RS485 chip transmission of data, the change of FPGA still Real-Time Monitoring TXD signal baud rate, when TXD signal baud rate changes, repeats above-mentioned steps, relearns.So just achieve the control to RS485 chip transmit-receive position, achieve the complete communication of RS485, not obliterated data.
Fig. 5 is the state machine of system, after board powers on, the state of acquiescence is ldle, after detecting that TXD signal has negative edge to arrive, state enters into bps_check, start to detect minimum pulse width, before the baud rate that board is supported being detected, state machine maintains bps_check, until detect that board supports baud rate, state enters into package_start, wait for the arrival of next bag data packet head, detection method is the transmitting time of at least one byte of bus free, after arriving in packet header, state enters into TX state (normal operating conditions), now board will carry out the transmission of data according to the baud rate newly detected, if do not change the baud rate of data sending terminal, state machine can maintain TX state always and send data, when the baud rate of transmitting terminal data changes, state machine just can return to idle state and restart.
Claims (2)
1. the method for a FPGA adaptive control RS485 chip transmit-receive position, it is characterized in that: complete need to provide in the Circuits System of Multi-serial port at one, the phase inverter of the data transfer signal TXD adopting FPGA to send as CPU, the request to send signal RTS sending corresponding control RS485 chip transmit-receive position from the I/O mouth of FPGA after FPGA gives RS485 chip and receives enable pin, sends enable pin, realizes the control to RS485 chip transmit-receive position.
2. the method for adaptive control RS485 chip transmit-receive position according to claim 1, is characterized in that, said method comprising the steps of:
(1) that first carries out hardware connects to form Multi-serial port Circuits System, and the common I/O mouth of CPU sends TXD signal to the receiving end D of RS485 chip, and the transmitting terminal R of RS485 chip sends data reception signal RXD to the other common I/O mouth of CPU; Data transfer signal TXD is also sent to FPGA by CPU simultaneously, and the I/O mouth of FPGA sends request to send signal RTS to the transmission enable pin of RS485 chip, reception enable pin;
(2) after the Multi-serial port Circuits System described in step (1) powers on, by FPGA, the minimum pulse width of data transfer signal TXD is detected, by the list of inquiry baud rate, determine the baud rate of TXD signal, communicate afterwards and just produce transmitting-receiving control signal by this baud rate, and transmit data with the principle of work of zero propagation circuit;
(3) FPGA repeats the minimum pulse width inquiring about TXD signal, finds that communication baud rate changes, then starts reset, repeat step (2) if detect; Otherwise, enter normal mode of operation, when the TXD signal that FPGA receives is continuously high level, transmission enable pin from FPGA to RS485 chip R E, receive enable pin DE export request to send signal RTS for continue low level, now control RS485 chip is in accepting state, when bus there being differential data signals arrive differential data transmission interface A, B of RS485 chip, this differential signal directly can be received by CPU through the RXD channel between RS485 chip and CPU; Between RS485 chip and CPU, TXD channel has data to transmit, when the negative edge of the start bit of data-signal arrives, transmission enable pin from FPGA to RS485 chip R E, receive the RTS signal that enable pin DE exports and at once become high level, control RS485 chip is in transmission state, the stream compression of TXD channel is changed to differential pair signal and is sent in bus by RS485 chip differential data transmission interface A, B;
(4) when RS485 chip transmission of data, the change of FPGA Real-Time Monitoring TXD signal baud rate, when TXD signal baud rate changes, return step (2), repeat above-mentioned steps, relearn and correct baud rate is set, thus realizing by the control of FPGA to RS485 chip transmit-receive position.
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| CN201410587592.1A CN104317762A (en) | 2014-10-28 | 2014-10-28 | Method for adaptively controlling transmitting and receiving directions of RS485 chip by aid of FPGA (field programmable gate array) |
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| CN201410587592.1A CN104317762A (en) | 2014-10-28 | 2014-10-28 | Method for adaptively controlling transmitting and receiving directions of RS485 chip by aid of FPGA (field programmable gate array) |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105608298A (en) * | 2016-03-03 | 2016-05-25 | 深圳市同创国芯电子有限公司 | Array package-based FPGA (field programmable gate array) chip |
| CN110572336A (en) * | 2019-09-06 | 2019-12-13 | 南京俊禄科技有限公司 | baud rate identification method of NMEA data |
| CN112838972A (en) * | 2020-12-31 | 2021-05-25 | 广州航天海特系统工程有限公司 | Enabling control method, device and equipment based on RS-485 transceiver and storage medium |
| CN112988648A (en) * | 2021-03-10 | 2021-06-18 | 惠州拓邦电气技术有限公司 | Communication method, device and communication circuit |
| CN113189882A (en) * | 2021-07-01 | 2021-07-30 | 深圳合芯谷微电子有限公司 | IO self-adaptive integrated control circuit and control method |
| CN113872837A (en) * | 2020-06-30 | 2021-12-31 | 配天机器人技术有限公司 | Signal processing method, device and system |
| CN115603729A (en) * | 2022-12-13 | 2023-01-13 | 天津卡雷尔机器人技术有限公司（Cn） | Asynchronous TTL serial port to single bus circuit |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105608298A (en) * | 2016-03-03 | 2016-05-25 | 深圳市同创国芯电子有限公司 | Array package-based FPGA (field programmable gate array) chip |
| CN110572336A (en) * | 2019-09-06 | 2019-12-13 | 南京俊禄科技有限公司 | baud rate identification method of NMEA data |
| CN110572336B (en) * | 2019-09-06 | 2021-09-17 | 南京俊禄科技有限公司 | Baud rate identification method of NMEA data |
| CN113872837A (en) * | 2020-06-30 | 2021-12-31 | 配天机器人技术有限公司 | Signal processing method, device and system |
| CN112838972A (en) * | 2020-12-31 | 2021-05-25 | 广州航天海特系统工程有限公司 | Enabling control method, device and equipment based on RS-485 transceiver and storage medium |
| CN112838972B (en) * | 2020-12-31 | 2022-05-27 | 广州航天海特系统工程有限公司 | Enabling control method, device and equipment based on RS-485 transceiver and storage medium |
| CN112988648A (en) * | 2021-03-10 | 2021-06-18 | 惠州拓邦电气技术有限公司 | Communication method, device and communication circuit |
| CN113189882A (en) * | 2021-07-01 | 2021-07-30 | 深圳合芯谷微电子有限公司 | IO self-adaptive integrated control circuit and control method |
| CN115603729A (en) * | 2022-12-13 | 2023-01-13 | 天津卡雷尔机器人技术有限公司（Cn） | Asynchronous TTL serial port to single bus circuit |
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