CN104301631A - Different-type-of-signal adaptive access circuit and application method thereof - Google Patents
Different-type-of-signal adaptive access circuit and application method thereof Download PDFInfo
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Abstract
The invention discloses a different-type-of-signal adaptive access circuit and an application method thereof. In the circuit disclosed by the invention, a first-type-of-signal demodulation and decoding device is used for inputting a first type of signals into a processor; a second-type-of-signal demodulation and decoding device is connected with the first-type-of-signal demodulation and decoding device and used for inputting a second type of signals into the processor; and the processor is connected with the first-type-of-signal demodulation and decoding device and the second-type-of-signal demodulation and decoding device, and used for discriminating the type of signals connected to the first-type-of-signal demodulation and decoding device or the second-type-of-signal demodulation and decoding device under trigger of interruption feedback signals inputted by the first-type-of-signal demodulation and decoding device or the second-type-of-signal demodulation and decoding device and opening an output path corresponding to the signal type according to a discrimination result, thereby reducing the complexity of a system design and the hardware cost.
Description
Technical field
The present invention relates to safety guard field, in particular to a kind of signal with different type adaptive access circuit and using method thereof.
Background technology
At present, (Operational amplifier, referred to as " amplifier ", has the circuit unit of very high-amplification-factor to adopt operational amplifier in digital hard disc video recorder (DVR) input port coupling.In side circuit, usually jointly form certain functional modules in conjunction with feedback network) or the low-pass filtering of other device composition or high-pass filtering after by analogue camera signal, high-definition signal is separated with simulation, input respective demodulating and decoding module again, thus realize analogue camera signal and the adaptive access of simulating high-definition signal.But the defect of this kind of technical scheme is: not only can increase outside the cost of each road signal access, the discreteness impact of device parameters is comparatively large, and consistency of performance is difficult to be guaranteed; And filter circuit also can exist decay and time delay to useful signal, thus affect picture quality and effect.
For Digital Signal Processing interface end, at demodulating and decoding module and digital signal processor (Digital Signal Processor in correlation technique, referred to as DSP, it is a kind of microprocessor of uniqueness, is to process the device of bulk information with digital signal.Its powerful data-handling capacity and the high speed of service are the two large characteristics making it receive much concern) interface between module adopts CPLD (Complex Programmable Logic Device, referred to as CPLD, it is the digital integrated circuit of a kind of user constitutive logic function voluntarily according to needing separately, its basic design method is by Integrated Development software platform, utilize schematic diagram, the methods such as hardware description language generate corresponding file destination, by download cable, code is sent in objective chip to realize the digital system designed) chip solution, the itu-r bt.656 exported separately after analogue camera signal and simulation high definition camera signal being transformed is (referred to as " BT656 ", which define a parallel hardware interface and be used for the digital video frequency flow of YCbCr of transmission one road 4:2:2, this hardware interface is made up of 8 single data signals and 1 clock signal) or itu-r bt.1120 (referred to as " BT1120 ", which define a parallel hardware interface and be used for the digital video frequency flow of YCbCr of transmission one road 4:2:0, this hardware interface is made up of 16 single data signals and 1 clock signal) signal is input to DSP process after carrying out switch designs.But the defect of this kind of technical scheme is: need to increase exploitation and the maintenance that CPLD carries out program, increase the design complexities of PCB, add interface cost significantly simultaneously.
Summary of the invention
The invention provides a kind of signal with different type adaptive access circuit and using method thereof, at least to solve the problem that the patten's design polytype signal being accessed digital hard disc video recorder mentioned in correlation technique is complicated, increase hardware cost.
According to an aspect of the present invention, a kind of signal with different type adaptive access circuit is provided.
Signal with different type adaptive access circuit according to the embodiment of the present invention comprises: first kind signal receiving decoding device, for inputting first kind signal to processor; Second Type signal receiving decoding device, be connected with first kind signal receiving decoding device, for to processor input Second Type signal, wherein, after Second Type signal receiving decoding device and first kind signal receiving decoding device interconnect, jointly access processor; Processor, be connected with Second Type signal receiving decoding device with first kind signal receiving decoding device respectively, for differentiating the signal type of current access first kind signal receiving decoding device or Second Type signal receiving decoding device under the triggering of the interrupt feed-back signal of first kind signal receiving decoding device or the input of Second Type signal receiving decoding device, and according to differentiating that result opens the output channel corresponding with signal type.
Preferably, first output of first kind signal receiving decoding device and the second output of Second Type signal receiving decoding device carry out line with, and be connected to processor, wherein, the first output and the second output are all for exporting data (DATA) signal of parallel data grabbing card.
Preferably, 3rd output of Second Type signal receiving decoding device carry out with the 4th output of first kind signal receiving decoding device under the control action of tri-state switch line with, and be connected to processor, wherein, the 3rd output and the 4th output are all for exporting clock (CLK) signal of parallel data grabbing card.
Preferably, the 5th output of first kind signal receiving decoding device and the 6th output of Second Type signal receiving decoding device are connected to processor respectively, and wherein, the 5th output and the 6th output are all for exporting interrupt feed-back signal.
Preferably, foregoing circuit also comprises: Signal Regulation device, be connected with Second Type signal receiving decoding device with first kind signal receiving decoding device respectively, for after carry out electrostatic and carrying out surge protection and impedance matching process to the signal of current access first kind signal receiving decoding device or Second Type signal receiving decoding device, AC coupled is to first kind signal receiving decoding device and Second Type signal receiving decoding device.
Preferably, Signal Regulation device comprises: electrostatic protection device, for carrying out electrostatic defending process to the signal of current access; Surge suppresses thyristor, for carrying out carrying out surge protection process to the signal after electrostatic defending process; Terminating resistor and printed circuit board (PCB) walk line impedence, for carrying out impedance matching process to the signal after carrying out surge protection process.
According to a further aspect in the invention, a kind of using method based on above-mentioned signal with different type adaptive access circuit is provided.
Using method according to the signal with different type adaptive access circuit of the embodiment of the present invention comprises: processor receives the interrupt feed-back signal of first kind signal receiving decoding device or the input of Second Type signal receiving decoding device; Processor differentiates the signal type of current access first kind signal receiving decoding device or Second Type signal receiving decoding device under the triggering of interrupt feed-back signal; Processor is according to differentiating that result opens the output channel corresponding with signal type.
Preferably, processor carries out differentiation to the signal type of current access first kind signal receiving decoding device or Second Type signal receiving decoding device and comprises under the triggering of interrupt feed-back signal: processor response interrupt feed-back signal, via inter-integrated circuit (I2C) bus, the lock register in first kind signal receiving decoding device and Second Type signal receiving decoding device and interrupt signal register are read, wherein, first kind signal receiving decoding device or Second Type signal receiving decoding device are when signal type is identical with own type, locking processing is carried out to this signal, and when signal type is different from own type, losing lock process is carried out to this signal, processor differentiates signal type according to reading result.
Preferably, processor comprises according to the differentiation result unlatching output channel corresponding with signal type: processor judges the signal receiving decoding device that the signal of current access first kind signal receiving decoding device or Second Type signal receiving decoding device belongs to; Processor controls tri-state switch and the output channel corresponding to the another kind of type signal demodulating and decoding device except the signal receiving decoding device belonged to except signal is set to high-impedance state, opens the output channel corresponding with the signal receiving decoding device that signal belongs to simultaneously.
Preferably, receive the interrupt feed-back signal of first kind signal receiving decoding device or the input of Second Type signal receiving decoding device at processor before, also comprise: Signal Regulation device carries out electrostatic defending process to the signal of current access; Signal Regulation device carries out carrying out surge protection process to the signal after electrostatic defending process; Signal Regulation device carries out impedance matching process to the signal after carrying out surge protection process, and the signal communication after impedance matching process is coupled to first kind signal receiving decoding device and Second Type signal receiving decoding device.
By the embodiment of the present invention, adopt first kind signal receiving decoding device, for inputting first kind signal to processor, Second Type signal receiving decoding device, is connected with first kind signal receiving decoding device, for inputting Second Type signal to processor, processor, be connected with Second Type signal receiving decoding device with first kind signal receiving decoding device respectively, for differentiating the signal type of current access first kind signal receiving decoding device or Second Type signal receiving decoding device under the triggering of the interrupt feed-back signal of first kind signal receiving decoding device or the input of Second Type signal receiving decoding device, and according to differentiating that result opens the output channel corresponding with signal type, solve the patten's design polytype signal being accessed digital hard disc video recorder mentioned in correlation technique complicated, increase the problem of hardware cost, and then reduce complexity and the hardware cost of system.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, and form a application's part, schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the structured flowchart of the signal with different type adaptive access circuit according to the embodiment of the present invention;
Fig. 2 is the connection diagram of signal with different type adaptive access circuit according to the preferred embodiment of the invention;
Fig. 3 is the flow chart of the using method of signal with different type adaptive access circuit according to the embodiment of the present invention;
Fig. 4 is the structured flowchart of the signal with different type adaptive access system according to the embodiment of the present invention;
Fig. 5 is the structured flowchart of signal with different type adaptive access system according to the preferred embodiment of the invention.
Embodiment
Hereinafter also describe the present invention in detail with reference to accompanying drawing in conjunction with the embodiments.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.
In the following description, except as otherwise noted, the symbol otherwise with reference to the action performed by one or more computer and operation represents each embodiment describing the application.Wherein, computer comprises the various products such as personal computer, server, mobile terminal, employs the equipment that central processing unit (CPU), single-chip microcomputer, digital signal processor (DSP) etc. have a process chip and all can be called computer.Thus, be appreciated that processing unit that this kind of action performed sometimes referred to as computer and operation comprise computer is to the manipulation of the signal of telecommunication representing data with structured form.It is safeguarded in this manipulation transforms data or the position in the accumulator system of computer, and this reshuffles or changes the operation of computer in the mode that those skilled in the art understands.The data structure of service data is the physical location of the memory of the particular community that the form with data defines.But although describe the present invention in above-mentioned context, it does not also mean that restrictive, as understood by those skilled in the art, hereinafter described action and each side of operation also can realize with hardware.
Turn to accompanying drawing, wherein identical reference number refers to identical element, and the principle of the application is shown in a suitable computing environment and realizes.Below describe the embodiment based on described the application, and should not think about the alternative embodiment clearly do not described herein and limit the application.
Following examples can be applied in computer, such as: be applied in personal computer (PC).Also can be applied in the mobile terminal that have employed at present in intelligent operating system, and be not limited to this.Operating system for computer or mobile terminal does not have particular/special requirement, as long as can detect contact, determine whether this contact is consistent with pre-defined rule, and realizes corresponding function according to the attribute of this contact.
Fig. 1 is the structured flowchart of the signal with different type adaptive access circuit according to the embodiment of the present invention.As shown in Figure 1, this signal with different type adaptive access circuit can comprise: first kind signal receiving decoding device 10, for inputting first kind signal to processor 30; Second Type signal receiving decoding device 20, be connected with first kind signal receiving decoding device 10, for inputting Second Type signal to processor 30, wherein, after Second Type signal receiving decoding device 20 and first kind signal receiving decoding device 10 interconnect, jointly processor 30 is accessed; Processor 30, be connected with Second Type signal receiving decoding device 20 with first kind signal receiving decoding device 10 respectively, for differentiating the signal type of current access first kind signal receiving decoding device 10 or Second Type signal receiving decoding device 20 under the triggering of the interrupt feed-back signal of first kind signal receiving decoding device 10 or the input of Second Type signal receiving decoding device 20, and according to differentiating that result opens the output channel corresponding with signal type.
The patten's design polytype signal being accessed digital hard disc video recorder mentioned in correlation technique is complicated, increase hardware cost.Adopt circuit connecting mode as shown in Figure 1, first kind signal receiving decoding device and Second Type signal receiving decoding device are interconnected, simultaneous processor is also connected with first kind signal receiving decoding device and Second Type signal receiving decoding device respectively, the exploitation and the maintenance that use the circuit functions such as existing CPLD can be avoided, solve the problem that the patten's design polytype signal being accessed digital hard disc video recorder mentioned in correlation technique is complicated, increase hardware cost thus, and then reduce complexity and the hardware cost of system.
In preferred implementation process, above-mentioned first kind signal receiving decoding device is HD-TVI signal receiving decoder module, and above-mentioned Second Type signal receiving decoding device is analog signal demodulating and decoding module, and above-mentioned processor is DSP.
" interruption " in above-mentioned interrupt feed-back signal refers to when there is particular demands, and central processing unit (CPU) temporarily stops the execution of present procedure then performs program and the implementation of process new situation.Namely in program operation process, there is a situation that must be processed immediately by CPU in system, and now, CPU supspends the execution of program then processes this news.
HD video coffret (High Definition Transport Video Interface, referred to as HD-TVI), high-definition digital signal is carried out coded modulation and becomes analog signal to carry out long range propagation by camera end, at receiving terminal, this modulation signal is carried out the interface that demodulating and decoding becomes high-definition digital signal.According to the difference of the resolution of high-definition digital signal, can be divided into: 720P25,720P30,720P50,720P60,1080P25 and 1080P30 HD video form.
Preferably, Fig. 2 is the connection diagram of signal with different type adaptive access circuit according to the preferred embodiment of the invention.As shown in Figure 2, first output 100 of first kind signal receiving decoding device 10 carries out line and (wired-AND logic circuits refers to that two or more output direct interconnection just can realize the logic function of " AND ") with the second output 200 of Second Type signal receiving decoding device 20, and be connected to processor 30, wherein, the first output 100 and the second output 200 are all for exporting the DATA signal of parallel data grabbing card (such as: BT656 or BT1120).
Preferably, as shown in Figure 2,3rd output 202 of Second Type signal receiving decoding device 20 carry out with the 4th output 102 of first kind signal receiving decoding device 10 under the control action of tri-state switch 40 line with, and be connected to processor 30, wherein, the 3rd output 202 and the 4th output 102 are all for exporting clock (CLK) signal of parallel data grabbing card.
Tri-state switch refers to that its output both can be normal high level (logical one) or the low level (logical zero) of general two-valued function circuit, can keep again distinctive high impedance status (Hi-Z).When being in high impedance state, its output resistance is very large, is equivalent to open circuit, does not thus possess without any logic control function.The control of the output logic state of three state circuit can be realized by an input pin.
Preferably, as shown in Figure 2,5th output 104 of first kind signal receiving decoding device 10 and the 6th output 204 of Second Type signal receiving decoding device 20 are connected to processor 30 respectively, and wherein, the 5th output 104 and the 6th output 204 are all for exporting interrupt feed-back signal.
Preferably, as shown in Figure 2, foregoing circuit can also comprise: Signal Regulation device 50, be connected with Second Type signal receiving decoding device 20 with first kind signal receiving decoding device 10 respectively, for after carry out electrostatic and carrying out surge protection and impedance matching process to the signal of current access first kind signal receiving decoding device 10 or Second Type signal receiving decoding device 20, AC coupled (AC Coupling, refer to by capacitance coupling eliminate DC component) to first kind signal receiving decoding device 10 and Second Type signal receiving decoding device 20.
Preferably, as shown in Figure 2, Signal Regulation device 50 can comprise: electrostatic protection device 500, for carrying out electrostatic defending process to the signal of current access; Surge suppresses thyristor 502, for carrying out carrying out surge protection process to the signal after electrostatic defending process; Terminating resistor 504 and PCB walk line impedence 506, for carrying out impedance matching process to the signal after carrying out surge protection process.
Formed since Electro-static Driven Comb (Electro-Static discharge, referred to as ESD) is mid-term in 20th century to study the generation of electrostatic, the subject of harm and electrostatic defending etc.The equipment being used for electrostatic defending is accustomed to be referred to as ESD in the world.
Surge (Electrical surge) refers to the peak value occurring exceeding stationary value instantaneously, and it can comprise: surge voltage and surge current.Surge suppresses thyristor (TSS) to be voltage switch type Transient Suppression Diode; namely surge suppresses transistor; or be called semiconductor discharge tube, solid discharging tube etc., its protection device that semiconductor technology can be utilized to make, be mainly used in the lightning protection of signal circuit.The discharge capacity of device generally can reach 150A (8/20uS).
Impedance matching (impedance matching) refers to the specific matching relationship in signals transmission between load impedance and information source internal impedance.Particular kind of relationship should be met, in order to avoid produce significantly impact to the operating state of equipment itself after connecting load between the load impedance that the output impedance of an equipment is connected with it.
As a preferred embodiment of the present invention, the mode that combines of hardware and software is adopted to realize the adaptive access of analogue camera signal and HD-TVI camera signal at camera signal incoming end, effectively can solve the impact of filter circuit on signal, also reduce the cost of equipment and the complexity of design simultaneously.
In Digital Signal Processing interface end, BT656 DATA signal directly " line with " access DSP module after increasing suitable impedance matching and carry out signal transacting can be adopted.After the BT656 CLK signal that analogue camera signal decoding coding exports can be controlled by " tri-state switch " and the BT656 CLK signal that exports of HD-TVI camera signal decoding and coding carry out " line and ", and then access DSP module and carry out signal transacting.Related development and the maintenance of CPLD can not be needed like this, reduce interface exploitation cost significantly.
When signal access be HD-TVI camera signal access time, the compound mode of " TSS+ current-limiting resistance " can be adopted to carry out electrostatic and surge release to this signal path after, signal produces suitable signal level, AC coupled enters " decoding of HD-TVI signal receiving " and " analog signal demodulating and decoding " module through " impedance matching resistor "." decoding of HD-TVI signal receiving " locks this signal, and this signal of " analog signal demodulating and decoding " module losing lock." decoding of HD-TVI signal receiving " module produces " interrupt feed-back signal " and is sent to DSP.DSP is after receiving this feedback signal, inter-integrated circuit (Inter-Integrated Circuit can be passed through, referred to as I2C) (it is the twin wire universal serial bus developed by Philip (PHILIPS) company to bus, for connecting microcontroller and ancillary equipment thereof, it is a kind of bus standard that microelectronics Control on Communication field extensively adopts.It is a kind of special shape of synchronous communication, have that interface line is few, control mode be simple, device package form is little, traffic rate comparatively advantages of higher) what read that " lock register " and " interrupt signal register " of these two modules differentiate access is HD-TVI camera signal.Thus DSP arranges corresponding register by I2C bus and " the BT656 DATA signal " output channel of analogue camera and universal input/output (GPIO) mouth is controlled " tri-state switch " and " BT656 CLK signal " output channel is arranged to high-impedance state or maintenance and powers on the high-impedance state of default setting; Meanwhile, DSP arranges by I2C bus " BT656 signal " output channel that HD-TVI camera opened by corresponding register.DSP judges this " BT656 signal " validity again, if effectively, this closed-circuit working is at HD-TVI camera signal tupe.
When signal access be analogue camera signal access time, the combination of " TSS+ current-limiting resistance " can be adopted to carry out electrostatic and surge release to this signal path after, signal produces suitable signal level, AC coupled enters " decoding of HD-TVI signal receiving " and " analog signal demodulating and decoding " module through " impedance matching resistor "." analog signal demodulating and decoding " module locks this signal, and " decoding of HD-TVI signal receiving " this signal of module losing lock; " analog signal demodulating and decoding " module produces " interrupt feed-back signal " and is sent to DSP.DSP is after receiving this feedback signal, and what can read that " lock register " and " interrupt signal register " of these two modules differentiate access by I2C bus is analogue camera signal.Thus DSP can arrange corresponding register by I2C bus and " BT656 signal " output channel of HD-TVI camera is arranged to high-impedance state or maintenance and power on the high-impedance state of default setting; Meanwhile, DSP arranges by I2C bus " BT656 DATA signal " output channel that analogue camera opened by corresponding register, and GPIO controls " BT656 CLK signal " output channel that " tri-state switch " opens analogue camera.DSP judges this " BT656 signal " validity again, if effectively, this closed-circuit working is at analogue camera signal processing model.
Realize the adaptive access of HD-TVI camera signal and analogue camera signal thus.
Fig. 3 is the flow chart of the using method of signal with different type adaptive access circuit according to the embodiment of the present invention.As shown in Figure 3, the using method of this signal with different type adaptive access circuit can comprise following treatment step:
Step S302: processor receives the interrupt feed-back signal of first kind signal receiving decoding device or the input of Second Type signal receiving decoding device;
Step S304: processor differentiates the signal type of current access first kind signal receiving decoding device or Second Type signal receiving decoding device under the triggering of interrupt feed-back signal;
Step S306: processor is according to differentiating that result opens the output channel corresponding with signal type.
Adopt method as shown in Figure 3, solve the problem that the patten's design polytype signal being accessed digital hard disc video recorder mentioned in correlation technique is complicated, increase hardware cost, and then reduce complexity and the hardware cost of system.
Preferably, in step s 304, processor carries out differentiation to the signal type of current access first kind signal receiving decoding device or Second Type signal receiving decoding device and can comprise following operation under the triggering of interrupt feed-back signal:
Step S1: processor response interrupt feed-back signal, via inter-integrated circuit (I2C) bus, the lock register in first kind signal receiving decoding device and Second Type signal receiving decoding device and interrupt signal register are read, wherein, first kind signal receiving decoding device or Second Type signal receiving decoding device are when signal type is identical with own type, locking processing is carried out to this signal, and when signal type is different from own type, losing lock process is carried out to this signal;
Step S2: processor differentiates signal type according to reading result.
In a preferred embodiment, suppose when signal access be analogue camera signal access time, analogue camera signal can enter HD-TVI signal receiving decoder module and analog signal demodulating and decoding module respectively.Analog signal demodulating and decoding module locks this analogue camera signal, and this analogue camera signal of HD-TVI signal receiving decoder module losing lock.Analog signal demodulating and decoding module produces interrupt feed-back signal and is sent to DSP.DSP is after receiving this feedback signal, and what can read that the lock register of these two modules and interrupt signal register differentiate access by I2C bus is analogue camera signal.
Preferably, in step S306, processor is opened the output channel corresponding with signal type according to differentiation result and can be comprised the following steps:
Step S3: processor judges the signal receiving decoding device that the signal of current access first kind signal receiving decoding device or Second Type signal receiving decoding device belongs to;
Step S4: processor controls tri-state switch and the output channel corresponding to the another kind of type signal demodulating and decoding device except the signal receiving decoding device belonged to except signal is set to high-impedance state, opens the output channel corresponding with the signal receiving decoding device that signal belongs to simultaneously.
In a preferred embodiment, suppose when signal access be the access of analogue camera signal time, DSP can arrange the register in HD-TVI signal receiving decoder module by I2C bus and the BT656 signal output channel of HD-TVI camera is arranged to high-impedance state or maintenance and power on the high-impedance state of default setting; Meanwhile, DSP can also open the BT656 DATA signal output channel of analogue camera by the I2C bus register arranged in analog signal demodulating and decoding module, and GPIO controls the BT656 CLK signal output channel that tri-state switch opens analogue camera.Then, DSP judges this BT656 signal validity again, if effectively, this closed-circuit working is at analogue camera signal processing model.
Preferably, in step S302, processor can also comprise following operation before receiving the interrupt feed-back signal of first kind signal receiving decoding device or the input of Second Type signal receiving decoding device:
Step S5: Signal Regulation device carries out electrostatic defending process to the signal of current access;
Step S6: Signal Regulation device carries out carrying out surge protection process to the signal after electrostatic defending process;
Step S7: Signal Regulation device carries out impedance matching process to the signal after carrying out surge protection process, and the signal communication after impedance matching process is coupled to first kind signal receiving decoding device and Second Type signal receiving decoding device.
In a preferred embodiment, when signal access is when HD-TVI camera signal accesses or analogue camera signal accesses, the combination of " TSS+ current-limiting resistance " can be adopted to carry out electrostatic and surge release to this signal path after, signal produces suitable signal level through impedance matching resistor, then AC coupled enters HD-TVI signal receiving decoder module and analog signal demodulating and decoding module.
Fig. 4 is the structured flowchart of the signal with different type adaptive access system according to the embodiment of the present invention.As shown in Figure 4, this signal with different type adaptive access system can comprise: processor 1.This processor 1 can comprise: receiver module 10, for receiving the interrupt feed-back signal of first kind signal receiving decoding device or the input of Second Type signal receiving decoding device; Discrimination module 12, for differentiating the signal type of current access first kind signal receiving decoding device or Second Type signal receiving decoding device under the triggering of interrupt feed-back signal; Access module 14, for opening the output channel corresponding with signal type according to differentiation result.
Preferably, as shown in Figure 5, discrimination module 12 can comprise: reading unit 120, for responding interrupt feed-back signal, via I2C bus, the lock register in first kind signal receiving decoding device and Second Type signal receiving decoding device and interrupt signal register are read, wherein, first kind signal receiving decoding device or Second Type signal receiving decoding device are when signal type is identical with own type, locking processing is carried out to this signal, and when signal type is different from own type, losing lock process is carried out to this signal; Judgement unit 122, for differentiating signal type according to reading result.
Preferably, as shown in Figure 5, access module 14 can comprise: identifying unit 140, for judging the signal receiving decoding device that the signal of current access first kind signal receiving decoding device or Second Type signal receiving decoding device belongs to; Control unit 142, for controlling tri-state switch, the output channel corresponding to the another kind of type signal demodulating and decoding device except the signal receiving decoding device belonged to except signal being set to high-impedance state, opening the output channel corresponding with the signal receiving decoding device that signal belongs to simultaneously.
Preferably, as shown in Figure 5, said system can also comprise: Signal Regulation device 2, and this Signal Regulation device 2 can comprise: the first processing module 20, for carrying out electrostatic defending process to the signal of current access; Second processing module 22, for carrying out carrying out surge protection process to the signal after electrostatic defending process; 3rd processing module 24, for carrying out impedance matching process to the signal after carrying out surge protection process, and is coupled to first kind signal receiving decoding device and Second Type signal receiving decoding device by the signal communication after impedance matching process.
From above description, can find out, above embodiments enable following technique effect (it should be noted that these effects are effects that some preferred embodiment can reach): adopt the technical scheme that the embodiment of the present invention provides, in DVR, the mode adopting hardware and software to combine realizes HD-TVI camera signal and analogue camera signal (or other two kinds of different cameral signals) adaptive access DVR technology, the hardware connection mode of two kinds of (or two or more) camera signal identification and software treatment mechanism, and the hardware connection mode of BT656 signal (or similar parallel data grabbing card) " line with " function and software treatment mechanism.Thus, lossless signal access is adopted at camera signal incoming end.The mode adopting hardware and software to combine, can avoid filter to the decay of useful signal and time delay, make useful signal nondestructively can access DVR, can also realize the adaptive access DVR of two or more different cameral simultaneously.BT656 signal " line with " function is realized in Digital Signal Processing interface end.The realization of BT656 signal (or similar parallel data grabbing card) " line with " function, can avoid the exploitation and the maintenance that use the circuit functions such as CPLD, greatly reduce complexity and the cost of " adaptive access " system development.
Obviously, those skilled in the art should be understood that, above-mentioned of the present invention each module or each step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on network that multiple calculation element forms, alternatively, they can realize with the executable program code of calculation element, thus, they can be stored and be performed by calculation element in the storage device, and in some cases, step shown or described by can performing with the order be different from herein, or they are made into each integrated circuit modules respectively, or the multiple module in them or step are made into single integrated circuit module to realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a signal with different type adaptive access circuit, is characterized in that, comprising:
First kind signal receiving decoding device, for inputting first kind signal to processor;
Second Type signal receiving decoding device, be connected with described first kind signal receiving decoding device, for inputting Second Type signal to described processor, wherein, after described Second Type signal receiving decoding device and described first kind signal receiving decoding device interconnect, jointly described processor is accessed;
Described processor, be connected with described Second Type signal receiving decoding device with described first kind signal receiving decoding device respectively, for differentiating the signal type of current access described first kind signal receiving decoding device or described Second Type signal receiving decoding device under the triggering of the interrupt feed-back signal of described first kind signal receiving decoding device or the input of described Second Type signal receiving decoding device, and according to differentiating that result opens the output channel corresponding with described signal type.
2. circuit according to claim 1, it is characterized in that, first output of described first kind signal receiving decoding device and the second output of described Second Type signal receiving decoding device carry out line with, and be connected to described processor, wherein, described first output and described second output are all for exporting the data DATA signal of parallel data grabbing card.
3. circuit according to claim 1, it is characterized in that, 3rd output of described Second Type signal receiving decoding device carry out with the 4th output of described first kind signal receiving decoding device under the control action of tri-state switch line with, and be connected to described processor, wherein, described 3rd output and described 4th output are all for exporting the CLK signal of parallel data grabbing card.
4. circuit according to claim 1, it is characterized in that, 5th output of described first kind signal receiving decoding device and the 6th output of described Second Type signal receiving decoding device are connected to described processor respectively, wherein, described 5th output and described 6th output are all for exporting described interrupt feed-back signal.
5. circuit according to claim 1, is characterized in that, described circuit also comprises:
Signal Regulation device, be connected with described Second Type signal receiving decoding device with described first kind signal receiving decoding device respectively, for after carry out electrostatic and carrying out surge protection and impedance matching process to the signal of current access described first kind signal receiving decoding device or described Second Type signal receiving decoding device, AC coupled is to described first kind signal receiving decoding device and described Second Type signal receiving decoding device.
6. circuit according to claim 5, is characterized in that, described Signal Regulation device comprises:
Electrostatic protection device, for carrying out electrostatic defending process to the signal of described current access;
Surge suppresses thyristor, for carrying out carrying out surge protection process to the signal after electrostatic defending process;
Terminating resistor and printing board PCB walk line impedence, for carrying out impedance matching process to the signal after carrying out surge protection process.
7., based on a using method for the signal with different type adaptive access circuit according to any one of claim 1 to 6, it is characterized in that, comprising:
Processor receives the interrupt feed-back signal of first kind signal receiving decoding device or the input of Second Type signal receiving decoding device;
Described processor differentiates the signal type of current access described first kind signal receiving decoding device or described Second Type signal receiving decoding device under the triggering of described interrupt feed-back signal;
Described processor is according to differentiating that result opens the output channel corresponding with described signal type.
8. method according to claim 7, it is characterized in that, described processor carries out differentiation to the signal type of current access described first kind signal receiving decoding device or described Second Type signal receiving decoding device and comprises under the triggering of described interrupt feed-back signal:
Described processor responds described interrupt feed-back signal, via inter-integrated circuit I2C bus, the lock register in described first kind signal receiving decoding device and described Second Type signal receiving decoding device and interrupt signal register are read, wherein, described first kind signal receiving decoding device or described Second Type signal receiving decoding device are when described signal type is identical with own type, locking processing is carried out to this signal, and when described signal type is different from own type, losing lock process is carried out to this signal;
Described processor differentiates described signal type according to reading result.
9. method according to claim 7, is characterized in that, described processor is opened the output channel corresponding with described signal type according to described differentiation result and comprised:
Described processor judges the signal receiving decoding device that the signal of current access described first kind signal receiving decoding device or described Second Type signal receiving decoding device belongs to;
Described processor controls tri-state switch and the output channel corresponding to the another kind of type signal demodulating and decoding device except the signal receiving decoding device that described signal belongs to is set to high-impedance state, opens the output channel corresponding with the signal receiving decoding device that described signal belongs to simultaneously.
10. method according to claim 9, is characterized in that, before receiving the described interrupt feed-back signal of described first kind signal receiving decoding device or the input of described Second Type signal receiving decoding device, also comprises at described processor:
The signal of Signal Regulation device to described current access carries out electrostatic defending process;
Described Signal Regulation device carries out carrying out surge protection process to the signal after electrostatic defending process;
Described Signal Regulation device carries out impedance matching process to the signal after carrying out surge protection process, and the signal communication after impedance matching process is coupled to described first kind signal receiving decoding device and described Second Type signal receiving decoding device.
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