CN104298034A - Display panel - Google Patents
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- CN104298034A CN104298034A CN201410487504.0A CN201410487504A CN104298034A CN 104298034 A CN104298034 A CN 104298034A CN 201410487504 A CN201410487504 A CN 201410487504A CN 104298034 A CN104298034 A CN 104298034A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136218—Shield electrodes
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- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
Abstract
The embodiment of the invention provides a display panel and relates to the technical field of display. The problem that vertical crosstalk occurs due to the facts that a pixel electrode and a data line are formed on an array substrate of an existing display panel and produce coupling capacitance is solved. The display panel comprises a color film substrate, an array substrate, liquid crystals and an insulation pad. The color film substrate and the array substrate are opposite to each other. The liquid crystals and the insulation pad are arranged between the color film substrate and the array substrate. The insulation pad is conductive. The color film substrate comprises pixel electrodes formed on a first substrate and arranged in a matrix mode. The array substrate comprises a grid line, a data line and a thin film transistor, wherein the grid line, the data line and the thin film transistor are formed on a second substrate. The drain electrode of the thin film transistor is electrically connected with the corresponding pixel electrode through the conductive insulation pad. The display panel further comprises a first storage electrode and a second storage electrode, wherein the first storage electrode and the second storage electrode are formed on the first substrate and/or the second substrate, are insulated from each other, and have an overlapping area. The display panel is used for a display device comprising the display panel.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of display panel.
Background technology
TN (Twisted Nematic, twisted nematic) type display panel is the one of display panel, due to low production cost, is widely used in the low and middle-end liquid crystal display of current main flow.
As depicted in figs. 1 and 2, traditional TN type display panel comprises color membrane substrates 1, array base palte 2 and the liquid crystal between color membrane substrates 1 and array base palte 23.Wherein, color membrane substrates 1 comprises public electrode 4, array base palte 2 comprises and intersects limited pixel region by grid line 5 and data line 6, each pixel region comprises thin film transistor (TFT) 8 and pixel electrode 7.
The displaying principle of TN type display panel: thin film transistor (TFT) response is from the gate signal of grid line, and the data-signal of data line is applied to pixel electrode, there is provided voltage to public electrode simultaneously, like this, public electrode on color membrane substrates and the pixel electrode on array base palte form electric field, and because the voltage of pixel electrode is different, the liquid crystal anglec of rotation that each pixel region is corresponding is different, then light transmission is different, realizes the display of different grey-scale thus.
As shown in Figure 2, state in realization in the process of display, when grid line 5 inputs gate signal to the thin film transistor (TFT) 8 of respective pixel electrode 71, data line 6 inputs the first data-signal to the thin film transistor (TFT) 8 of respective pixel electrode 71, then first pixel electrode 71 correspondence input the first voltage.Grid line 5 carries out along direction of scanning 100 thin film transistor (TFT) 8 scanned to respective pixel electrode 72 and inputs gate signal, and data line 6 inputs the second data-signal to the thin film transistor (TFT) 8 of respective pixel electrode 72, then second pixel electrode 72 correspondence input the second voltage.Because the first data-signal is different with the second data-signal, then the first voltage of the first pixel electrode 71 correspondence input is different with the second voltage of the second pixel electrode 72 correspondence input.When data line 6 inputs the second voltage to the second pixel electrode 72, data line 6 is coupled with the first pixel electrode 71 and produces coupling capacitance, this coupling capacitance can affect the first voltage of the first pixel electrode 71 input originally, makes to occur crosstalk along grid line direction of scanning 100.
Summary of the invention
Embodiments of the invention provide a kind of display panel, and improve existing display panel owing to array base palte being formed with pixel electrode and data line, pixel electrode and data line produce coupling capacitance thus occur vertical crosstalk, affect the problem of display quality.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, provide a kind of display panel, comprising: to color membrane substrates and the array base palte of box, and liquid crystal between described color membrane substrates and described array base palte and chock insulator matter, described chock insulator matter is conductive spacer; Described color membrane substrates comprises: the first substrate and be formed in the pixel electrode of the arrangement of matrix on described first substrate; Described array base palte comprises: the second substrate and the grid line, data line and the thin film transistor (TFT) that are formed on described second substrate; Wherein, the grid of described thin film transistor (TFT) is electrically connected with described grid line, and source electrode is electrically connected with described data line, drains to be electrically connected with corresponding described pixel electrode by described conductive spacer; Also comprise and be formed in the first storage electrode on described first substrate and/or described second substrate and the second storage electrode, described first storage electrode and described second storage electrode mutually insulated and there is overlapping region.
Embodiments provide a kind of display panel, described display panel by arranging pixel electrode on color membrane substrates, and pixel electrode is electrically connected with the drain electrode of thin film transistor (TFT) by the conductive spacer on array base palte, thus drain electrode is charged to pixel electrode; The first storage electrode on color membrane substrates and/or array base palte and the second storage electrode form memory capacitance, uninterrupted to ensure the display of two continuous frames image; Pixel electrode is positioned at color membrane substrates again, data line bit is in array base palte, liquid crystal is filled with between color membrane substrates and array base palte, then to be at least greater than the box of liquid crystal thick for the spacing distance of the pixel electrode on color membrane substrates and the data line on array base palte, namely the spacing distance of data line and pixel electrode is increased relative to prior art, coupling capacitance between such pixel electrode and data line reduces greatly, and then improve the vertical cross talk problems of display panel, thus improve the display quality of display panel.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
A kind of TN type display panel structure schematic diagram of Fig. 1 for providing in prior art;
Fig. 2 is the enlarged diagram of local A in Fig. 1;
A kind of display panel structure schematic diagram that Fig. 3 provides for the embodiment of the present invention;
Fig. 4 is the color membrane substrates plan structure schematic diagram shown in Fig. 3;
Fig. 5 is the simple and easy enlarged diagram of local B in Fig. 3;
Fig. 6 is that the C-C ' of Fig. 5 is to cut-open view;
Fig. 7 is the concrete enlarged diagram of local B in Fig. 3;
A kind of schematic diagram forming grid line, grid, public electrode wire and the second storage electrode on the second substrate that Fig. 8 provides for the embodiment of the present invention;
A kind of schematic diagram forming data line, source electrode and drain electrode on the second substrate that Fig. 9 provides for the embodiment of the present invention;
A kind of second substrate that Figure 10 provides for the embodiment of the present invention is formed with the schematic diagram of public electrode via hole, the second storage electrode via hole, drain via;
A kind of schematic diagram forming public electrode and the first storage electrode on the second substrate that Figure 11 provides for the embodiment of the present invention.
Reference numeral:
100-direction of scanning; 1-color membrane substrates; 101-first substrate; 2-array base palte; 201-second substrate; 3-liquid crystal; 4-public electrode; 5-grid line; 6-data line; 7-pixel electrode; 71-first pixel electrode; 72-second pixel electrode; 8-thin film transistor (TFT); 801-grid; 802-source electrode; 803-drains; 9-conductive spacer; 10-first storage electrode; 11-second storage electrode; 12-public electrode wire; 13-public electrode via hole; 14-second storage electrode via hole; 15-drain via; 16-overlapping region.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
It should be noted that, in the embodiment of the present invention, described " on ", D score with the order of the film or Rotating fields that form substrate for foundation, at the film of rear formation or Rotating fields namely upper, the film formerly formed or Rotating fields namely under.
Thin film transistor (TFT) generally comprises grid, source electrode and drain electrode, according to the position relationship of grid in thin film transistor (TFT) and source-drain electrode, can be divided into the thin film transistor (TFT) of top gate structure and the thin film transistor (TFT) of bottom grating structure.Wherein, the thin film transistor (TFT) of top gate structure and grid are positioned at above source-drain electrode; Thin film transistor (TFT) and the grid of bottom grating structure are positioned at below source-drain electrode.Thin film transistor (TFT) in the embodiment of the present invention can be the thin film transistor (TFT) of top gate structure, also can be the thin film transistor (TFT) of bottom grating structure.
Embodiments provide a kind of display panel, as shown in Figure 3, comprising: to color membrane substrates 1 and the array base palte 2 of box, also comprise the liquid crystal 3 between color membrane substrates 1 and array base palte 2 and conductive spacer 9; As shown in Figure 4, color membrane substrates 1 comprises: the first substrate 101 and be formed in the pixel electrode 7 of the arrangement of matrix on the first substrate 101.
As shown in Fig. 3, Fig. 5, array base palte 2 comprises: the second substrate 201 and the grid line 5, data line 6 and the thin film transistor (TFT) 8 that are formed on the second substrate 201; Wherein, the grid of thin film transistor (TFT) 8 is electrically connected with grid line 5, and source electrode is electrically connected with data line 6, drains to be electrically connected with corresponding pixel electrode 7 by conductive spacer 9.
Color membrane substrates and/or array base palte also comprise and are formed in the first storage electrode on the first substrate and/or the second substrate and the second storage electrode, first storage electrode and the second storage electrode mutually insulated and there is overlapping region, for forming memory capacitance at overlapping region.
It should be noted that, array base palte comprises grid line and data line, and grid line and data line intersect to form multiple pixel region, and pixel region matrix arranges, and each pixel region comprises thin film transistor (TFT).Color membrane substrates comprises the pixel electrode of matrix arrangement, and the pixel electrode on color membrane substrates and the pixel region one_to_one corresponding on array base palte, be electrically connected with the drain electrode of the thin film transistor (TFT) of corresponding pixel region by conductive spacer.
Above-mentioned color membrane substrates and/or array base palte also comprise and are formed in the first storage electrode on the first substrate and/or the second substrate and the second storage electrode, namely can be that color membrane substrates also comprises formation the first storage electrode on the first substrate and the second storage electrode; Or array base palte also comprises and is formed in the first storage electrode on the second substrate and the second storage electrode; Or color membrane substrates can also comprise formation the first storage electrode on the first substrate, array base palte also comprises the second storage electrode be formed on the second substrate simultaneously; Or color membrane substrates can also comprise formation the second storage electrode on the first substrate, array base palte also comprises the first storage electrode be formed on the second substrate simultaneously.The embodiment of the present invention and accompanying drawing also comprise for array base palte and are formed in the first storage electrode on the second substrate and the second storage electrode is described in detail.
As shown in Figure 7, the first storage electrode 10 is positioned at above the second storage electrode 11, and the first storage electrode 10 and the second storage electrode 11 form overlapping region 16, and the first storage electrode 10 and the second storage electrode 11 form memory capacitance at overlapping region 16.First storage electrode and the second storage electrode form memory capacitance, and memory capacitance makes the voltage of pixel electrode to remain to upgrade picture next time, though current frame image remain to next frame more new images, uninterrupted to ensure the display of two continuous frames image.
A kind of display panel that the embodiment of the present invention provides, color membrane substrates arranges pixel electrode, and pixel electrode is electrically connected with the drain electrode of thin film transistor (TFT) by the conductive spacer on array base palte, and drain electrode is charged to pixel electrode like this; First storage electrode and the second storage electrode form memory capacitance, uninterrupted to ensure the display of two continuous frames image; Pixel electrode is positioned at color membrane substrates again, data line bit is in array base palte, liquid crystal is filled with between color membrane substrates and array base palte, then the spacing distance of the pixel electrode on color membrane substrates and the data line on array base palte increases (box being at least greater than liquid crystal is thick), namely the spacing distance of data line and pixel electrode is increased relative to prior art, coupling capacitance between such pixel electrode and data line reduces greatly, and then improve the vertical cross talk problems of display panel, thus improve the display quality of display panel.
Optionally, color membrane substrates also comprises formation public electrode on the first substrate; When public electrode and pixel electrode are positioned at different layers, at least away from the first substrate in public electrode and pixel electrode is gap electrode; Or when pixel electrode and public electrode are positioned at same layer, pixel electrode and public electrode are gap electrode.
When above-mentioned public electrode and pixel electrode are positioned at different layers, at least away from the first substrate in public electrode and pixel electrode is gap electrode.Namely can be positioned at above public electrode by pixel electrode, then pixel electrode be away from the first substrate, and now, pixel electrode is gap electrode, and public electrode can be gap electrode also can be plate electrode.Can also be positioned at above pixel electrode by public electrode, then public electrode be away from the first substrate, and now public electrode is gap electrode, and pixel electrode can be gap electrode also can be plate electrode.And preferred, when public electrode and pixel electrode are positioned at different layers, pixel electrode and public electrode are gap electrode.
It should be noted that, when color membrane substrates also comprises public electrode, namely pixel electrode and public electrode are all arranged on color membrane substrates.For pixel electrode be positioned at public electrode above, because color membrane substrates and array base palte are to after box, pixel electrode is away from the first substrate, namely pixel electrode is near liquid crystal, then in order to form the multi-dimensional electric field driving liquid crystal between pixel electrode and public electrode, pixel electrode is necessary for gap electrode.Public electrode is positioned at situation above pixel electrode with principle is identical above.Public electrode and pixel electrode form multi-dimensional electric field on same substrate, and display panel has the features such as visible angle is high, fast response time.
In addition, color membrane substrates also comprises formation public electrode on the first substrate, can be that color membrane substrates comprises pixel electrode and public electrode; Or, can also be that color membrane substrates comprises pixel electrode, the first storage electrode, the second storage electrode and public electrode; Or, can also be that color membrane substrates comprises pixel electrode, the first storage electrode (or second storage electrode) and public electrode.
Optionally, array base palte also comprises the public electrode be formed on the second substrate, color membrane substrates comprises formation pixel electrode on the first substrate, vertical electric field is formed between pixel electrode and public electrode, then the display panel of corresponding formation is TN (Twisted Nematic, twisted nematic) type display panel etc., this panel has the features such as cost is low.
In addition, array base palte also comprises the public electrode be formed on the second substrate, can be that array base palte comprises public electrode; Can also be that array base palte comprises the first storage electrode, the second storage electrode and public electrode; Or, can also be that color membrane substrates comprises the second storage electrode (or first storage electrode) and public electrode.In the embodiment of the present invention, comprise pixel electrode with color membrane substrates, it is that example is described in detail that array base palte comprises the first storage electrode, the second storage electrode and public electrode.
Optionally, as shown in Figure 7, array base palte also comprises and is formed in the second storage electrode 11, second storage electrode 11 on the second substrate 201 and grid line 5 can be formed by a patterning processes.One time patterning processes comprises the techniques such as mask, exposure, development, etching and stripping, and the second storage electrode and grid line are formed by a patterning processes, decrease the number of times of patterning processes, thus reduce manufacturing cost.
Optionally, when the first storage electrode and public electrode are positioned on color membrane substrates or array base palte simultaneously, first storage electrode and public electrode can be formed by a patterning processes, can reduce the number of times of patterning processes like this, thus reduce manufacturing cost.As shown in Figure 7, be positioned on array base palte for the first storage electrode 10 and public electrode 4, then the first storage electrode 10 and public electrode 4 can be formed by a patterning processes simultaneously.
Optionally, as shown in Figure 7, array base palte also comprises the public electrode wire 12 be electrically connected with public electrode 4, and public electrode wire 12 and grid line 5 can be formed by a patterning processes, can reduce the number of times of patterning processes like this, thus reduce manufacturing cost.
It should be noted that, the framework that the first storage electrode and the second storage electrode form memory capacitance has various ways.First storage electrode and the second storage electrode respectively by pixel electrode and grid line charging, can form memory capacitance; Can also be respectively by pixel electrode and public electrode wire charging, form memory capacitance.
Concrete, in the embodiment of the present invention, because pixel electrode is electrically connected with drain electrode, then charge, when forming memory capacitance respectively by pixel electrode and grid line at the first storage electrode and the second storage electrode.First storage electrode can be and the electrical connection that drains, by drain electrode to the first storage electrode charging, second storage electrode can be and grid line electrical connection, be charged, form memory capacitance like this at the first storage electrode and the second storage electrode at overlapping region by grid line to the second storage electrode.Or, first storage electrode can be and grid line electrical connection, and charged to the first storage electrode by grid line, the second storage electrode can be and the electrical connection that drains, by drain electrode to the second storage electrode charging, form memory capacitance at the first storage electrode and the second storage electrode at overlapping region like this.
Charge, when forming memory capacitance respectively by pixel electrode and public electrode wire at the first storage electrode and the second storage electrode.First storage electrode can be and the electrical connection that drains, by drain electrode to the first storage electrode charging, second storage electrode can be electrically connected with public electrode wire, by the charging of public electrode alignment second storage electrode, form memory capacitance at the overlapping region of the first storage electrode and the second storage electrode like this.Or, first storage electrode can be electrically connected with public electrode wire, charged by public electrode alignment first storage electrode, second storage electrode can be and the electrical connection that drains, by drain electrode to the second storage electrode charging, form memory capacitance at the overlapping region of the first storage electrode and the second storage electrode like this.
, be arranged on color membrane substrates with pixel electrode below, it is example that public electrode, the first storage electrode, the second storage electrode are all arranged on array base palte, provides a kind of display panel that a specific embodiment provides to describe the embodiment of the present invention in detail.
As shown in Figure 6, this display panel comprises: to color membrane substrates 1 and the array base palte 2 of box, also comprise the liquid crystal 3 between color membrane substrates 1 and array base palte 2 and conductive spacer 9; The pixel electrode 7 that color membrane substrates 1 comprises the first substrate 101 and is formed on the first substrate 101.Color membrane substrates also comprises: be positioned at the first substrate and the flatness layer (not shown) of covering pixel electrode 7, flatness layer is provided with pixel electrode via hole in the position of correspondence drain electrode 803, and conductive spacer 9 is electrically connected with pixel electrode 7 by pixel electrode via hole.
As shown in Figure 6, Figure 7, array base palte 2 comprises: the second substrate 201 and the grid line 5, data line 6 and the thin film transistor (TFT) that are formed on the second substrate 201; Wherein, array base palte also comprises and is formed in the second substrate and covers the second storage electrode and the gate insulation layer (not shown) of grid line and the passivation layer (not shown) of cover film transistor.The grid 801 of thin film transistor (TFT) is electrically connected with grid line 5, and source electrode 802 is electrically connected with data line 6, and passivation layer is provided with drain via 15 in the position of correspondence drain electrode 803, and conductive spacer 9 is electrically connected with drain electrode 803 by drain via 15.
As shown in Figure 7, array base palte also comprises the first storage electrode 10, second storage electrode 11, public electrode 4, the public electrode wire 12 that are formed on the second substrate 201.Gate insulation layer is provided with the second storage electrode via hole 14 in the position of corresponding second storage electrode 11, public electrode 4 be formed in gate insulation layer above and be electrically connected with the second storage electrode 11 by the second storage electrode via hole 14; Passivation layer is provided with drain via 15 in the position of correspondence drain electrode 803, the first storage electrode 10 be formed in passivation layer above and 803 to be electrically connected with draining by drain via 15.
First storage electrode 10 is by drain via 15 and drain electrode 803; Second storage electrode 11 is electrically connected by the second storage electrode via hole 14 with public electrode 4, and public electrode 4 and public electrode wire 12 are electrically connected by public electrode via hole 13, thus the second storage electrode 11 is electrically connected with public electrode wire 12.Like this, first storage electrode 10 is charged by drain electrode 803, and the second storage electrode 11 is charged by public electrode wire 12, and the first storage electrode 10 and the second storage electrode 11 form memory capacitance at overlapping region 16, thus can voltage be preserved, use time in order to upgrading picture.
Based on a kind of display panel that the embodiment of the present invention provides, pixel electrode is arranged on color membrane substrates, be electrically connected with drain electrode by conductive spacer, thus drain electrode is charged to pixel electrode, public electrode is arranged on array base palte, and public electrode is electrically connected with public electrode wire, is charged by public electrode alignment public electrode, to make pixel electrode and public electrode form electric field, liquid crystal is driven to realize display; First storage electrode is by drain charge, and the second storage electrode is charged by public electrode wire, and then forms memory capacitance at the overlapping region of the first storage electrode and the second storage electrode, uninterrupted to ensure the display of two continuous frames image; Pixel electrode is positioned at color membrane substrates again, data line bit is in array base palte, liquid crystal is filled with between color membrane substrates and array base palte, then the interval of the pixel electrode on color membrane substrates and the data line on array base palte increases (box that distance is at least greater than liquid crystal is thick), namely the spacing distance of data line and pixel electrode is increased relative to prior art, coupling capacitance between such pixel electrode and data line reduces greatly, and then improve the vertical cross talk problems of display panel, thus improve the display quality of display panel.
Below, enumerate a specific embodiment in order to the method for making of display panel to be as shown in Figure 6 described, described method comprises:
The flatness layer of step S011, the pixel electrode forming matrix arrangement on the first substrate and covering pixel electrode, flatness layer is provided with pixel electrode via hole in the position of respective pixel electrode.Namely the color membrane substrates formed comprises pixel electrode.
Step S021, as shown in Figure 8, on the second substrate 201, form grid metal level by a patterning processes, wherein, grid metal level comprises: grid line 5, grid 801, public electrode wire 12 and the second storage electrode 11.
Step S022, on the second substrate, form the gate insulation layer of covering gate metal level, wherein, gate insulation layer is formed with the second storage electrode via hole in the position of corresponding second storage electrode, and is formed with public electrode via hole in the position of corresponding public electrode wire.
Step S023, as shown in Figure 9, the second substrate 201 forms source and drain metal level, wherein, source and drain metal level comprises data line 6, source electrode 802 and drain electrode 803.Source electrode 802 is electrically connected with data line 6.
Step S024, on the second substrate, form passivation layer, the position that passivation layer drains in correspondence is provided with drain via.
Above-mentioned steps S021-S024 can form array base palte as shown in Figure 10, gate insulation layer (not shown) is formed with the second storage electrode via hole 14 in the position of corresponding second storage electrode 11, and is formed with public electrode via hole 13 in the position of corresponding public electrode wire 12.Passivation layer (not shown) is provided with drain via 15 in the position of correspondence drain electrode 803.
Step S025, as shown in figure 11, forms public electrode 4 and the first storage electrode 10 by a patterning processes.Concrete, public electrode 4 is formed in the region of grid line 5 and the restriction of data line 6 intersection, is electrically connected with public electrode wire 12 by public electrode via hole 13.Second storage electrode 11 is electrically connected with public electrode 4 by the second storage electrode via hole 14.The top that first storage electrode 10 is formed in drain electrode 803 is formed, and is electrically connected with drain electrode 803 by drain via 15.
Step S026, as shown in Figure 7, forms conductive spacer 9 in the position of the second substrate correspondence drain electrode.Wherein, conductive spacer 9 is electrically connected with drain electrode 803 by drain via 15.
Step S027, as shown in Figure 6, between color membrane substrates 1 and array base palte 2, form liquid crystal 3, utilize box technique, by color membrane substrates 1 and array base palte 2 pairs of boxes.Now, the conductive spacer on array base palte is electrically connected with pixel electrode by the pixel electrode via hole of flatness layer on color membrane substrates.
As shown in Figure 7, its display panel become box-like with color membrane substrates as shown in Figure 6 for the array base palte that can be formed through above-mentioned steps S021-step S026.
It should be noted that, the method for making forming display panel as shown in Figure 6 is also not limited to above-mentioned concrete steps, and such as, it is first-class that conductive spacer can also be formed in color membrane substrates.The embodiment of the present invention only illustrates the method for making of the display panel that the embodiment of the present invention provides for above-mentioned concrete steps.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (10)
1. a display panel, comprising: to color membrane substrates and the array base palte of box, and liquid crystal between described color membrane substrates and described array base palte and chock insulator matter, and it is characterized in that, described chock insulator matter is conductive spacer;
Described color membrane substrates comprises: the first substrate and be formed in the pixel electrode of the arrangement of matrix on described first substrate;
Described array base palte comprises: the second substrate and the grid line, data line and the thin film transistor (TFT) that are formed on described second substrate; Wherein, the grid of described thin film transistor (TFT) is electrically connected with described grid line, and source electrode is electrically connected with described data line, drains to be electrically connected with corresponding described pixel electrode by described conductive spacer;
Also comprise and be formed in the first storage electrode on described first substrate and/or described second substrate and the second storage electrode, described first storage electrode and described second storage electrode mutually insulated and there is overlapping region.
2. display panel according to claim 1, is characterized in that, described color membrane substrates also comprises the public electrode be formed on described first substrate;
When described public electrode and described pixel electrode are positioned at different layers, at least away from the first substrate in described public electrode and described pixel electrode is gap electrode; Or,
When described pixel electrode and described public electrode are positioned at same layer, described pixel electrode and described public electrode are gap electrode.
3. display panel according to claim 2, is characterized in that, when described public electrode and described pixel electrode are positioned at different layers, described pixel electrode and described public electrode are gap electrode.
4. display panel according to claim 1, is characterized in that, described array base palte also comprises the public electrode be formed on described second substrate.
5. display panel according to claim 1, is characterized in that, described second storage electrode is formed on described second substrate, and described second storage electrode and described grid line are formed by a patterning processes.
6. display panel according to claim 4, is characterized in that, described first storage electrode is formed on described second substrate, and described first storage electrode and described public electrode are formed by a patterning processes.
7. display panel according to claim 4, is characterized in that, described array base palte also comprises the public electrode wire be electrically connected with described public electrode, and described public electrode wire and described grid line are formed by a patterning processes.
8. the display panel according to any one of claim 1-7, is characterized in that, described first storage electrode is electrically connected with described drain electrode, and described second storage electrode is electrically connected with described public electrode.
9. display panel according to claim 8, it is characterized in that, described second storage electrode is formed on described second substrate, and formed by a patterning processes with described grid line, described array base palte also comprises and is formed in described second substrate and the gate insulation layer covering described second storage electrode and described grid line, described gate insulation layer is provided with the second storage electrode via hole in the position of described second storage electrode of correspondence, described public electrode be formed in described gate insulation layer above and be electrically connected with described second storage electrode by described second storage electrode via hole;
Described first storage electrode is formed on described second substrate, and formed by a patterning processes with described public electrode, described array base palte also comprises and is formed in described second substrate and the passivation layer covering described thin film transistor (TFT), the position that described passivation layer drains in correspondence is provided with drain via, described first storage electrode be formed in described passivation layer above and be electrically connected with described drain electrode by described drain via.
10. display panel according to claim 1, it is characterized in that, described array base palte also comprises: be formed in described second substrate and cover the passivation layer of described thin film transistor (TFT), the position that described passivation layer drains in correspondence is provided with drain via, and described conductive spacer is electrically connected with described drain electrode by described drain via;
Described color membrane substrates also comprises: be positioned at described first substrate and cover the flatness layer of described pixel electrode, described flatness layer is provided with pixel electrode via hole in the position that correspondence drains, and described conductive spacer is electrically connected with described pixel electrode by described pixel electrode via hole.
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