CN104282571B - Fin FET and manufacture method thereof - Google Patents
Fin FET and manufacture method thereof Download PDFInfo
- Publication number
- CN104282571B CN104282571B CN201310286545.9A CN201310286545A CN104282571B CN 104282571 B CN104282571 B CN 104282571B CN 201310286545 A CN201310286545 A CN 201310286545A CN 104282571 B CN104282571 B CN 104282571B
- Authority
- CN
- China
- Prior art keywords
- fin
- dielectric layer
- gate
- side wall
- room
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000002210 silicon-based material Substances 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000001953 recrystallisation Methods 0.000 claims description 7
- 229910004143 HfON Inorganic materials 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 89
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000005530 etching Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- 239000007769 metal material Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910004491 TaAlN Inorganic materials 0.000 description 3
- 229910010037 TiAlN Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910004200 TaSiN Inorganic materials 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000005297 pyrex Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004821 distillation Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
That the present invention provides a kind of fin FET and manufacture method, the method includes: provide Semiconductor substrate；Forming gate stack on a semiconductor substrate, described gate stack includes dielectric layer and gate material layers under grid successively；Side wall is formed in described gate stack both sides；Form the fin room running through gate material layers and side wall；Gate dielectric layer is formed in fin room；Formed and be positioned at the fin structure in fin room and be positioned at the source-drain area of fin structure both sides.The present invention can simply and efficiently be formed for isolated gate stacking and the high-quality side wall of source/drain region, is effectively improved device production yield.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of fin FET and manufacture method thereof.
Background technology
Along with MOSFET (MOS memory) channel length constantly shortens, a series of at the long ditch of MOSFET
In road model, negligible effect becomes more notable, even becomes the leading factor affecting performance, and this phenomenon is referred to as
Short-channel effect.Short-channel effect causes the electric property of device to deteriorate, as cause threshold voltage of the grid decline, power consumption increase with
And degradation problem under signal to noise ratio.
At present, a kind of thinking is to improve traditional planar device technology, tries every possible means to reduce the thickness of channel region, eliminates ditch
Neutral line bottom depletion layer in road, allows the depletion layer in raceway groove can fill up whole channel region, the most so-called complete depletion type
(Fully Depleted, FD) device.
But, complete depletion type device to be produced, it is desirable to the silicon layer thickness at raceway groove is very thin.Traditional manufacturing process, special
It not that tradition manufacturing process based on body silicon is difficult to produce satisfactory structure or involve great expense, even if to emerging SOI (absolutely
Silicon on edge body) for technique, the thickness of raceway groove silicon layer also is difficult to control the level relatively thin.Around how realizing complete depletion type device
The general idea of part, the center of gravity of research and development turns to solid type device architecture, i.e. turn to complete depletion type double grid or three gate techniques.
Solid type fin FET is expected to apply 22nm technology node and following, along with device size is further
Reducing, in device, the isolation between source/drain region and grid just becomes extremely important.Accordingly, it would be desirable to being used for of easily making isolates
Source/drain region and the side wall of grid.
Summary of the invention
In order to solve the problems referred to above, the invention provides a kind of fin FET and forming method thereof, use embedding
Enter formula technique and form fin FET, simply form the high-quality side wall for isolating source/drain region and grid, have
Effect improves the production yield of fin FET.
According to an aspect of the present invention, it is provided that the manufacture method of a kind of fin FET, including:
A) Semiconductor substrate is provided；
B) forming gate stack on a semiconductor substrate, described gate stack includes dielectric layer and grid material under grid successively
Layer；
C) side wall is formed in described gate stack both sides；
D) formation runs through the fin room of gate material layers and side wall；
E) in fin room, gate dielectric layer is formed；
F) formation is positioned at the fin structure in fin room and is positioned at the source-drain area of fin structure both sides.
According to another aspect of the present invention, it is provided that fin FET, including:
Substrate；
Gate stack, is positioned at substrate, and described gate stack includes dielectric layer and gate material layers under grid；
Side wall, is positioned at gate stack both sides；
Fin structure, runs through gate material layers and side wall, has gate dielectric layer between fin structure and gate material layers；
Source-drain area, is positioned at the both sides of fin structure.
The manufacture method of the fin FET that the present invention provides and structure thereof, by using embedded methods to be formed
Multi-grid structure, in the fin FET of formation, side wall can be effectively isolated grid and source/drain region, and this side
Wall is formed simply, and quality is high.The production that the method using the present invention can be effectively improved multiple-grid (fin-shaped or three grid) device is good
Rate.
Accompanying drawing explanation
By the detailed description that non-limiting example is made made with reference to the following drawings of reading, other of the present invention
Feature, purpose and advantage will become more apparent upon:
Fig. 1 is a detailed description of the invention of the manufacture method of the fin FET according to the embodiment of the present invention
Schematic flow sheet；
Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 and Fig. 8 are respectively fin FET according to embodiments of the present invention
The schematic top plan view of each step of manufacture method；
Fig. 2 (a), Fig. 3 (a), Fig. 4 (a), Fig. 5 (a), Fig. 6 (a), Fig. 7 (a) and Fig. 8 (a) are respectively along Fig. 2, Fig. 3, Fig. 4, figure
5, the generalized section of AA ' in Fig. 6, Fig. 7 and Fig. 8；
Fig. 4 (b), Fig. 5 (b), Fig. 6 (b), Fig. 7 (b) and Fig. 8 (b) BB ' along Fig. 4, Fig. 5, Fig. 6, Fig. 7 and Fig. 8 respectively
Generalized section；
Fig. 4 (c), Fig. 5 (c), Fig. 6 (c), Fig. 7 (c) and Fig. 8 (c) CC ' along Fig. 4, Fig. 5, Fig. 6, Fig. 7 and Fig. 8 respectively
Generalized section；
In accompanying drawing, same or analogous reference represents same or analogous parts.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with the accompanying drawing enforcement to the present invention
Example is described in detail.
Embodiments of the invention are described below in detail, and the example of described embodiment is shown in the drawings, the most from start to finish
Same or similar label represents same or similar element or has the element of same or like function.Below with reference to attached
The embodiment that figure describes is exemplary, is only used for explaining the present invention, and is not construed as limiting the claims.
Following disclosure provides many different embodiments or example for realizing the different structure of the present invention.For letter
Changing disclosure of the invention, hereinafter parts and setting to specific examples are described.Certainly, they are the most merely illustrative, and
It is not intended to limit the present invention.Additionally, the present invention can in different examples repeat reference numerals and/or letter.This heavy
It is for purposes of simplicity and clarity again, the relation between itself not indicating discussed various embodiment and/or arranging.This
Outward, the various specific technique that the invention provides and the example of material, but those of ordinary skill in the art it can be appreciated that
The property of can be applicable to of other techniques and/or the use of other materials.It addition, fisrt feature described below second feature it
On " " structure can include that the first and second features are formed as the embodiment directly contacted, it is also possible to include other feature shape
Becoming the embodiment between the first and second features, such first and second features are not likely to be directly contact.It should be noted that,
Parts illustrated in accompanying drawing are not drawn necessarily to scale.Present invention omits and known assemblies and treatment technology and process are retouched
State to avoid being unnecessarily limiting the present invention.
Manufacture method below in conjunction with the fin FET of embodiment of the present invention offer is carried out further
Illustrate.
It it is a detailed description of the invention of the manufacture method of the fin FET according to the present invention with reference to Fig. 1, Fig. 1
Flow chart, the method includes:
Step S101, it is provided that Semiconductor substrate 100；
Step S102, forms gate stack on a semiconductor substrate 100, and described gate stack includes dielectric layer under grid successively
200 and gate material layers 300；
Step S103, forms side wall 310 in described gate stack both sides；
Step S104, forms the fin room running through gate material layers and side wall；
Step S105, forms gate dielectric layer 400 in fin room；
Step S106, is formed and is positioned at the fin structure in fin room and is positioned at the source-drain area of fin structure both sides.
Below in conjunction with Fig. 2 to Fig. 8 (c), step S101 is explained to step S106.Fig. 2 to Fig. 8 (c) is according to this
Bright detailed description of the invention is according to this fin FET during the flow manufacturing fin FET shown in Fig. 1
The schematic diagram of each fabrication stage.It should be noted that the accompanying drawing of each embodiment of the present invention merely to signal purpose, because of
This is not necessarily to scale.
With reference to Fig. 2 and Fig. 2 (a), perform step S101, it is provided that Semiconductor substrate 100.Substrate 100 such as includes silicon substrate
(such as silicon wafer).Requiring (such as P type substrate or N-type substrate) according to design known in the art, substrate 100 can wrap
Include various doping configuration.In other embodiments, substrate 100 can also include other basic quasiconductors, such as germanium.Or, substrate
100 can include compound semiconductor, such as carborundum, GaAs, indium arsenide or indium phosphide.Typically, substrate 100 is permissible
Have but be not limited to the thickness of the most hundreds of micron, such as can be in the thickness range of 400 μm～800 μm, such as: 400 μm,
650 μm or 800 μm.
Then performing step S102, form gate stack on a semiconductor substrate 100, described gate stack includes grid successively
Lower dielectric layer 200 and gate material layers 300.First in whole Semiconductor substrate 100, form dielectric layer 200 under grid, described grid
Lower dielectric layer 200 can be thermal oxide layer, including silicon oxide or silicon oxynitride；It is alternatively high K medium, such as: HfAlON,
One in HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON or a combination thereof.Medium under grid
The thickness of layer 200 can be such as 1nm～10nm, such as 1nm, 5nm or 10nm.Under grid, dielectric layer 200 can also be that other are thick
Degree.Thermal oxide, the chemical gaseous phase deposition technique such as (CVD), ald (ALD) can be used to form dielectric layer 200 under grid.
Afterwards, under grid, gate material layers 300 on dielectric layer 200, is formed.Gate material layers 300 can be metal material system
Become, preferably polysilicon.Metal material include but not limited to TaN, TaC, TiN, TaAlN, TiAlN, MoAlN, TaTbN,
TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTaxIn one or its combination in any.Its thickness range such as may be used
Think 10nm～80nm, such as 30nm, 50nm or 80nm.Optionally, dielectric layer under at grid is being formed before gate material layers 300
Workfunction layers (not shown) is formed on 200.The material of workfunction layers includes but not limited to TiN, TiAlN, TaN
Or the one in TaAlN or its combination in any.Its thickness range is 3nm～15nm, such as 3nm, 10nm or 15nm.
Afterwards, gate material layers 300 is formed mask layer (not shown), and is patterned.The material of mask layer
Material can be photoresist, organic polymer, silicon oxide, silicon nitride, Pyrex, boron-phosphorosilicate glass and combinations thereof.Described mask
When layer is photoresist, can be formed on described metal material layer 300 by the method for spin coating, glue spraying, and by exposure, development
It is patterned.When described mask layer is organic polymer, described metal material can be formed at by the method for spin coating, distillation
On layer 300；And when described mask layer is silicon oxide, silicon nitride, Pyrex, boron-phosphorosilicate glass, chemical gaseous phase can be passed through
The suitably method such as deposit, sputtering is formed on described metal material layer 300, and then, redeposited photoresist, as mask, passes through
Dry etching or wet etching are patterned.After Patterned masking layer, according to figure to gate material layers 300 He under it
Under grid, dielectric layer 200 performs etching, and forms gate stack.As it is shown on figure 3, gate stack can be on a semiconductor substrate 100
The shape of a plurality of straight line extended.
Perform step S103, form side wall 310 in described gate stack both sides.Side wall 310 is used for separating gate stack,
As shown in Fig. 3 and Fig. 3 (a).Side wall 310 can by silicon nitride, silicon oxide, silicon oxynitride, carborundum and combinations thereof, and/or its
He is formed by suitable material.Side wall 310 can have multiple structure.Side wall 310 can by including that deposition-etch technique is formed,
Its thickness range can be 10nm～100nm, such as 10nm, 50nm or 100nm.
Perform step S104, form the fin room running through gate material layers 300 and side wall 310.In the application, fin room refers to
Be the position that will form fin structure in subsequent technique, such as in the gate stack of the extension cut off by etching formed sky
Position.Such as, whole semiconductor structure is formed mask layer (not shown), is patterned afterwards.The formation of mask layer
And patterned process is referred to the narration of front portion of this specification, repeat no more.After Tu Xinghua, according to figure
Gate material layers 300 and side wall 310 are performed etching, to form fin room, as shown in Fig. 4, Fig. 4 (a)～Fig. 4 (c).Etching work
Skill can include wet etching or dry etching.Wet-etching technique include use hydrogen-oxygen comprise solution (such as ammonium hydroxide), deionized water or
Other suitable etchant solution；Dry carving technology includes plasma etching, ion beam milling, reverse sputtering, reactive ion etching etc..
Perform step S105, with reference to Fig. 5, Fig. 5 (a)～Fig. 5 (c), fin room forms gate dielectric layer 400.Grid
Dielectric layer 400 is preferably high-k dielectric layer.The material of high-k dielectric layer 400 include but not limited to HfAlON, HfSiAlON,
One in HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON or its combination in any.Chemistry can be used
The techniques such as vapour deposition (CVD), ald (ALD) form high-k dielectric layer 400.The upper table of described high-k dielectric layer 400
Face is less than the side wall 310 not being etched and the upper surface of gate material layers 300, and covers other parts of semiconductor structure.
With reference to Fig. 6, Fig. 6 (a)～Fig. 6 (c), continue executing with step S105, formed be positioned at the fin structure in fin room and
It is positioned at the source-drain area of fin structure both sides.First deposited amorphous silicon materials on whole semiconductor structure, amorphous silicon material is filled with
Run through the fin room of gate material layers 300 and side wall 310；Afterwards with gate material layers 300 and side wall 310 as stop-layer, carry out
Planarization processes, and makes side wall 310 and gate material layers 300 expose, and with the upper surface flush of amorphous silicon material；Finally swash
Light high annealing carries out recrystallization to amorphous silicon material.The silicon materials of the recrystallization being positioned in fin room form fin structure.
Then, in order to isolate adjacent device.With reference to Fig. 7, Fig. 7 (a)～Fig. 7 (c), recrystallization silicon layer 500 is carved
Erosion.Optionally, it is initially formed mask layer, and is patterned.Formation mask layer and the technique and the material that are patterned exist
The preceding sections of this specification has been explained, and does not repeats them here.After being patterned, according to the pattern after graphical to again
Crystallizing silicon layer 500 performs etching, expose portion high-k dielectric layer 400, to isolate adjacent device.
Optionally, forming source/drain region (not shown), source/drain region can be by being positioned at tying again of fin structure both sides
Implanting p-type or N-type dopant or impurity in crystal silicon layer and formed.Such as, for PMOS, source/drain region can be that p-type is mixed
Miscellaneous；For NMOS, source/drain region can be n-type doping.
Optionally, anneal, to activate the impurity in source/drain region.Such as can use laser annealing, flash anneal
Deng, activate the impurity in source/drain region.In one embodiment, spike technique can be used fin field effect crystal
Pipe is annealed, such as, carry out laser annealing under about 800 DEG C～the high temperature of 1100 DEG C.
Optionally, with reference to Fig. 8, Fig. 8 (a)～Fig. 8 (c), form contact plug 610.First, on fin FET
Form interlayer dielectric layer 600, cover whole fin FET.Afterwards, etching interlayer dielectric layer 600 is formed and makes recrystallization
The contact hole that silicon layer 500 and gate material layers 300 at least partly expose.Specifically, it is possible to use dry etching, wet etching or
Other suitable etching mode etching interlayer dielectric layer 600 is to form contact hole.Owing to gate material layers 300 is by side wall 310 institute
Therefore protection, even if carrying out over etching be also not result in the short circuit of gate material layers 300 and source/drain region when forming contact hole.
Further, depositing metal on the recrystallization silicon layer 500 and gate material layers 300 of contact hole bottom exposed, this metal is through connecing
Contact hole runs through interlayer dielectric layer 600 and exposes its top.Preferably, the material of this metal is W.Certainly according to the manufacture of quasiconductor
Needing, the material of deposition metal includes but not limited in W, Al, TiAl alloy any one or its combination in any.
Use the semiconductor making method that the present invention provides, it is possible to formed for isolated gate and the high-quality of source/drain region
Side wall, is effectively improved the production yield of semiconductor device.
As follows according to the fin FET structure that said method manufactures.
This fin FET includes: substrate 100；Gate stack, is positioned on substrate 100, described gate stack
Including dielectric layer under grid 200 and gate material layers 300；Side wall 310, is positioned at gate stack both sides；Fin structure, runs through grid material
Layer and side wall, have gate dielectric layer 400 between fin structure and gate material layers；Source-drain area, is positioned at the both sides of fin structure.
Substrate 100 includes silicon substrate (such as silicon wafer).(such as P type substrate is required according to design known in the art
Or N-type substrate), substrate 100 can include various doping configuration.In other embodiments, substrate 100 can also include other bases
This quasiconductor, such as germanium.Or, substrate 100 can include compound semiconductor, such as carborundum, GaAs, indium arsenide or
Indium phosphide.Typically, substrate 100 can have but be not limited to the thickness of the most hundreds of micron, such as can be 400um-800um's
In thickness range.
Under grid, dielectric layer 200 can be thermal oxide layer, including silicon oxide or silicon oxynitride.It is preferably high K medium, such as:
One in HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON or its any group
Close.
Gate material layers 300 can be that metal material is made, preferably polysilicon.Metal material include but not limited to TaN,
TaC、TiN、TaAlN、TiAlN、MoAlN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTaxIn
One or its combination in any.
Side wall 310 can be by silicon nitride, silicon oxide, silicon oxynitride, carborundum and combinations thereof, and/or other suitable materials
Material is formed.
Gate dielectric layer 400 is preferably high-k dielectric layer, including HfAlON, HfSiAlON, HfTaAlON, HfTiAlON,
One in HfON, HfSiON, HfFaON, HfTiON or its combination in any.
Recrystallization silicon layer 500 is formed after carrying out high annealing for amorphous silicon material.
Optionally, this fin FET can also include interlayer dielectric layer 600 and be formed at interlayer dielectric layer 600
In contact plug 610.The material of interlayer dielectric layer 600 can use and include SiO2, carbon doping SiO2, BPSG, PSG, UGS, nitrogen oxygen
SiClx, low-k materials or its combination in any.
The material of the contacting metal that contact plug 610 uses is preferably W.Manufacture needs according to fin FET,
The material of contacting metal includes but not limited in W, Al, TiAl alloy any one or its combination in any.
Although being described in detail about example embodiment and advantage thereof, it should be understood that without departing from the present invention spirit and
In the case of protection domain defined in the appended claims, these embodiments can be carried out various change, substitutions and modifications.Right
In other examples, those of ordinary skill in the art it should be readily appreciated that while keeping in scope, technique
The order of step can change.
Additionally, the range of application of the present invention is not limited to the technique of specific embodiment described in description, mechanism, system
Make, material composition, means, method and step.From the disclosure, will be easily as those of ordinary skill in the art
Ground understands, for the technique having existed at present or will having developed later, mechanism, manufacture, material composition, means, method or
Step, wherein they perform the knot that the function that is substantially the same of corresponding embodiment or acquisition with present invention description are substantially the same
Really, they can be applied according to the present invention.Therefore, claims of the present invention are intended to these technique, mechanism, system
Make, material composition, means, method or step are included in its protection domain.
Claims (5)
1. a manufacture method for fin FET, including:
A) Semiconductor substrate (100) is provided；
B) forming gate stack in Semiconductor substrate (100), described gate stack includes dielectric layer under grid (200) and grid successively
Pole material layer (300)；
C) side wall (310) is formed in described gate stack both sides；
D) formation runs through the fin room of gate material layers and side wall；
E) in fin room, gate dielectric layer (400) is formed；
F) formation is positioned at the fin structure in fin room and is positioned at the source-drain area of fin structure both sides.
Method the most according to claim 1, wherein gate dielectric layer (400) is high-k dielectric layer.
Method the most according to claim 1, wherein, step f) including:
Deposited amorphous silicon materials；
Execution planarization process, make described side wall (310) and described gate material layers (300) exposure, and with described non-crystalline silicon material
The upper surface flush of material；
Carry out annealing and make amorphous silicon layer (500) recrystallization, formed and be positioned at the fin structure in fin room；
Carry out ion implanting in fin structure both sides and form source-drain area.
Method the most according to claim 1, wherein, also includes after described step f):
Form contact plug (610).
Method the most according to claim 2, it is characterised in that described high-k dielectric layer (400) include HfAlON,
One in HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON or its combination in any.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310286545.9A CN104282571B (en) | 2013-07-09 | 2013-07-09 | Fin FET and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310286545.9A CN104282571B (en) | 2013-07-09 | 2013-07-09 | Fin FET and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104282571A CN104282571A (en) | 2015-01-14 |
| CN104282571B true CN104282571B (en) | 2016-12-28 |
Family
ID=52257349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310286545.9A Active CN104282571B (en) | 2013-07-09 | 2013-07-09 | Fin FET and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104282571B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1503372A (en) * | 2002-11-26 | 2004-06-09 | 台湾积体电路制造股份有限公司 | Transistor with multi-gate and strain channel layer and mfg method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100679693B1 (en) * | 2004-10-29 | 2007-02-09 | 한국과학기술원 | Non-Volatile Memory Structure for two Bits Cell Operation with Asymmetrical Work Function Double Gate and its Manufacturing |
| US7517764B2 (en) * | 2006-06-29 | 2009-04-14 | International Business Machines Corporation | Bulk FinFET device |
-
2013
- 2013-07-09 CN CN201310286545.9A patent/CN104282571B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1503372A (en) * | 2002-11-26 | 2004-06-09 | 台湾积体电路制造股份有限公司 | Transistor with multi-gate and strain channel layer and mfg method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104282571A (en) | 2015-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10084080B2 (en) | Vertical tunneling FinFET | |
| CN101714508B (en) | Method for fabricating semiconductor device | |
| CN103779226B (en) | Quasi-nano-wire transistor and manufacture method thereof | |
| US9401302B2 (en) | FinFET fin bending reduction | |
| CN103137488B (en) | Semiconductor device and manufacture method thereof | |
| TWI533408B (en) | Thin-film transistor, active matrix organic light emitting diode assembly, and manufacturing method thereof | |
| CN104821296A (en) | Semiconductor device and forming method thereof | |
| US20100193872A1 (en) | Work function adjustment in a high-k gate electrode structure after transistor fabrication by using lanthanum | |
| US9159798B2 (en) | Replacement gate process and device manufactured using the same | |
| CN104576382B (en) | A kind of asymmetric FinFET structure and its manufacture method | |
| KR20120067973A (en) | Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities | |
| CN104217954A (en) | Formation method of transistors | |
| US9837417B1 (en) | Semiconductor device and method for fabricating the same | |
| CN104282571B (en) | Fin FET and manufacture method thereof | |
| CN103779227B (en) | The manufacture method of fin FET | |
| US10770360B2 (en) | Semiconductor structures and fabrication methods thereof | |
| CN104465377A (en) | Pmos transistor and forming method thereof | |
| CN105633151B (en) | A kind of asymmetric FinFET structure and its manufacturing method | |
| US20120302025A1 (en) | Method for Manufacturing a Semiconductor Structure | |
| CN103165622B (en) | A kind of semiconductor structure and manufacture method thereof | |
| CN203038895U (en) | Semiconductor structure | |
| CN103515232B (en) | Semiconductor structure and manufacture method thereof | |
| CN108400116B (en) | Method for manufacturing semiconductor device | |
| CN108573850B (en) | Method for manufacturing semiconductor device | |
| CN106711041B (en) | The forming method of semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |