CN106711041B

CN106711041B - The forming method of semiconductor devices

Info

Publication number: CN106711041B
Application number: CN201510465605.2A
Authority: CN
Inventors: 赵杰
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2015-07-31
Filing date: 2015-07-31
Publication date: 2019-09-27
Anticipated expiration: 2035-07-31
Also published as: CN106711041A

Abstract

A kind of forming method of semiconductor devices, it include: to form the first oxide layer and pseudo- grid layer in first area substrate surface, the first oxide layer, the first barrier layer and pseudo- grid layer are formed in second area substrate surface, forms the first oxide layer, the first barrier layer, the second barrier layer and pseudo- grid layer on third area substrate surface；Interlayer dielectric layer is formed in substrate surface；Etching removes the pseudo- grid layer of first area, second area and third region；First oxide layer of etching removal first area；Processing is doped to the first area substrate exposed, reduces the oxidation rate of oxidation technology oxidation first area substrate；First barrier layer of etching removal second area and the first oxide layer；Second oxide layer is formed in first area substrate surface using oxidation technology, while forming third oxide layer in second area substrate surface, and the thickness of second oxide layer is less than the thickness of third oxide layer.The present invention improves the electric property of semiconductor devices.

Description

The forming method of semiconductor devices

Technical field

The present invention relates to semiconductor fabrication techniques field, in particular to a kind of forming method of semiconductor devices.

Background technique

The main semiconductor devices of integrated circuit especially super large-scale integration is Metal-oxide-semicondutor field effect (MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor), abbreviation field-effect tube should be managed.

The working characteristics of semiconductor devices is determined by the construction of many different field-effect tube, including gate dielectric layer Thickness.Wherein, the upper limit of field-effect tube operating voltage, it is mainly related with the breakdown voltage that gate dielectric layer can be born, it is described to hit Voltage is worn mainly to determine and the equivalent oxide thickness of gate dielectric layer (EOT, Equivalent Oxide Thickness).It is equivalent Oxide thickness determines that the dielectric constant of material is higher or physical thickness is smaller, then by the dielectric constant and physical thickness of material The equivalent oxide thickness of gate dielectric layer is smaller.In general, the gate dielectric layer needs of the field-effect tube of work under high voltages are thicker Equivalent oxide thickness, the gate dielectric layer for the field-effect tube under lower operating voltage of working needs relatively thin equivalent oxide Thickness.Since various field-effect tube are usually designed for different operating voltages, production has a variety of equivalent oxides The field-effect tube of thickness becomes current one of research hotspot.

And with the rapid development of semiconductor processing technology, integrated circuit is sent out towards high device density, high integration direction It opens up, the physical thickness of the gate dielectric layer in semiconductor devices constantly reduces, and semiconductor device is caused asking for leakage current increase occur Topic.

To solve the problems, such as that leakage current increases, the solution currently proposed is to replace passing using high-k gate dielectric layer material The silicon dioxide gate dielectric layer material of system, and use metal as gate electrode layer material, to avoid high-k gate dielectric layer material and pass Fermi level pinning effect occurs for gate electrode layer material of uniting.

However, the prior art forms the complex process, at high cost of semiconductor devices, and the electricity of the semiconductor devices formed Performance is to be improved.

Summary of the invention

Problems solved by the invention is to provide a kind of forming method of semiconductor devices, is meeting different field-effect tube equities While the difference of effect oxide thickness requires, the quality of the gate dielectric layer of formation is improved, to improve the electricity of semiconductor devices Learn performance.

To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising: providing includes the firstth area Domain, second area and third region substrate, the substrate surface is formed with the first oxidation film, wherein the second area and The first oxidation film surface in third region is formed with the first barrier film, and the is formed on first barrier film in the third region Two barrier films；Stop film surface and third region in the first oxidation film surface of the first area, the first of second area Second blocking film surface form pseudo- grid film；The graphical pseudo- grid film, the second barrier film, the first barrier film and the first oxidation Film, the substrate surface in first area form the first oxide layer and pseudo- grid layer, form first in the substrate surface of second area Oxide layer, the first barrier layer and pseudo- grid layer, the substrate surface in third region form the first oxide layer, the first barrier layer, the Two barrier layers and pseudo- grid layer；Interlayer dielectric layer is formed in the substrate surface, and at the top of interlayer dielectric layer and at the top of pseudo- grid layer It flushes；Etching removes the pseudo- grid layer of the first area, second area and third region；Etching removes the of the first area One oxide layer exposes first area section substrate surface；Processing is doped to the first area substrate exposed, is dropped The oxidation rate of suboxides technique oxidation first area substrate；Etching removes the first barrier layer and the first oxygen of the second area Change layer；Oxidation processes are carried out to the first area substrate exposed, second area substrate using oxidation technology, in the firstth area Domain substrate surface forms the second oxide layer, while forming third oxide layer, and second oxidation in second area substrate surface The thickness of layer is less than the thickness of third oxide layer, the thickness of the thickness of the third oxide layer less than the first oxide layer.

Optionally, first barrier film is identical as the material of the second barrier film；First barrier film in the third region Intermediate coat is also formed between the second barrier film, and the material of the intermediate coat is different from the material of the first barrier film；It is described Middle layer is also formed between first barrier layer and the second barrier layer in third region.

Optionally, while etching removes the first barrier layer and the first oxide layer of the second area, third region The second barrier layer and middle layer be etched removal；After carrying out the oxidation technology, the first of etching removal third region Barrier layer.

Optionally, the processing step for forming first barrier film, intermediate coat and the second barrier film includes: successively the One oxidation film surface forms the first barrier film, the intermediate coat for stopping film surface positioned at first and positioned at the of intermediate film surface Two barrier films；The first photoresist layer is formed on the substrate in the second area and third region；With first photoresist layer For exposure mask, the second barrier film, intermediate coat and the first barrier film of etching removal first area；In the first area and third The second photoresist layer is formed on the substrate in region；Using second photoresist layer as exposure mask, the second of etching removal second area Barrier film.

Optionally, before etching removes the second barrier film, intermediate coat and the first barrier film of the first area or Later, it further comprises the steps of: using first photoresist layer as exposure mask, ion implanting is carried out to the substrate of the first area, The first well region is formed in the substrate of first area；Before or after the second barrier film of etching removal second area, further include Step: using second photoresist layer as exposure mask, ion implanting is carried out to the substrate of the second area, in the lining of second area The second well region is formed in bottom.

Optionally, the material of first barrier film is SiN, SiON, SiBN, SiCN, SiOBN, SiOCN, HfO₂、 HfZrO₂, HfSiO, HfSiON, TiN or TaN；The material of second barrier film be SiN, SiON, SiBN, SiCN, SiOBN, SiOCN、HfO₂、HfZrO₂, HfSiO, HfSiON, TiN or TaN.

Optionally, the Doped ions of the doping treatment are Nitrogen ion.Optionally, the technological parameter of the doping treatment Are as follows: N₂Flow is 50sccm to 500sccm, and chamber pressure is 10 millitorrs to 30 millitorrs, and power is 40 watts to 400 watts.

Optionally, the material of second oxide layer is silicon oxynitride；The material of the third oxide layer is silica；Institute The material for stating the first oxide layer is silica.Optionally, the thickness of second oxide layer is less than 10 angstroms；The third oxide layer With a thickness of 10 angstroms to 20 angstroms；First oxide layer with a thickness of 20 angstroms to 30 angstroms.

Optionally, first barrier film is different from the material of the second barrier film；Second barrier film in the third region Stop film surface positioned at first.Optionally, after carrying out the oxidation technology, etching removes second resistance in the third region Barrier and the first barrier layer.Optionally, it further comprises the steps of: in the second oxidation layer surface, third oxidation layer surface, Yi Ji The first oxidation layer surface in three regions forms high-k gate dielectric layer；Metal gate electrode layer, and institute are formed in high-k gate dielectric layer surface It states and is flushed at the top of metal gate electrode layer with interlayer dielectric layer top.

The present invention also provides a kind of forming methods of semiconductor devices, comprising: provide include first area, second area and The substrate in third region, the substrate surface are formed with the first oxidation film, wherein the first of the second area and third region Oxidation film surface is formed with the first barrier film, and is formed with the second barrier film on first barrier film in the third region；Etching The first oxidation film for removing the first area, exposes first area substrate surface；To the first area lining exposed Bottom is doped processing, reduces the oxidation rate of oxidation technology oxidation first area substrate；Etching removes the second area First barrier film and the first oxidation film；The first area substrate, second area substrate are aoxidized using oxidation technology Processing, in first area, substrate surface forms the second oxidation film, while forming third oxidation film in second area substrate surface, and The thickness of second oxidation film is less than the thickness of third oxidation film, and the thickness of the third oxidation film is less than the first oxidation film Thickness；Etching removes second barrier film and the first barrier film in the third region.

Optionally, it further comprises the steps of: the of the second oxidation film surface, third oxidation film surface and third region One oxidation film surface forms high-k gate dielectric film；Pseudo- grid film is formed in the high-k gate dielectric film surface；The graphical pseudo- grid film, High-k gate dielectric film, the second oxidation film, third oxidation film, third region the first oxidation film, in first area, substrate surface is formed Second oxide layer, high-k gate dielectric layer and pseudo- grid layer form third oxide layer, high-k gate dielectric layer in second area substrate surface And pseudo- grid layer, the first oxide layer, high-k gate dielectric layer and pseudo- grid layer are formed on third area substrate surface, wherein the second oxygen The thickness for changing layer is less than the thickness of third oxide layer, the thickness of the thickness of third oxide layer less than the first oxide layer；In the lining Bottom surface forms interlayer dielectric layer, and flushes at the top of the interlayer dielectric layer at the top of pseudo- grid layer；The etching removal pseudo- grid layer； High-k gate dielectric layer surface in the first area, second area and third region forms metal gate electrode layer, and the metal It is flushed at the top of gate electrode layer with interlayer dielectric layer top.

Optionally, it further comprises the steps of: the of the second oxidation film surface, third oxidation film surface and third region One oxidation film surface forms pseudo- grid film；The graphical pseudo- grid film, the second oxidation film, third oxidation film, third region first Oxidation film, in first area, substrate surface forms the second oxide layer and pseudo- grid layer, forms third in second area substrate surface Oxide layer and pseudo- grid layer form the first oxide layer and pseudo- grid layer on third area substrate surface, wherein the second oxide layer Thickness is less than the thickness of third oxide layer, the thickness of the thickness of third oxide layer less than the first oxide layer；In the substrate surface Interlayer dielectric layer is formed, and is flushed at the top of the interlayer dielectric layer at the top of pseudo- grid layer；The etching removal pseudo- grid layer；Described Second oxidation layer surface, third oxidation layer surface, the first oxidation layer surface form high-k gate dielectric layer；In the high-k gate dielectric layer Surface forms metal gate electrode layer, and flushes at the top of the metal gate electrode layer with interlayer dielectric layer top.

Optionally, first barrier film is identical as the material of the second barrier film；First barrier film in the third region Intermediate coat is also formed between the second barrier film, and the material of the intermediate coat is different from the material of the first barrier film.

Optionally, the Doped ions of the doping treatment are Nitrogen ion；The material of first oxidation film is silica；Institute The material for stating the second oxidation film is silicon oxynitride；The material of the third oxidation film is silica.

Compared with prior art, technical solution of the present invention has the advantage that

In the technical solution of the forming method of semiconductor devices provided by the invention, the first oxidation is formed in substrate surface Film, the first oxidation film surface in second area and third region is formed with the first barrier film, and the first of third region stops The second barrier film is formed on film；Then pseudo- grid film is formed in the first barrier film and the second blocking film surface；Then graphical pseudo- Grid film, the second barrier film, the first barrier film and the first oxidation film, in first area substrate surface formed the first oxide layer and Pseudo- grid layer forms the first oxide layer, the first barrier layer and pseudo- grid layer in second area substrate surface, the substrate in third region Surface forms the first oxide layer, the first barrier layer, the second barrier layer and pseudo- grid layer；Substrate surface formed interlayer dielectric layer it Afterwards, etching removes the pseudo- grid layer of first area, second area and third region；First oxide layer of etching removal first area, And etch stopper is played the role of on the first barrier layer of second area, the third barrier layer in third region, prevents second area and First oxide layer in three regions is etched removal；Processing is doped to the first area substrate exposed, reduces oxidation technology The oxidation rate of first area substrate is aoxidized, therefore, when the substrate to first area and second area carries out oxidation technology, The thickness for the second oxide layer that first area substrate surface is formed is less than the third oxide layer that second area substrate surface is formed Thickness requires the difference of equivalent oxide thickness to meet different field-effect tube.Also, the second oxidation in the present embodiment Layer and third oxide layer do not undergo the technique of removal photoresist layer, and avoid etching technics to the second oxide layer and third oxide layer Etching injury is caused, the quality for the second oxide layer and third oxide layer to be formed is improved, so as to improve the semiconductor device of formation The electric property of part.

Further, in the present invention, using the first photoresist layer formed when forming the first well region and the second well region is formed When the second photoresist layer, the first oxidation film surface in second area and third region forms the first barrier film, in third area The second barrier film is formed on first barrier film in domain.Therefore, the present invention is without being additionally formed photoresist layer, to save production Cost improves production efficiency.

Detailed description of the invention

Fig. 1 to Fig. 5 is the schematic diagram of the section structure for the semiconductor devices forming process that one embodiment of the invention provides；

Fig. 6 to Figure 18 be another embodiment of the present invention provides semiconductor devices forming process the schematic diagram of the section structure；

Fig. 6 to Figure 10, Figure 19 to Figure 24 be the section of semiconductor devices forming process that further embodiment of this invention provides Structural schematic diagram.

Specific embodiment

It can be seen from background technology that the prior art forms the complex process of semiconductor devices, semiconductor at high cost, and being formed The electric property of device is to be improved.

In one embodiment, formed tool there are three types of different equivalent oxide thickness semiconductor devices method include with Lower step:

With reference to Fig. 1, substrate 100 is provided, the substrate 100 includes first area 10, second area 20 and third region 30； Wherein, 10 substrate of first area, 100 surface, 20 substrate of second area, 100 surface and 30 substrate of third region, 100 surface difference It is formed with pseudo- grid structure, dummy gate structure includes the first oxide layer 101 and the polysilicon positioned at 101 surface of the first oxide layer Layer 102；Interlayer dielectric layer 103 is formed on 100 surface of substrate, the interlayer dielectric layer 103 covers pseudo- grid structure side wall table Face, and flushed at the top of 103 top of the interlayer dielectric layer and pseudo- grid structure；

With reference to Fig. 2, the polysilicon layer 102 (referring to Fig. 1) in first area 10, second area 20 and third region 30 is removed； The first photoresist layer 104 is formed on 101 surface of the first oxide layer in the third region 30；With first photoresist layer 104 For exposure mask, the first oxide layer 101 of etching removal first area 10, formed be located at first area 10 interlayer dielectric layer 103 it Between first opening 105, etching removal second area 20 the first oxide layer 101, formed be located at second area 20 interlayer be situated between The second opening 106 between matter layer 103；

With reference to Fig. 3, first photoresist layer 104 (referring to Fig. 2) is removed；In first 105 bottoms of opening and the Second oxide layer 107 is formed on two 106 bottoms of opening, and the thickness of second oxide layer 107 is less than the thickness of the first oxide layer 101 Degree；

The first oxide layer 101 with reference to Fig. 4, on 107 surface of the second oxide layer of the second area 20, third region 30 Surface forms the second photoresist layer 108；It is exposure mask with second photoresist layer 108,105 bottoms of the first opening of etching removal Second oxide layer 107；

With reference to Fig. 5, second photoresist layer 108 (referring to Fig. 4) is removed；The is formed in first opening, 105 bottoms Three oxide layers 109, and the thickness of the third oxide layer 109 is less than the thickness of the second oxide layer 107.

Subsequent processing step includes: to aoxidize in 101 surface of the first oxide layer, 107 surface of the second oxide layer and third 109 surface of layer form high-k gate dielectric layer, form metal gates, and metal gates top and layer in high-k gate dielectric layer surface Between flush at the top of dielectric layer 103.

The forming method of the semiconductor devices of above-mentioned offer, including multiple formation photoresist layer and removal photoresist layer Processing step so that the formation process of semiconductor devices is complicated and high production cost.Also, due to the first of third region 30 Oxide layer 101 and the second oxide layer 107 of second area 20 are in contact with Other substrate materials, first oxygen in third region 30 The second oxide layer 107 for changing layer 101 and second area 20 experienced the processing step for removing Other substrate materials, remove photoetching The processing step of glue material be easy to cause first oxide layer 101 in third region 30 and the second oxide layer 107 of second area 20 Quality be deteriorated, cause the yield of semiconductor devices to decline, and then cause adverse effect to the electric property of semiconductor devices.

For this purpose, the present invention provides a kind of forming method of semiconductor devices, meeting different field-effect tube to gate dielectric layer Equivalent oxide thickness requirement difference while, the quality of the gate dielectric layer of formation is improved, so as to improve semiconductor devices Electric property.

To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.

Fig. 6 to Figure 18 be another embodiment of the present invention provides semiconductor devices forming process the schematic diagram of the section structure.

The present embodiment forms high-k gate dielectric layer, forms metal gates (high k last metal afterwards after using Gatelast mode) forms semiconductor devices.

With reference to Fig. 6, the substrate 200 including first area I, second area II and third region III is provided.

The substrate 200 is one of the silicon on monocrystalline silicon, polysilicon, amorphous silicon or insulator；The substrate 200 It can be Si substrate, Ge substrate, GeSi substrate or GaAs substrate；200 surface of substrate can also form several epitaxial interfaces Layer or strained layer are to improve the electric property of semiconductor devices.

In the present embodiment, the substrate 200 is Si substrate.The first area I, second area II and third region III To be formed there is the field-effect tube of different operating voltage to provide technique platform.It is subsequent to form first on first area I substrate 200 Gate dielectric layer, first gate dielectric layer have the first equivalent oxide thickness；Second is formed on second area II substrate 200 Gate dielectric layer, second gate dielectric layer have the second equivalent oxide thickness；Is formed on third region III substrate 200 Three gate dielectric layers, the third gate dielectric layer have third equivalent oxide thickness.The present embodiment is with the first equivalent oxide thickness Degree, which is less than third equivalent oxide thickness as example less than the second equivalent oxide thickness, the second equivalent oxide thickness, to carry out It is described in detail.

The first area I, second area II and third region III can be adjacent or be separated by.The present embodiment is with One region I, second area II and third region III are arranged successively and adjacent as example.

Fleet plough groove isolation structure 201 can also be formed in the substrate 200.The fleet plough groove isolation structure 201 is filled out Fill material can for one or more of silica, silicon nitride, silicon oxynitride, fleet plough groove isolation structure 201 be mainly used for every From first area I, second area II and third region III, prevent from being electrically connected between different field-effect tube.

With continued reference to Fig. 6, the first oxidation film 202 successively is formed, positioned at the first oxidation film 202 on 200 surface of substrate First barrier film 203 on surface, positioned at the intermediate coat 204 on 203 surface of the first barrier film and positioned at 204 surface of intermediate coat Second barrier film 205.

First oxidation film 202 is to be subsequently formed the first pseudo- grid structure, the second pseudo- grid structure and third puppet grid structure to mention For Process ba- sis, and rear extended meeting carries out ion implanting to substrate 200 and forms well region, and first oxidation film 202 can prevent Ion implanting causes lattice damage to substrate 200；Meanwhile it being subsequently used for being formed positioned at the first oxidation film 202 of third region III A part of third gate dielectric layer.

The material of first oxidation film 202 is silica；Using thermal oxidation technology, atom layer deposition process or chemical gas Phase depositing operation forms first oxidation film 202.In the present embodiment, first oxidation film is formed using thermal oxidation technology 202, the first oxidation film 202 with a thickness of 20 angstroms to 30 angstroms.

The material of first barrier film 203 is different from the material of the first oxidation film 202, so that subsequent etching technics pair First barrier film 203 is different with the etch rate of the first oxidation film 202.The material of first barrier film 203 is silicon nitride, is adopted First barrier film 203 is formed with tropical resources technique, atom layer deposition process or chemical vapor deposition process.

The material of first barrier film 203 is SiN, SiON, SiBN, SiCN, SiOBN, SiOCN, HfO₂、HfZrO₂、 HfSiO, HfSiON, TiN or TaN；The material of second barrier film 205 be SiN, SiON, SiBN, SiCN, SiOBN, SiOCN、HfO₂、HfZrO₂, HfSiO, HfSiON, TiN or TaN.In the present embodiment, first barrier film 203 and second stops The material of film 205 is identical, is also formed with intermediate coat 204 between first barrier film 203 and the second barrier film 205, it is described in Between film 204 material it is different from the material of the first barrier film 203.

Select dielectric material as the first barrier film 202 and the in order to avoid unnecessary metallic pollution, in the present embodiment The material of two barrier films 205.In the present embodiment, the material of first barrier film 203 is silicon nitride, with a thickness of 10 angstroms to 50 Angstrom；The material of the intermediate coat 204 is silica, with a thickness of 10 angstroms to 50 angstroms；The material of second barrier film 205 is nitridation Silicon, with a thickness of 10 angstroms to 50 angstroms.

In other embodiments, it when the material difference of the first barrier film and the second barrier film, then can not need to be formed Between film, directly first stop film surface formed the second barrier film.

With reference to Fig. 7, the first photoetching is formed on 205 surface of the second barrier film of the second area II and third region III Glue-line 206；It is exposure mask with first photoresist layer 206, ion implanting is carried out to the substrate 200 of first area I, in the firstth area The first well region (not shown) is formed in the substrate 200 of domain I.

In one embodiment, first area I is when forming the region of N-type field-effect tube, the ion implantation technology Injection ion is P-type ion, such as boron, gallium or indium；In another embodiment, first area I is the region to form p-type field-effect tube When, the injection ion of the ion implantation technology is N-type ion, such as phosphorus, arsenic or antimony.

It is formed in the technique of the first well region carrying out ion implanting, since I substrate 200 surface in first area is formed with first Oxide layer 202 reduces first area I lining to prevent the injection ion in ion implantation technology from directly bombarding 200 surface of substrate The lattice damage that bottom 200 is subject to.

It, can also be in first area I, second area II and third region before forming first photoresist layer 206 205 surface of the second barrier film of III forms bottom antireflective coating.

It is exposure mask with first photoresist layer 206 with reference to Fig. 8, the second barrier film 205 of etching removal first area I, Intermediate coat 204 and the first barrier film 203 expose 202 surface of the first oxidation film of first area I.

After forming the first well region, retain the first photoresist layer 206 for being located at second area II and third region III. It is exposure mask with the first photoresist layer 206, the second barrier film 205, the centre of removal first area I is etched using dry etch process Film 204 and the first barrier film 203.

In the present embodiment, without being additionally formed photoresist layer, it is using the first photoresist layer 206 when forming the first well region Exposure mask performs etching the second barrier film 205 of removal first area I, the etching work of intermediate coat 204 and the first barrier film 203 Skill saves production cost to simplify processing step.

After the second barrier film 205, intermediate coat 204 and the first barrier film 203 of etching removal first area I, go Except first photoresist layer 206.It is removed photoresist using wet process or cineration technics removes first photoresist layer 206.

In other embodiments, the second barrier film, intermediate coat and the first resistance of removal first area can also first be etched Film is kept off, then using the first photoresist layer as exposure mask, ion implanting is carried out to first area substrate and forms the first well region.

With reference to Fig. 9, on 202 surface of the first oxide layer of the first area I, the second barrier film 205 of second area II Surface forms the second photoresist layer 207, and second photoresist layer 207 exposes 205 table of the second barrier film of second area II Face；It is exposure mask with second photoresist layer 207, ion implanting is carried out to the substrate 200 of second area II, in second area II Substrate 200 in formed the second well region (not shown).

In one embodiment, second area II is when forming the region of N-type field-effect tube, the ion implantation technology Injection ion is P-type ion, such as boron, gallium or indium；In another embodiment, second area II is the area to form p-type field-effect tube When domain, the injection ion of the ion implantation technology is N-type ion, such as phosphorus, arsenic or antimony.The is formed carrying out ion implantation technology In the technique of two well regions, can be avoided injection ion and directly bombard 200 surface of substrate, reduction second area II substrate 200 by Lattice damage.

Before forming second photoresist layer 207, can also first area I 202 surface of the first oxidation film, the 205 surface of the second barrier film of two region II and 205 surface of the second barrier film of third region III form bottom anti-reflective and apply Layer.

It is exposure mask with second photoresist layer 207 with reference to Figure 10, the second barrier film of etching removal second area II 205。

After forming the second well region, retain the second photoresist layer 207 for being located at first area I and third region III, with Second photoresist layer 207 is exposure mask, using dry etch process, in the second barrier film 205 of etching removal second area II.Nothing It need to be additionally formed photoresist layer, be exposure mask using the second photoresist layer 207 when forming the second well region, perform etching removal second The etching technics of the second barrier film 205 and intermediate coat 204 of region II saves production cost to simplify processing step.

In the present embodiment, after the second barrier film 205 of etching removal second area II, also etching removes second area The intermediate coat 204 of II exposes 203 surface of the first barrier film of second area II.

In other embodiments, the second barrier film 205 of removal second area II can also only be etched.After this is because: The first oxidation film 202 of the graphical first area I of extended meeting forms the first oxide layer, the intermediate coat 204 of graphical second area II Middle layer is formed, the intermediate coat 204 of graphical third region III forms middle layer；And rear extended meeting etching removal first area I First oxide layer, when etching technics is suitable with the etch rate to middle layer to the first oxide layer, the centre of second area II Layer can be etched removal.Also, even if the technique of the first oxide layer of etching removal first area I not can be removed second area II Middle layer, due to rear extended meeting etch removal third region III middle layer, then etching removal third region III in When interbed, the middle layer of second area II can also be etched removal.

In other embodiments, the second barrier film that can also first etch removal second area, then with the second photoresist Layer is exposure mask, carries out ion implanting to second area substrate and forms the second well region.It should be noted that in other embodiments, Then the second barrier film that removal second area can also first be etched etches the second barrier film, the centre of removal first area again Film and the first barrier film.

After the second barrier film 205 and intermediate coat 204 of removal second area II, second photoresist layer is removed 207.It is removed photoresist using wet process or cineration technics removes second photoresist layer 207.

With reference to Figure 11, on 202 surface of the first oxidation film of the first area I, the first barrier film 203 of second area II Surface and 205 surface of the second barrier film of third region III form pseudo- grid film 208.

The puppet grid film 208 provides Process ba- sis to be subsequently formed pseudo- grid.The material of the puppet grid film 208 be polysilicon, Amorphous silicon or amorphous carbon；The pseudo- grid film is formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process 208。

In the present embodiment, the material of the puppet grid film 208 is polysilicon, forms the puppet using chemical vapor deposition process Grid film 208.

With reference to Figure 12, the first pseudo- grid structure is formed on 200 surface of first area I substrate；In the second area II 200 surface of substrate forms the second pseudo- grid structure；Third puppet grid structure is formed on 200 surface of third region III substrate.

Specifically, the pseudo- grid film 208 (referring to Figure 11) on 200 surface of graphical first area I substrate and the first oxidation film 202 (referring to Figure 11) form the described first pseudo- grid structure.First pseudo- grid structure includes: positioned at 200 surface of first area I substrate The first oxide layer 212, the pseudo- grid layer 218 positioned at 212 surface of the first oxide layer.

The pseudo- grid film 208 on graphical 200 surface of second area II substrate, the first barrier film 203 (referring to Figure 11) and the One oxidation film 202 forms the described second pseudo- grid structure.Second pseudo- grid structure includes: positioned at 200 surface of second area II substrate First oxide layer 212, positioned at 212 surface of the first oxide layer the first barrier layer 213 and be located at 213 surface of the first barrier layer Pseudo- grid layer 218.

The pseudo- grid film 208 on 200 surface of graphical third region III substrate, the second barrier film 205 (referring to Figure 11), centre Film 204 (referring to Figure 11), the first barrier film 203 and the first oxidation film 202, form the third puppet grid structure.Third puppet grid Structure includes: the first oxide layer 212 positioned at 200 surface of third region III substrate, positioned at 212 surface of the first oxide layer One barrier layer 213, positioned at the middle layer 214 on 213 surface of the first barrier layer, positioned at second barrier layer on 214 surface of middle layer 215 and the pseudo- grid layer 218 positioned at 215 surface of the second barrier layer.

The material of first oxide layer 212 is identical as the material of the first oxidation film 202；First barrier layer 213 Material is identical as the material of the first barrier film 203；The material of the middle layer 214 is identical as the material of intermediate coat 204；Described The material on two barrier layers 215 is identical as the material of the second barrier film 205.In the technique that subsequent etching removes the second barrier layer 215 In, the middle layer 214 plays the role of etching stopping.

It, can also be in the first puppet after forming the described first pseudo- grid structure, the second pseudo- grid structure and third puppet grid structure Grid structure sidewall surfaces form the first side wall, the second side wall are formed in the second pseudo- grid structure sidewall surfaces, in third puppet grid structure Sidewall surfaces form third side wall.After forming the first pseudo- grid structure, first is carried out to the substrate of the first pseudo- grid structure two sides Doping treatment forms the first source-drain area in the substrate of the first pseudo- grid structure two sides；After forming the second pseudo- grid structure, to the The substrate of two pseudo- grid structure two sides carries out the second doping treatment, forms the second source and drain in the substrate of the second pseudo- grid structure two sides Area；After forming third puppet grid structure, third doping treatment is carried out to the substrate of third puppet grid structure two sides, in third puppet grid Third source-drain area is formed in the substrate of structure two sides.

With reference to Figure 13, interlayer dielectric layer 220, the covering of interlayer dielectric layer 220 first are formed on 200 surface of substrate Pseudo- grid structure sidewall surfaces, the second pseudo- grid structure sidewall surfaces and third puppet grid structure sidewall surfaces, and the inter-level dielectric 220 top of layer is flushed at the top of the first pseudo- grid structure top, the second pseudo- grid structure and at the top of third puppet grid structure.

In the present embodiment, before forming the interlayer dielectric layer 220, further comprise the steps of: in the substrate 200, first Pseudo- grid structure sidewall surfaces, the second pseudo- grid structure sidewall surfaces and third puppet grid structure sidewall surfaces form etching barrier layer 221.The material of the etching barrier layer 221 is different from the material of interlayer dielectric layer 220, subsequent in etching interlayer dielectric layer 220 When formation exposes the first contact hole of the first source-drain area, the etching technics of interlayer dielectric layer 220 is etched to etching barrier layer 221 Etch rate it is small, to prevent etching technics from causing over etching to 200 surface of substrate.

The material of the interlayer dielectric layer 220 is silica, silicon nitride or silicon oxynitride.In the present embodiment, the interlayer The material of dielectric layer 220 is silica, and the material of the etching barrier layer 221 is silicon nitride.

In a specific embodiment, the processing step packet of the interlayer dielectric layer 220 and etching barrier layer 221 is formed It includes: at the top of 200 surface of substrate, the first pseudo- grid structure and at the top of sidewall surfaces, the second pseudo- grid structure and sidewall surfaces, the At the top of three pseudo- grid structures and sidewall surfaces form etch stopper film；Interlayer deielectric-coating is formed in the etch stopper film surface, and It is higher than at the top of the first pseudo- grid structure at the top of the inter-level dielectric film；Grinding removal is higher than the first pseudo- grid structure top, the second pseudo- grid Inter-level dielectric film and etch stopper film at the top of structural top and third puppet grid structure, formed the etching barrier layer 221 with And the interlayer dielectric layer 220 positioned at 221 surface of etching barrier layer.

With reference to Figure 14, the pseudo- grid layer 218 (referring to Figure 13) of first area I, second area II and third region III are removed.

In the present embodiment, using dry etch process, etching off removes first area I, second area II and third area in the same time The pseudo- grid layer 218 of domain III.

The pseudo- grid layer 218 for removing first area I forms the first opening 231, institute in first area I interlayer dielectric layer 220 It states 231 bottom-exposed of the first opening and goes out 212 surface of the first oxide layer.

The pseudo- grid layer 218 for removing second area II forms the second opening 232 in second area II interlayer dielectric layer 220, Second opening, 232 bottom-exposeds go out 213 surface of the first barrier layer.In other embodiments, the pseudo- grid layer 218 of second area When being also formed with middle layer between the first barrier layer, then the second open bottom exposes interlayer surfaces.

The pseudo- grid layer 218 for removing third region III forms third opening in third region III interlayer dielectric layer 220 233。

With reference to Figure 15, removal is located at the first oxide layer 212 of the first 231 bottoms of opening, makes 231 bottom-exposed of the first opening 200 surface of first area I substrate out；Processing 222 is doped to the substrate 200 of 231 lower section of the first opening, reduces oxidation The oxidation rate of technique oxidation first area I substrate 200.

During the first oxide layer 212 of 231 bottoms of the first opening of etching removal, due to the second 232 bottoms of opening It is formed with the first barrier layer 213, first barrier layer 213 can play the first oxide layer 212 of protection second area II Effect prevents the first oxide layer 212 of second area II to be etched removal.Likewise, third is open, 233 bottoms are formed with second Barrier layer 215 can play the first oxide layer of protection third region III positioned at the second barrier layer 215 of third region III 212 effect.

In the present embodiment, the first oxide layer of the first 231 bottoms of opening is located at using dry etch process etching removal 212.In other embodiments, the first oxidation of the first open bottom can also be located at using wet-etching technology etching removal Layer, the etch liquids of wet-etching technology are hydrofluoric acid solution, wherein the volume ratio of hydrofluoric acid and deionized water be 1:500 extremely 1:700。

In other embodiments, it if the first barrier layer surface of second area is formed with middle layer, is removed in etching While positioned at the first oxide layer of the first open bottom, the middle layer of etching removal second area.

Since the second 232 bottoms of opening are formed with the first oxide layer 212 and the first barrier layer 213, so that doping treatment 222 will not be doped the substrate 200 of 232 lower section of the second opening.Likewise, third is open, 233 bottom surfaces are formed with the One oxide layer 212, the first barrier layer 213, middle layer 214 and the second barrier layer 215, so that doping treatment 222 will not be right The substrate 200 of 233 lower section of third opening is doped.Therefore, in the present embodiment, without being additionally formed needed for doping treatment 222 Mask plate, can be realized and only the substrate 200 of 231 lower section of the first opening is doped, to reduce processing step, save Production cost.

In the present embodiment, the Doped ions of the doping treatment 222 are Nitrogen ion, the substrate below the first opening 231 Nitrogen ion is adulterated in 200, can reduce the oxidation rate of the substrate 200 of 231 lower section of the first opening of subsequent oxidation technique oxidation.

In a specific embodiment, the technological parameter of the doping treatment are as follows: N₂Flow is 50sccm to 500sccm, Chamber pressure is 10 millitorrs to 30 millitorrs, and power is 40 watts to 400 watts and refers to Figure 16, removes 232 lower section of the second opening First barrier layer 213 (referring to Figure 15) and the first oxide layer 212 (referring to Figure 15) make 232 bottom-exposed of the second opening go out the Two region II substrates, 200 surface.

In the present embodiment, 200 surface of second area II substrate is exposed, and is subsequent progress oxidation technology in the secondth area II substrate 200 surface in domain forms third oxide layer and provides Process ba- sis.The first barrier layer below the opening of removal second 232 While 213, positioned at the second barrier layer 215 (referring to Figure 15) of 233 lower section of third opening, be etched removal；It is opened in removal second While first oxide layer 212 of mouthfuls 232 lower sections, the middle layer 214 positioned at 233 lower section of third opening is etched removal.

Since 212 surface of the first oxide layer of third region III is formed with the first barrier layer 213, removed in etching During the first barrier layer 213 of second area II and the first oxide layer 212, protection is played on first barrier layer 213 The effect of one oxide layer 212 prevents the first oxide layer 212 of third region III to be etched removal.

In other embodiments, when the material difference on the first barrier layer and the second barrier layer, below the opening of removal second The first barrier layer and the first oxide layer during, second barrier layer in third region is not etched removal, therefore, subsequent After carrying out oxidation technology, need to etch second barrier layer and the first barrier layer in removal third region.

With reference to Figure 17, using oxidation technology to the substrate of 232 lower section of the opening of substrate 200, second of 231 lower section of the first opening 200 carry out oxidation processes, and 200 surface of substrate below the first opening 231 forms the second oxide layer 223, while opening second 200 surface of substrate of 232 lower section of mouth forms third oxide layer 224, and the thickness of second oxide layer 223 is aoxidized less than third The thickness of layer 224.

In the present embodiment, the oxidation processes are carried out using thermal oxidation technology, the second oxidation is formed using thermal oxidation technology When layer 223 and third oxide layer 224, second oxide layer 223 is in close contact with substrate 200, has good boundary between the two Face performance prevents the generation of boundary defect.Likewise, having good interface between the third oxide layer 224 and substrate 200 Performance, prevents the generation of boundary defect, to prevent the electric leakage of boundary defect bring or breakdown problem, improves semiconductor devices Electric property.

Due in the substrate 200 of 231 lower section of the first opening doped with Nitrogen ion, the thermal oxidation technology oxidation the The oxidation rate of the substrate 200 of one opening, 231 lower section is less than the oxidation rate of the substrate 200 of 232 lower section of the second opening of oxidation, After the completion of thermal oxidation technology, the thickness of the second oxide layer 223 of formation is less than the thickness of third oxide layer 224, to meet not With field-effect tube to the different demands of gate dielectric layer thickness.

As a kind of explanation, Nitrogen ion is adulterated in the substrate 200 below the first opening 231, can reduce oxidation technology The reason of oxidation rate of the substrate 200 of 231 lower section of the first opening of oxidation, is: shape in the substrate 200 of 231 lower section of the first opening At there is Si-N key；For Si-Si bond energy, Si-N bond energy is higher, therefore Si-N key is more stable, and Si-N key is aoxidized institute The energy needed is higher；And in the substrate 200 of 232 lower section of the second opening it is mostly Si-Si bond, therefore oxidation technology is open to second The oxidation rate of the substrate 200 of 232 lower sections is greater than the oxidation rate of the substrate 200 to 231 lower section of the first opening.

In a specific embodiment, the technological parameter of the thermal oxidation technology are as follows: reaction gas includes O₂And H₂, wherein O₂Flow is 0.1slm to 20slm, H₂Flow is 0.1slm to 20slm, and reaction chamber temperature is 650 degree to 1000 degree, reaction chamber Chamber pressure is 0.1 support to 760 supports, and when reaction is 5 seconds to 10 points a length of.Wherein, slm is flux unit, is to rise often under the status of criterion Point.

In the present embodiment, the thickness of the thickness of the third oxide layer 224 less than the first oxide layer 212；Second oxygen The material for changing layer 223 is silicon oxynitride, and the thickness of the second oxide layer 223 is less than 10 angstroms；The material of the third oxide layer 224 is Silica, third oxide layer 224 with a thickness of 10 angstroms to 20 angstroms.

Since the present embodiment is forming the second oxide layer 223 and third oxide layer 224 with along in processing step, so that half The formation process of conductor device is simple, reduces technology difficulty, also, compared with prior art, the present embodiment considerably reduces The quantity of the mask plate needed takes full advantage of photoresist layer needed for forming the first well region, and takes full advantage of and to form second Photoresist layer needed for well region, to further reduce process costs.

Meanwhile in the present embodiment, the second oxide layer 223, third oxide layer 224 and positioned at the first of third region III Oxide layer 212 is not exposed in the environment of removal photoresist, so as to avoid the bad shadow of the technique introducing of removal photoresist It rings, so that the matter with higher of the first oxide layer 212 of the second oxide layer 223, third oxide layer 224 and third region III Amount, to improve the electric property of semiconductor devices.

After forming second oxide layer 223 and third oxide layer 224, the first of 233 lower section of removal third opening Barrier layer 213, so that the first oxide layer 212 of 233 lower section of third opening is exposed.In the present embodiment, carved using wet process First barrier layer 213 of 233 lower section of etching technique etching removal third opening, the etch liquids of wet-etching technology are that hot phosphoric acid is molten Liquid, wherein the mass percent of phosphoric acid is 65% to 85% in solution, and solution temperature is 120 degrees Celsius to 200 degrees Celsius.

With reference to Figure 18, on 212 surface of the first oxide layer, 224 table of 223 surface of the second oxide layer and third oxide layer Face forms grid, and full first opening 231 (referring to Figure 17) of grid filling, the second opening 232 (referring to Figure 17) and Third opening 233 (refers to Figure 17).

The problem of in order to meet the development trend of semiconductor devices miniaturization micromation, and reduce grid current leakage, this In embodiment, the grid is metal gates.

It include: in first oxide layer as the processing step in a specific embodiment, forming the metal gates 212 surfaces, 223 surface of the second oxide layer, 224 surface of third oxide layer, the first 231 sidewall surfaces of opening, the second 232 sides of opening Wall surface and third 233 sidewall surfaces of opening form high-k gate dielectric layer 132；It is formed on 132 surface of high-k gate dielectric layer Metal gate electrode layer 133, and full the 231, second opening 232 of first opening of the filling of the metal gate electrode layer 133 and third opening 233；Removal is higher than the high-k gate dielectric layer 132 and metal gate electrode layer 133 at 220 top of interlayer dielectric layer, so that metal gate electrode Layer 133 with flushed at the top of interlayer dielectric layer 220, acquisition grid.

The material of the high-k gate dielectric layer 132 is the material for the relative dielectric constant that relative dielectric constant is greater than silica, That is, the relative dielectric constant of the material of high-k gate dielectric layer 132 is greater than 3.9.The material of the high-k gate dielectric layer 132 is HfO₂、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO₂Or Al₂O₃。

In the present embodiment, the material of the high-k gate dielectric layer 132 is HfO₂, the HfO₂Formation process be atomic layer deposition Product, the high-k gate dielectric layer 132 with a thickness of 5 angstroms to 30 angstroms.

The material of the metal gate electrode layer 133 be Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN or WSi.

The first gate dielectric layer of first area I is situated between by the second oxide layer 223, the high k grid positioned at 223 surface of the second oxide layer Matter layer 132 collectively constitutes.The second gate dielectric layer of second area II by third oxide layer 224, be located at 224 surface of third oxide layer High-k gate dielectric layer 132 collectively constitute.The third gate dielectric layer of third region III by the first oxide layer 212, be located at the first oxygen The high-k gate dielectric layer 132 for changing 212 surface of layer collectively constitutes.

The relative dielectric constant of silica material is k, the i.e. phase of 224 material of third oxide layer, 212 material of the first oxide layer It is k to dielectric constant.

For the I of first area, the second oxide layer 223 with a thickness of d1 (not shown), 223 material of the second oxide layer Relative dielectric constant is k1, and k1 is greater than k, high-k gate dielectric layer 132 with a thickness of d2 (not shown), 132 material of high-k gate dielectric layer Relative dielectric constant be k2, then, the equivalent oxide thickness D1=d1k/k1+ of the first gate dielectric layer of first area I D2k/k2, k1 are greater than k.For second area II, third oxide layer 224 with a thickness of d3 (not shown), third oxide layer The relative dielectric constant of 223 materials be k, high-k gate dielectric layer 132 with a thickness of d2 (not shown), 132 material of high-k gate dielectric layer Relative dielectric constant be k2, then, the equivalent oxide thickness D2=d3+d2k/ of the second gate dielectric layer of second area II k2.For the III of third region, the first oxide layer 212 with a thickness of d4, the opposite dielectric of 212 material of the first oxide layer is normal Number is k, high-k gate dielectric layer 132 with a thickness of d2 (not shown), the relative dielectric constant of 132 material of high-k gate dielectric layer is k2, So, the equivalent oxide thickness D3=d4+d2k/k2 of the third gate dielectric layer of third region III.

Since d1 is less than d3, d3 is less than d4, and k1 is greater than k, therefore from equivalent oxide thickness D1, equivalent oxide thickness D2, equivalent oxide thickness D3 relational expression in as can be seen that for the grid of formation be metal gates for, first area I The first gate dielectric layer equivalent oxide thickness D1 less than second area II the second gate dielectric layer equivalent oxide thickness Third gate dielectric layer of the equivalent oxide thickness D2 of the second gate dielectric layer of D2, second area II less than third region III Equivalent oxide thickness D3.

In other embodiments of the present invention, the material of the grid is the polysilicon of polysilicon or doping；Form grid Processing step include: second aoxidize layer surface, third oxidation layer surface and first oxidation layer surface formed polysilicon layer, and The polysilicon layer filling full first is open, the second opening and third opening, the polysilicon layer are also covered in interlayer dielectric layer Surface；Removal is higher than the polysilicon layer of interlayer dielectric layer top surface, forms grid, the top of the grid and interlayer dielectric layer Top flushes.

Fig. 6 to Figure 10, Figure 19 to Figure 24 be the structure of semiconductor devices forming process that further embodiment of this invention provides Schematic diagram.

The present embodiment, which uses, to be initially formed high-k gate dielectric layer, forms metal gates (high k first metal gate afterwards Last mode) forms semiconductor devices.

With reference to Fig. 6 to Figure 10, the substrate 200 including first area I, second area II and third region is provided；Successively exist 200 surface of substrate formed the first oxidation film 202, positioned at 202 surface of the first oxidation film the first barrier film 203, be located at the The intermediate coat 204 on one barrier film, 203 surface and the second barrier film 205 positioned at 204 surface of intermediate coat；In secondth area 205 surface of the second barrier film of domain II and third region III forms the first photoresist layer 206；With first photoresist layer 206 For exposure mask, ion implanting is carried out to the substrate 200 of first area I, forms the first well region (not in the substrate 200 of first area I Diagram)；It is exposure mask with first photoresist layer 206, the second barrier film 205, the intermediate coat 204 of etching removal first area I And first barrier film 203, expose 202 surface of the first oxidation film of first area I；In the first oxygen of the first area I Change 202 surface of layer, 205 surface of the second barrier film of second area II forms the second photoresist layer 207, second photoresist layer 207 expose 205 surface of the second barrier film of second area II；It is exposure mask with second photoresist layer 207, to second area The substrate 200 of II carries out ion implanting, and the second well region (not shown) is formed in the substrate 200 of second area II；With described Two photoresist layers 207 are exposure mask, the second barrier film 205 of etching removal second area II.

The material of first barrier film 203 is silicon nitride, and the material of the intermediate coat 204 is silica, described second The material of barrier film 205 is silicon nitride.

In the present embodiment, after the second barrier film 205 of etching removal second area II, also etching removes second area The intermediate coat 204 of II.Then, it is removed photoresist using wet process or cineration technics removes second photoresist layer 207.

With reference to Figure 19, the first oxidation film 202 of etching removal first area I exposes 200 table of substrate of first area I Face.

Using dry etching or wet-etching technology, the first oxidation film 202 of etching removal first area I.

202 surface of the first oxidation film of second area II is formed with the first barrier film 203, and first barrier film 203 rises To the effect of the first oxidation film 202 of protection second area II, the first oxidation film 202 of second area II is prevented to be etched It removes.The second barrier film 205 is formed with above the first oxidation film 202 of third region III, second barrier film 205 plays guarantor The effect for protecting the first oxidation film 202 of third region III prevents the first oxidation film 202 of third region III to be etched removal.

Therefore, exposure mask needed for the first oxidation film 202 in the present embodiment without being additionally formed etching removal first area I Version improves production efficiency to save production cost.

With reference to Figure 20, processing 322 is doped to the substrate 200 of the first area I, reduces oxidation technology oxidation first The oxidation rate of region I substrate 200.

202 surface of the first oxidation film of second area II is formed with the first barrier film 203, and first barrier film 203 hinders The Doped ions of gear doping treatment 322 enter in the substrate 200 of second area II.The second resistance is formed with above the III of third region Film 205 is kept off, second barrier film 205 stops the Doped ions of doping treatment 322 to enter in the substrate 200 of third region III. Therefore, it without mask plate needed for being additionally formed doping treatment 322 in the present embodiment, to be further reduced processing step, saves About production cost.

In the present embodiment, the Doped ions of the doping treatment 322 are Nitrogen ion.Technique ginseng in relation to doping treatment 322 Number can refer to the explanation of previous embodiment, and details are not described herein.

With reference to Figure 21, the first barrier film 203 and the first oxidation film 202 of the second area II are removed, exposes Two region II substrates, 200 surface；First area I substrate 200, second area II substrate 200 are aoxidized using oxidation technology Processing, in first area, 200 surface of I substrate forms the second oxidation film 302, while being formed on 200 surface of second area II substrate Third oxidation film 303, and the thickness of the second oxidation film 302 is less than the thickness of third oxidation film 303.

In the present embodiment, the thickness of the thickness of the third oxidation film 303 less than the first oxidation film 202.

200 surface of second area II substrate is exposed, and does standard to carry out oxidation processes to second area II substrate 200 It is standby.In the present embodiment, in the first barrier film 203 of etching removal second area II, the second barrier film of third region III Be etched 205 (referring to Figure 20) removal；In the first oxidation film 202 of etching removal second area II, in the III of third region Between film 204 (refer to Figure 20) be etched removal.Simultaneously as 202 surface of the first oxidation film of third region III is formed with first Barrier film 203, first barrier film 203 can play the role of protecting the first oxidation film 202 of third region III, prevent The first oxidation film 202 of third region III is etched.

In the present embodiment, the oxidation processes are carried out using thermal oxidation technology.Due to being mixed in the substrate 200 of first area I It is miscellaneous to have Nitrogen ion, and undoped with Nitrogen ion in the substrate 200 of second area II, therefore oxidation technology aoxidizes first area I substrate 200 oxidation rate is less than the oxidation rate of oxidation technology oxidation second area II substrate 200, so that the second oxidation film 302 Thickness is less than the thickness of third oxidation film 303.

Technological parameter in relation to thermal oxidation technology can refer to the explanation of previous embodiment, and details are not described herein.

In the present embodiment, the material of first oxidation film 202 is silica, first oxidation film 202 with a thickness of 20 angstroms to 30 angstroms；The material of second oxidation film 302 is silicon oxynitride, and the thickness of the second oxidation film 302 is less than 10 angstroms；It is described The material of third oxidation film 303 be silica, third oxidation film 303 with a thickness of 10 angstroms to 20 angstroms.

Since the present embodiment is forming the second oxidation film 302 and third oxidation film 303 with along in processing step, so that half The formation process of conductor device is simple, reduces technology difficulty, also, compared with prior art, the present embodiment considerably reduces The quantity of the mask plate needed takes full advantage of photoresist layer needed for forming the first well region, and takes full advantage of and to form second Photoresist layer needed for well region, to further reduce process costs.

Meanwhile in the present embodiment, the first oxidation of the second oxidation film 302, third oxidation film 303 and third region III Film 202 is not exposed in the environment of removal photoresist layer, so as to avoid the bad shadow of technique bring of removal photoresist layer It rings, so that the matter with higher of the first oxidation film 202 of the second oxidation film 302, third oxidation film 303 and third region III Amount, to improve the electric property of semiconductor devices.

After forming second oxidation film 302 and third oxidation film 303, the first barrier film of third region II is removed 203, so that the first oxidation film 202 of third region III is exposed.In the present embodiment, etched using wet-etching technology The first barrier film 203 of third region III is removed, the etch liquids of wet-etching technology are hot phosphoric acid solution, wherein in solution The mass percent of phosphoric acid is 65% to 85%, and solution temperature is 120 degrees Celsius to 200 degrees Celsius.

With reference to Figure 22,302 surface of the second oxidation film, 303 surface of third oxidation film, third region III first 202 surface of oxidation film forms high-k gate dielectric film 332；Pseudo- grid film 308 is formed on 332 surface of high-k gate dielectric film.

The material of the high-k gate dielectric film 332 is high K medium material, wherein high K medium material refers to opposite dielectric Constant is greater than the material of the relative dielectric constant of silica.The material of the puppet grid film 308 is polysilicon, amorphous silicon or amorphous Carbon.

With reference to Figure 23, the pseudo- grid film 308 and the second oxidation film 302 of graphical first area I, in first area I substrate 200 surfaces form the first pseudo- grid structure；The pseudo- grid film 308 and third oxidation film 303 of graphical second area II, in the secondth area II substrate 200 surface in domain forms the second pseudo- grid structure；The pseudo- grid film 308 and the first oxidation film of graphical third region III 202, in third region, 200 surface of III substrate forms third puppet grid structure.

First pseudo- grid structure includes: positioned at second oxide layer 312 on 200 surface of first area I substrate, positioned at the second oxidation The high-k gate dielectric layer 342 on 312 surface of layer, the pseudo- grid layer 318 positioned at 342 surface of high-k gate dielectric layer.The thickness of second oxide layer 312 Degree is less than the thickness of third oxide layer 313, and the material of the second oxide layer 312 is silicon oxynitride, and thickness is less than 10 angstroms.

Second pseudo- grid structure includes: positioned at the third oxide layer 313 on 200 surface of second area II substrate, positioned at third oxygen The high-k gate dielectric layer 342 on change 313 surface of layer, the pseudo- grid layer 318 positioned at 342 surface of high-k gate dielectric layer.Third oxide layer 313 Thickness is less than the thickness of the first oxide layer 212, and the material of third oxide layer 313 is silica, with a thickness of 10 angstroms to 20 angstroms.

Third puppet grid structure includes: positioned at first oxide layer 212 on 200 surface of third region III substrate, positioned at the first oxygen The high-k gate dielectric layer 342 on change 212 surface of layer, the pseudo- grid layer 318 positioned at 342 surface of high-k gate dielectric layer.First oxide layer 212 Material is silica, with a thickness of 20 angstroms to 30 angstroms.

After forming the described first pseudo- grid structure, formed in the first area I substrate 200 of the first pseudo- grid structure two sides First source-drain area；After forming the described second pseudo- grid structure, in the second area II substrate 200 of the second pseudo- grid structure two sides Form the second source-drain area；Third region III substrate after forming the third puppet grid structure, in third puppet grid structure two sides Third source-drain area is formed in 200.

With reference to Figure 24, interlayer dielectric layer 320, the covering of interlayer dielectric layer 320 first are formed on 200 surface of substrate Pseudo- grid structure sidewall surfaces, the second pseudo- grid structure sidewall surfaces and third puppet grid structure sidewall surfaces, and the inter-level dielectric 320 top of layer is flushed at the top of the first pseudo- grid structure top, the second pseudo- grid structure and at the top of third puppet grid structure；Removal first The pseudo- grid layer 318 (referring to Figure 23) of region I, second area II and third region III；I, second area II and in first area 342 surface of high-k gate dielectric layer of three region III forms metal gate electrode layer 343, and 343 top of the metal gate electrode layer with It is flushed at the top of interlayer dielectric layer 320.

Material in relation to metal gate electrode layer 343 can refer to the explanation of previous embodiment, and details are not described herein.

In the present embodiment, the first gate dielectric layer of first area I by the second oxide layer 312, be located at 312 table of the second oxide layer The high-k gate dielectric layer 342 in face collectively constitutes.The second gate dielectric layer of second area II by third oxide layer 313, be located at third oxygen The high-k gate dielectric layer 342 for changing 313 surface of layer collectively constitutes.The third gate dielectric layer of third region III by the first oxide layer 212, High-k gate dielectric layer 342 positioned at 212 surface of the first oxide layer collectively constitutes.By the analysis of previous embodiment it is found that the present embodiment In, equivalent oxide thickness of the equivalent oxide thickness less than the second gate dielectric layer of the first gate dielectric layer, the second gate dielectric layer Equivalent oxide thickness be less than third gate dielectric layer equivalent oxide thickness so that first area I, second area II Different operating voltages is able to bear with the third region III field-effect tube formed.

Also, in the present embodiment, the first oxide layer 212, the second oxide layer 312 and the third oxide layer 313 of formation are not It is exposed in the process environments of removal photoresist layer, so that the first oxide layer 212, the second oxide layer 312 and third oxidation 313 quality with higher of layer.Also, the light of formation when making full use of to form the first well region, the second well region in the present embodiment Photoresist layer, and by the first barrier film of setting, intermediate coat and the second barrier film, so that the present embodiment is without being additionally formed photoresist Layer, to save production cost, improves the production efficiency of semiconductor devices.

In other embodiments, the not formed high-k gate dielectric film before forming pseudo- grid film, etching remove pseudo- grid layer it Afterwards, high-k gate dielectric layer is formed, comprising the following steps: aoxidize film surface, third oxidation film surface and third region second First oxidation film surface forms pseudo- grid film；The graphical pseudo- grid film, the second oxidation film, third oxidation film, third region the One oxidation film, in first area, substrate surface forms the second oxide layer and pseudo- grid layer, forms the in second area substrate surface Three oxide layers and pseudo- grid layer form the first oxide layer and pseudo- grid layer on third area substrate surface, wherein the second oxide layer Thickness be less than the thickness of third oxide layer, the thickness of the thickness of third oxide layer less than the first oxide layer；In the substrate table Face forms interlayer dielectric layer, and flushes at the top of the interlayer dielectric layer at the top of pseudo- grid layer；The etching removal pseudo- grid layer；Institute It states the second oxidation layer surface, third oxidation layer surface, the first oxidation layer surface and forms high-k gate dielectric layer；In the high-k gate dielectric Layer surface forms metal gate electrode layer, and flushes at the top of the metal gate electrode layer with interlayer dielectric layer top

Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims

1. a kind of forming method of semiconductor devices characterized by comprising

Substrate including first area, second area and third region is provided, the substrate surface is formed with the first oxidation film, In, the first oxidation film surface in the second area and third region is formed with the first barrier film, and the of the third region The second barrier film is formed on one barrier film；

Stop the of film surface and third region in the first oxidation film surface of the first area, the first of second area Two blocking film surfaces form pseudo- grid film；

The graphical pseudo- grid film, the second barrier film, the first barrier film and the first oxidation film, the substrate surface in first area The first oxide layer and pseudo- grid layer are formed, forms the first oxide layer, the first barrier layer and puppet in the substrate surface of second area Grid layer, the substrate surface in third region form the first oxide layer, the first barrier layer, the second barrier layer and pseudo- grid layer；

Interlayer dielectric layer is formed in the substrate surface, and is flushed at the top of interlayer dielectric layer at the top of pseudo- grid layer；

Etching removes the pseudo- grid layer of the first area, second area and third region；

Etching removes the first oxide layer of the first area, exposes first area section substrate surface；

Processing is doped to the first area substrate exposed, reduces the oxidation of oxidation technology oxidation first area substrate Rate；

Etching removes the first barrier layer and the first oxide layer of the second area；

Oxidation processes are carried out to the first area substrate exposed, second area substrate using oxidation technology, in the firstth area Domain substrate surface forms the second oxide layer, while forming third oxide layer, and second oxidation in second area substrate surface The thickness of layer is less than the thickness of third oxide layer, the thickness of the thickness of the third oxide layer less than the first oxide layer.

2. the forming method of semiconductor devices as described in claim 1, which is characterized in that first barrier film and the second resistance The material for keeping off film is identical；It is also formed with intermediate coat between first barrier film and the second barrier film in the third region, and described The material of intermediate coat is different from the material of the first barrier film；Between first barrier layer and the second barrier layer in the third region also It is formed with middle layer.

3. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that remove the second area in etching The first barrier layer and while the first oxide layer, second barrier layer in third region and middle layer are etched removal；Carry out After the oxidation technology, first barrier layer in etching removal third region.

4. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that formed first barrier film, in Between the processing step of film and the second barrier film include: successively first oxidation film surface formed the first barrier film, be located at first Stop the intermediate coat of film surface and the second barrier film positioned at intermediate film surface；In the second area and third region The first photoresist layer is formed on substrate；Using first photoresist layer as exposure mask, the second barrier film of etching removal first area, Intermediate coat and the first barrier film；The second photoresist layer is formed on the substrate in the first area and third region；With described Second photoresist layer is exposure mask, the second barrier film of etching removal second area.

5. the forming method of semiconductor devices as claimed in claim 4, which is characterized in that remove the first area in etching The second barrier film, before or after intermediate coat and the first barrier film, further comprising the steps of: with first photoresist layer is to cover Film carries out ion implanting to the substrate of the first area, forms the first well region in the substrate of first area；It is removed in etching Before or after second barrier film of second area, further comprise the steps of: using second photoresist layer as exposure mask, to described second The substrate in region carries out ion implanting, and the second well region is formed in the substrate of second area.

6. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material of first barrier film is SiN、SiON、SiBN、SiCN、SiOBN、SiOCN、HfO₂、HfZrO₂, HfSiO, HfSiON, TiN or TaN；Described second stops The material of film is SiN, SiON, SiBN, SiCN, SiOBN, SiOCN, HfO₂、HfZrO₂, HfSiO, HfSiON, TiN or TaN.

7. the forming method of semiconductor devices as described in claim 1, which is characterized in that the Doped ions of the doping treatment For Nitrogen ion.

8. the forming method of semiconductor devices as claimed in claim 7, which is characterized in that the technological parameter of the doping treatment Are as follows: N₂Flow is 50sccm to 500sccm, and chamber pressure is 10 millitorrs to 30 millitorrs, and power is 40 watts to 400 watts.

9. the forming method of semiconductor devices as claimed in claim 7, which is characterized in that the material of second oxide layer is Silicon oxynitride；The material of the third oxide layer is silica；The material of first oxide layer is silica.

10. the forming method of semiconductor devices as claimed in claim 9, which is characterized in that the thickness of second oxide layer Less than 10 angstroms；The third oxide layer with a thickness of 10 angstroms to 20 angstroms；First oxide layer with a thickness of 20 angstroms to 30 angstroms.

11. the forming method of semiconductor devices as described in claim 1, which is characterized in that first barrier film and second The material of barrier film is different；Second barrier film in the third region is located at first and stops film surface.

12. the forming method of semiconductor devices as claimed in claim 11, which is characterized in that carry out the oxidation technology it Afterwards, etching removes second barrier layer and the first barrier layer in the third region.

13. the forming method of semiconductor devices as described in claim 1, which is characterized in that further comprise the steps of: described second The the first oxidation layer surface for aoxidizing layer surface, third oxidation layer surface and third region forms high-k gate dielectric layer；In high k grid Dielectric layer surface forms metal gate electrode layer, and flushes at the top of the metal gate electrode layer with interlayer dielectric layer top.

14. a kind of forming method of semiconductor devices characterized by comprising

Etching removes the first oxidation film of the first area, exposes first area substrate surface；

Etching removes the first barrier film and the first oxidation film of the second area；

Oxidation processes are carried out to the first area substrate, second area substrate using oxidation technology, in first area substrate table Face forms the second oxidation film, while forming third oxidation film, and the thickness of second oxidation film in second area substrate surface Less than the thickness of third oxidation film, the thickness of the thickness of the third oxidation film less than the first oxidation film；

Etching removes second barrier film and the first barrier film in the third region.

15. the forming method of semiconductor devices as claimed in claim 14, which is characterized in that further comprise the steps of: described Titanium dioxide film surface, third oxidation film surface and the first oxidation film surface in third region form high-k gate dielectric film；Described High-k gate dielectric film surface forms pseudo- grid film；The graphical pseudo- grid film, high-k gate dielectric film, the second oxidation film, third oxidation film, First oxidation film in third region, in first area, substrate surface forms the second oxide layer, high-k gate dielectric layer and pseudo- grid layer, Third oxide layer, high-k gate dielectric layer and pseudo- grid layer are formed in second area substrate surface, is formed on third area substrate surface First oxide layer, high-k gate dielectric layer and pseudo- grid layer, wherein the thickness of the second oxide layer is less than the thickness of third oxide layer, the Thickness of the thickness of three oxide layers less than the first oxide layer；Interlayer dielectric layer is formed in the substrate surface, and the interlayer is situated between It is flushed at the top of matter layer at the top of pseudo- grid layer；The etching removal pseudo- grid layer；In the first area, second area and third region High-k gate dielectric layer surface formed metal gate electrode layer, and the metal gate electrode layer at the top of with interlayer dielectric layer top flush.

16. the forming method of semiconductor devices as claimed in claim 14, which is characterized in that further comprise the steps of: described Titanium dioxide film surface, third oxidation film surface and the first oxidation film surface in third region form pseudo- grid film；It is graphical described Pseudo- grid film, the second oxidation film, third oxidation film, third region the first oxidation film, in first area substrate surface formed second Oxide layer and pseudo- grid layer form third oxide layer and pseudo- grid layer in second area substrate surface, in third area substrate table Face forms the first oxide layer and pseudo- grid layer, wherein the thickness of the second oxide layer is less than the thickness of third oxide layer, third oxidation Thickness of the thickness of layer less than the first oxide layer；Interlayer dielectric layer, and the interlayer dielectric layer top are formed in the substrate surface It is flushed at the top of portion and pseudo- grid layer；The etching removal pseudo- grid layer；In the second oxidation layer surface, third oxidation layer surface, the One oxidation layer surface forms high-k gate dielectric layer；Metal gate electrode layer, and the metal are formed in the high-k gate dielectric layer surface It is flushed at the top of gate electrode layer with interlayer dielectric layer top.

17. the forming method of semiconductor devices as claimed in claim 14, which is characterized in that first barrier film and second The material of barrier film is identical；Intermediate coat, and institute are also formed between first barrier film and the second barrier film in the third region The material for stating intermediate coat is different from the material of the first barrier film.

18. the forming method of semiconductor devices as claimed in claim 17, which is characterized in that formation first barrier film, The processing step of intermediate coat and the second barrier film includes: successively to form the first barrier film in the first oxidation film surface, be located at the One stops the intermediate coat of film surface and the second barrier film positioned at intermediate film surface；In the second area and third region Substrate on form the first photoresist layer；Using first photoresist layer as exposure mask, the second of etching removal first area stops Film, intermediate coat and the first barrier film；The second photoresist layer is formed on the substrate in the first area and third region；With institute Stating the second photoresist layer is exposure mask, the second barrier film of etching removal second area.

19. the forming method of semiconductor devices as claimed in claim 18, which is characterized in that remove firstth area in etching Before or after second barrier film in domain, intermediate coat and the first barrier film, further comprises the steps of: and be with first photoresist layer Exposure mask carries out ion implanting to the substrate of the first area, forms the first well region in the substrate of first area；It is gone in etching Before or after the second barrier film of second area, further comprise the steps of: using second photoresist layer as exposure mask, to described The substrate in two regions carries out ion implanting, and the second well region is formed in the substrate of second area.

20. the forming method of semiconductor devices as claimed in claim 14, which is characterized in that the doping of the doping treatment from Son is Nitrogen ion；The material of first oxidation film is silica；The material of second oxidation film is silicon oxynitride；Described The material of three oxidation films is silica.