CN104282333A - Data inversion based storage method and memory - Google Patents
Data inversion based storage method and memory Download PDFInfo
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- CN104282333A CN104282333A CN201310293503.8A CN201310293503A CN104282333A CN 104282333 A CN104282333 A CN 104282333A CN 201310293503 A CN201310293503 A CN 201310293503A CN 104282333 A CN104282333 A CN 104282333A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5647—Multilevel memory with bit inversion arrangement
Abstract
The embodiment of the invention provides a data inversion based storage method and device. The storage device comprises a NOT gate array and a PCM (Phase Change Memory), wherein the NOT gate array comprises NOT gates arranged on data lines, and is used for inversing each numerical value in initial data to obtain target data of the initial data, the target data is input in the PCM, and the PCM is used for storing the target data. The method comprises the steps of inversing each numerical value in the initial data through the NOT gate array to obtain the target data of the initial data, and inputting the target data into the PCM for storing the target data. According to the embodiment, when stored in the PCM, data to be stored is directly inverted to be stored in the PCM, the problem of high energy consumption expense in the prior art is solved, and the data storage efficiency can be improved.
Description
Technical field
The present invention relates to computer technology, particularly relate to a kind of storage means based on data reversal and storer.
Background technology
In the decades in past, memory system is made up of dynamic RAM (Dynamic Random Access Memory, referred to as DRAM).But DRAM exists the higher problem of energy consumption, in order to reduce the energy consumption of memory system, available non-volatile memory (Non-Volatile Memory, referred to as NVM) substitutes DRAM and forms memory system.Wherein, phase transition storage (Phase ChangeMemory, referred to as PCM) is a kind of NVM, can substitute DRAM and form memory system.
At present, when writing data to PCM, from the storage unit that data to be stored will write, the raw data originally stored in this storage unit is read.Each numerical value in data to be stored and each numerical value in raw data are compared.Compared with raw data, if there is the data bit exceeding half to change in data to be stored, then data to be stored reversed, be written in storage unit, and be 1 by this data markers to be stored.Otherwise data to be stored are directly write in storage unit, and this data markers to be stored is designated as 0.When reading data from PCM, if data to be read be labeled as 1, reading these data after these data are reversed.If data to be read be labeled as 0, do not need to read data reverse.
Above-mentioned PCM date storage method, needs to read raw data, and needs data to be stored and raw data to compare before write data, there is the problem that energy consumption expense is comparatively large and data storage efficiency is lower.
Summary of the invention
The embodiment of the present invention provides a kind of storage means based on data reversal and storer, in order to reduce energy consumption when storing data in PCM, and improves the efficiency of data storage.
Embodiment of the present invention first aspect provides a kind of storer, comprising: non-gate array and PCM; Described non-gate array comprises the not gate be arranged on every bar data line;
Described non-gate array, for reversing to each numerical value in primary data, obtains the target data of described primary data, described target data is input to described PCM;
Described PCM, for storing described target data.
In the first possible implementation of first aspect, described PCM, also for receiving reading command, reading described first data corresponding with described reading command, described first data is input to described non-gate array;
Described non-gate array, also for reversing to each numerical value in described first data, obtains the described primary data corresponding with described first data.
In conjunction with the first possible implementation of first aspect or first aspect, in the implementation that the second of first aspect is possible, described PCM comprises PCM line buffer and PCM storage array, described PCM line buffer is connected with external unit by data bus, and described PCM line buffer is connected by bus with described PCM storage array;
Described non-gate array is arranged between described PCM line buffer and described PCM storage array.
In conjunction with the first possible implementation of first aspect or first aspect, in the third possible implementation of first aspect, described PCM, comprise PCM line buffer and PCM storage array, described PCM line buffer is connected with external unit by data bus, and described PCM line buffer is connected by bus with described PCM storage array;
Described non-gate array is arranged on described data bus.
A kind of storage means based on data reversal that embodiment of the present invention second aspect provides, comprising:
Non-gate array is reversed to each numerical value in primary data, obtains the target data of described primary data, and described target data is input to phase transition storage PCM; Wherein, described non-gate array comprises the not gate be arranged on every bar data line;
Described PCM stores described target data.
In the first possible implementation of second aspect, also comprise: described PCM receives reading command, reads first data corresponding with described reading command, described first data are input to described non-gate array;
Described non-gate array is reversed to each numerical value in described first data, obtains the described primary data corresponding with described first data.
May implementation in conjunction with the first of second aspect or second aspect, in the implementation that the second of second aspect is possible, described PCM comprises PCM line buffer and PCM storage array, described PCM line buffer is connected with external unit by data bus, described PCM line buffer is connected by data line with described PCM storage array, and described non-gate array is arranged between described PCM line buffer and described PCM storage array;
Described non-gate array is reversed to each numerical value in primary data, obtains the target data of described primary data, described target data is input to PCM and comprises:
Described primary data is input to described non-gate array by described data line by described PCM line buffer;
Each described not gate in described non-gate array reverses to the one digit number value in described primary data, obtains described target data, is input to described PCM storage array by described data line;
Described PCM stores described target data and comprises:
Described PCM storage array stores described target data.
May implementation in conjunction with the first of second aspect or second aspect, in the third possible implementation of second aspect, described non-gate array is reversed to each numerical value in described first data, obtains the described primary data corresponding with described first data and comprises:
Described first data are input to described non-gate array by described data line by described PCM storage array;
Each described not gate in described non-gate array reverses to the one digit number value in described first data, obtains the described primary data corresponding with described first data, is input to described PCM line buffer by described data line.
May implementation in conjunction with the first of second aspect or second aspect, in the 4th kind of possible implementation of second aspect, described PCM comprises PCM line buffer and PCM storage array, described PCM line buffer is connected with external unit by data bus, and described PCM line buffer is connected by bus with described PCM storage array; Described non-gate array is arranged on described data bus;
Described non-gate array is reversed to each numerical value in primary data, obtains the target data of described primary data, described target data is input to PCM and comprises:
Described primary data is input to described non-gate array by described data bus by described external unit;
Each described not gate in described non-gate array reverses to the one digit number value in described primary data, obtains described target data, by described data bus, described target data is input to described PCM line buffer;
Described target data is input to described PCM storage array by described data line by described PCM line buffer;
Described PCM stores described target data and comprises:
Described PCM storage array stores described target data.
May implementation in conjunction with the first of second aspect or second aspect, in the 5th kind of possible implementation of second aspect, described non-gate array is reversed to each numerical value in described first data, obtains the described primary data corresponding with described first data and comprises:
Described first data are input to described non-gate array by described data bus by described PCM line buffer;
Each described not gate in described non-gate array reverses to the one digit number value in described first data, obtains the described primary data that described first data are corresponding, and is exported by described data bus.
A kind of storage means based on data reversal that the embodiment of the present invention provides and storer, before store data in PCM, by non-gate array, each numerical value in primary data is reversed, obtain the target data of described primary data, target data be input in PCM, PCM stores target data.When storing data by the embodiment of the present invention in PCM, directly data to be stored are reversed, data after reversion are stored in PCM, do not need to read raw data from PCM, and by operations such as data to be stored and raw data compare, thus overcome in prior art and there is the higher problem of energy consumption, and improve the efficiency that data store.
Accompanying drawing explanation
The structural representation of a kind of storer that Fig. 1 provides for the embodiment of the present invention;
The structural representation of the another kind of storer that Fig. 2 provides for the embodiment of the present invention;
The structural representation of the another kind of storer that Fig. 3 provides for the embodiment of the present invention;
The schematic diagram of a kind of storage means based on data reversal that Fig. 4 provides for the embodiment of the present invention;
The another kind that Fig. 5 provides for the embodiment of the present invention is based on the schematic diagram of the storage means of data reversal;
The another kind that Fig. 6 provides for the embodiment of the present invention is based on the schematic diagram of the storage means of data reversal;
The schematic diagram of a kind of method for reading data based on data reversal that Fig. 7 provides for the embodiment of the present invention.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
When writing " 0 " in PCM, needing to apply high voltage to storage unit, making the state of this storage unit become amorphous state.Under being in amorphous state situation, the resistance of storage unit is large, for representing numerical value " 0 ".To in PCM during one writing, need to apply a low-voltage to storage unit, make this storage unit become crystalline state.Under being in crystalline state situation, the resistance of storage unit is little, for representing numerical value " 1 ".In the mode that the data of above-mentioned PCM write, the energy consumption writing " 0 " is greater than the energy consumption of one writing.
In practical application, the frequency that numerical value " 0 " uses, apparently higher than the frequency of numerical value " 1 ", and is greater than the energy consumption of one writing to the energy consumption that PCM writes " 0 ", therefore, data is write direct in PCM, can cause energy dissipation.
The structural representation of a kind of storer that Fig. 1 provides for the embodiment of the present invention.As shown in Figure 1, this storer comprises: non-gate array 1 and PCM2.
In the present embodiment, non-gate array 1 comprises and is arranged on not gate on every bar data line.Non-gate array 1, for reversing to each numerical value of primary data, obtains the target data of primary data, target data is input in PCM2.PCM2 is for storing target data.
In the present embodiment, non-gate array 1 gets primary data to be stored from data line, every bar data is provided with a not gate.Each not gate in non-gate array 1 reverses to the one digit number value in primary data, to obtain target data corresponding to this primary data.In the present embodiment, reversion is and " 0 " is taken as " 1 ", " 1 " is taken as " 0 ".
After non-gate array 1 gets target data, be input in PCM2 by data line by target data, PCM2 stores target data.
Illustrate, primary data is 00110101, and this primary data is reversed by non-gate array 1, obtains target data 11001010, is input in PCM32, and PCM2 stores target data 11001010.
The storer that the present embodiment provides, before storing data to PCM, reversed to each numerical value in primary data by non-gate array, obtain the target data of described primary data, target data be input in PCM, PCM stores target data.The embodiment of the present invention when storing data in PCM, directly primary data is reversed, then the target data after reversion is stored in PCM, do not need to read raw data from PCM, and by operations such as primary data and raw data compare, thus overcome in prior art and there is the higher problem of energy consumption, and improve the efficiency that data store.Further, not needing the target data for storing to make marks, storage resources and energy consumption can be saved.
And numerical value " 0 " is higher than the frequency of utilization of numerical value " 1 " in actual applications, because the energy consumption writing " 0 " in PCM is greater than the energy consumption of one writing, the storer that the present embodiment provides, can save energy consumption when writing data.
Further, the PCM2 in the storer that the present embodiment provides can also receive reading command, then reads first data corresponding with reading command.In the present embodiment, the first data that PCM2 reads are the target data that primary data obtains after non-gate array 1 is reversed, and are not primary data.Therefore, when reading the first data, the first data are input in non-gate array 1 by PCM2.Non-gate array 1 is reversed to each numerical value in the first data, obtains the primary data corresponding with the first data.
Illustrate, when storing data to PCM2, primary data is 00110101, and non-gate array 1 pair of primary data is reversed, and obtains the target data 11001010 of this primary data, target data 11001010 is input in PCM2.When needs reading 00110101, a reading command is sent to PCM2, according to this reading command to reading the first data 11001010, first data 11001010 are input to non-gate array 1 by PCM2, through non-gate array 1, negate is carried out to the first data 11001010, obtain primary data 00110101.
The another kind of memory construction schematic diagram that Fig. 2 provides for the embodiment of the present invention.As shown in Figure 2, this storer comprises non-gate array 1 and PCM2.Non-gate array 1 comprises the not gate arranged on every bar data line.PCM2 comprises PCM row buffer 21 and PCM storage array 22.Wherein, PCM row buffer 21 is connected with external unit by data bus, and PCM line buffer is also connected with PCM memory array 22 by data line.In the present embodiment, non-gate array 1 is arranged between PCM line buffer 21 and PCM storage array 22, that is, is arranged on the not gate on every bar data line between PCM line buffer 21 and PCM storage array 22, forms non-gate array 1.
When storing data to PCM2, PCM line buffer 21 receives primary data data line transmitting come.Wherein, PCM line buffer 21 is connected with the data line identical with primary data figure place, each data line transmits the one digit number value in primary data.Primary data is input to non-gate array 1 by data line by PCM line buffer 21.Particularly, each numerical value in primary data is input in the not gate that corresponding data line is arranged by PCM line buffer 21.The one digit number value not gate pair data line be connected with this not gate transmitted in the primary data come carries out negate.Non-gate array 1 is after obtaining the target data of primary data, and be input in PCM storage array 22 by data line by target data, PCM storage array 22 stores target data.
When reading data from PCM storage array 22, PCM storage array 22 receives reading command, reads first data corresponding with reading command according to reading command.First data are input in non-gate array 1 by data line by PCM storage array 22.Particularly, each numerical value in the first data is input to through data line in the not gate be connected with this data line by PCM storage array 22, and not gate reverses to the first data a numerical value.After non-gate array 1 is reversed to the first data, obtain the primary data that the first data are corresponding, then primary data is passed through in PCM line buffer 21.
The another kind of memory construction schematic diagram that Fig. 3 provides for the embodiment of the present invention.As shown in Figure 3, this storer comprises non-gate array 1 and PCM2.Non-gate array 1 comprises the not gate arranged on every bar data line.PCM2 comprises PCM row buffer 21 and PCM storage array 22.Wherein, PCM row buffer 21 is connected with external unit by data bus, and PCM line buffer 21 is also connected with PCM memory array 22 by data line.In the present embodiment, non-gate array 1 is arranged on the data bus.Particularly, the data bus between external unit and PCM line buffer 21 is arranged row's not gate, the number of not gate is identical with the number of primary data.Such as, primary data is 8, be then set up in parallel 8 not gates on the data bus, the corresponding not gate of each numerical value.Be arranged on the not gate on data bus between external unit and PCM line buffer 21, form non-gate array 1.
When storing data to PCM storage array 22, primary data is input in non-gate array 1 by data bus by external unit.The one digit number value each not gate pair data bus be connected with this not gate in non-gate array 1 transmitted in the primary data come carries out negate, obtains the target data of primary data.Non-gate array 1 is after obtaining target data, by data bus, target data is input in PCM line buffer 21, target data is input in PCM storage array 22 by data line by PCM line buffer 21 by target data, and PCM storage array 22 stores this target data.
When reading data from PCM storage array 22, PCM storage array 22 receives reading command, read first data corresponding with this reading command, the first data be input in PCM line buffer 21, the first data are sent in non-gate array 1 by PCM line buffer 21.In non-gate array 1, each not gate reverses to one digit number value in these not gate first data of input.Non-gate array 1, by after the first data reversal, is obtained the primary data of the first data, and is outputted in external unit by data bus.
A kind of storage means schematic diagram based on data reversal that Fig. 4 provides for the embodiment of the present invention.As shown in Figure 4, the method comprises the following steps:
401, non-gate array is reversed to each numerical value in primary data, obtains the target data of described primary data, and described target data is input to PCM; Wherein, described non-gate array comprises the not gate be arranged on every bar data line.
In PCM, arrange a non-gate array, non-gate array comprises the not gate be arranged on every bar data line.Primary data to be stored is input to non-gate array by data line, and input the one digit number value in this primary data in non-gate array in each not gate, non-gate array is reversed to each numerical value in primary data, obtains the target data of this primary data.In the present embodiment, reversion is and " 0 " is taken as " 1 ", " 1 " is taken as " 0 ".
402, described PCM stores described target data.
After getting target data, target data is input in PCM by data line by non-gate array, and PCM stores this target data.
Illustrate, primary data is 00110101, and a data in this primary data of non-goalkeeper in non-gate array on every bar data line is reversed, and obtains the target data 11001010 of this primary data, target data 11001010 is stored in PCM.
The storage means based on data reversal that the present embodiment provides, before PCM storing initial data, is reversed to each numerical value in primary data by non-gate array, obtains the target data of primary data, then target data stored in PCM.By the storage means based on data reversal that the embodiment of the present invention provides, directly primary data is reversed, do not need to read raw data from PCM, and by operations such as primary data and raw data compare, thus overcome in prior art and there is the higher problem of energy consumption, and improve the efficiency that data store.Further, not needing the target data for storing to make marks, storage resources and energy consumption can be saved.
And numerical value " 0 " is higher than the frequency of utilization of numerical value " 1 " in actual applications, because the energy consumption writing " 0 " in PCM is greater than the energy consumption of one writing, the storage means provided by the present embodiment, can save energy consumption when writing data to PCM.
In reality, PCM comprises PCM line buffer and PCM storage array.External unit is connected with PCM line buffer by data bus, and PCM line buffer is connected by data line with PCM storage array.
A kind of optional method to set up of non-gate array is: non-gate array is arranged between PCM line buffer and PCM storage array.Fig. 5 provides the another kind of schematic diagram based on the storage means of data reversal for the embodiment of the present invention.As shown in Figure 5, the method comprises the following steps:
501, primary data is input to non-gate array by data line by PCM line buffer.
502, each not gate in non-gate array reverses to the one digit number value in primary data, obtains target data, is input to PCM storage array by data line.
503, PCM storage array stores target data.
The another kind of non-gate array alternatively method to set up is: gate array is arranged on the data bus between external unit and PCM line buffer.Fig. 6 provides the another kind of schematic diagram based on the storage means of data reversal for the embodiment of the present invention.As shown in Figure 6, the method comprises the following steps:
601, primary data is input to non-gate array by data bus by external unit.
602, each not gate in non-gate array reverses to the one digit number value in primary data, obtains target data, by data bus, target data is input to PCM line buffer.
603, target data is input to PCM storage array by data line by PCM line buffer.
604, PCM storage array stores target data.
The schematic diagram of a kind of method for reading data based on data reversal that Fig. 7 provides for the embodiment of the present invention.Shown in Fig. 7, the method comprises the following steps:
701, PCM receives reading command.
External unit or controller, when attempting to read data from PCM, can send reading command to PCM.
702, PCM reads first data corresponding with reading command, and the first data are input to non-gate array.
First data are input in non-gate array by data line after reading the first data according to reading command by PCM.
703, non-gate array is reversed to each numerical value in the first data, obtains the primary data that the first data are corresponding.
Due to when storing data in PCM, have passed through non-gate array and data being reversed, therefore, storing in PCM is not primary data, but the target data that primary data obtains after reversion.After reading the first data in PCM, be input in non-gate array by data line.Non-gate array comprises the not gate be arranged on every bar data line.Each not gate in non-gate array carries out negate to the one digit number value in the first data, obtains the primary data that the first data are corresponding.
Illustrate, when storing data in PCM, if primary data is 00110101, a data in this primary data of non-goalkeeper on each data line is reversed, obtain the target data 11001010 of this primary data, target data 11001010 is stored in the storage array in PCM.When reading data from PCM, read the first data 11001010 from the storage array PCM, these first data are input in non-gate array by data line, and non-gate array carries out negate to the first data, obtain primary data 00110101.
In reality, PCM comprises PCM line buffer and PCM storage array.External unit is connected with PCM line buffer by data bus, and PCM line buffer is connected by data line with PCM storage array.
A kind of optional method to set up of non-gate array is: non-gate array is arranged between PCM line buffer and PCM storage array.In the present embodiment, non-gate array is reversed to each numerical value in the first data, obtain the primary data corresponding with the first data to be specially: the first data are input to non-gate array by data line by PCM storage array, each not gate in non-gate array reverses to the one digit number value in the first data, obtain the primary data corresponding with the first data, and be input to PCM line buffer by data line.
The another kind of non-gate array alternatively method to set up is: gate array is arranged on the data bus between external unit and PCM line buffer.In the present embodiment, non-gate array is reversed to each numerical value in the first data, obtain the primary data corresponding with the first data to be in particular: the first data are input to non-gate array by data bus by PCM line buffer, each not gate in non-gate array reverses to the one digit number value in the first data, obtain the primary data that the first data are corresponding, and exported by data bus.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a storer, is characterized in that, comprising: non-gate array and phase transition storage PCM; Described non-gate array comprises the not gate be arranged on every bar data line;
Described non-gate array, for reversing to each numerical value in primary data, obtains the target data of described primary data, described target data is input to described PCM;
Described PCM, for storing described target data.
2. storer according to claim 1, is characterized in that, described PCM, also for receiving reading command, reading first data corresponding to described reading command, described first data are input to described non-gate array;
Described non-gate array, also for reversing to each numerical value in described first data, obtains the described primary data corresponding with described first data.
3. storer according to claim 1 and 2, it is characterized in that, described PCM comprises PCM line buffer and PCM storage array, and described PCM line buffer is connected with external unit by data bus, and described PCM line buffer is connected by data line with described PCM storage array;
Described non-gate array is arranged between described PCM line buffer and described PCM storage array.
4. storer according to claim 1 and 2, it is characterized in that, described PCM comprises PCM line buffer and PCM storage array, and described PCM line buffer is connected with external unit by data bus, and described PCM line buffer is connected by bus with described PCM storage array;
Described non-gate array is arranged on described data bus.
5. based on a storage means for data reversal, it is characterized in that, comprising:
Non-gate array is reversed to each numerical value in primary data, obtains the target data of described primary data, and described target data is input to phase transition storage PCM; Wherein, described non-gate array comprises the not gate be arranged on every bar data line;
Described PCM stores described target data.
6. method according to claim 5, is characterized in that, also comprises: described PCM receives reading command, reads first data corresponding with described reading command, described first data are input to described non-gate array;
Described non-gate array is reversed to each numerical value in described first data, obtains the described primary data corresponding with described first data.
7. the method according to claim 5 or 6, is characterized in that, described PCM comprises PCM line buffer and PCM storage array; Described PCM line buffer is connected with external unit by data bus, and described PCM line buffer is connected by data line with described PCM storage array, and described non-gate array is arranged between described PCM line buffer and described PCM storage array;
Described non-gate array is reversed to each numerical value in primary data, obtains the target data of described primary data, described target data is input to PCM and comprises:
Described primary data is input to described non-gate array by described data line by described PCM line buffer;
Each described not gate in described non-gate array reverses to the one digit number value in described primary data, obtains described target data, is input to described PCM storage array by described data line;
Described PCM stores described target data and comprises:
Described PCM storage array stores described target data.
8. method according to claim 7, is characterized in that, described non-gate array is reversed to each numerical value in described first data, obtains the described primary data corresponding with described first data and comprises:
Described first data are input to described non-gate array by described data line by described PCM storage array;
Each described not gate in described non-gate array reverses to the one digit number value in described first data, obtains the described primary data corresponding with described first data, is input to described PCM line buffer by described data line.
9. the method according to claim 5 or 6, it is characterized in that, described PCM comprises PCM line buffer and PCM storage array, and described PCM line buffer is connected with external unit by data bus, and described PCM line buffer is connected by data line with described PCM storage array; Described non-gate array is arranged on described data bus;
Described non-gate array is reversed to each numerical value in primary data, obtains the target data of described primary data, described target data is input to PCM and comprises:
Described primary data is input to described non-gate array by described data bus by described external unit;
Each described not gate in described non-gate array reverses to the one digit number value in described primary data, obtains described target data, by described data bus, described target data is input to described PCM line buffer;
Described target data is input to described PCM storage array by described data line by described PCM line buffer;
Described PCM stores described target data and comprises:
Described PCM storage array stores described target data.
10. method according to claim 9, is characterized in that, described non-gate array is reversed to each numerical value in described first data, obtains the described primary data corresponding with described first data and comprises:
Described first data are input to described non-gate array by described data bus by described PCM line buffer;
Each described not gate in described non-gate array reverses to the one digit number value in described first data, obtains the described primary data that described first data are corresponding, and is exported by described data bus.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310293503.8A CN104282333A (en) | 2013-07-12 | 2013-07-12 | Data inversion based storage method and memory |
| PCT/CN2014/082053 WO2015003653A1 (en) | 2013-07-12 | 2014-07-11 | Storage method and memory based on data inversion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310293503.8A CN104282333A (en) | 2013-07-12 | 2013-07-12 | Data inversion based storage method and memory |
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| CN104282333A true CN104282333A (en) | 2015-01-14 |
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| CN201310293503.8A Pending CN104282333A (en) | 2013-07-12 | 2013-07-12 | Data inversion based storage method and memory |
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| CN (1) | CN104282333A (en) |
| WO (1) | WO2015003653A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106057236A (en) * | 2016-05-24 | 2016-10-26 | 华中科技大学 | Phase change memory data writing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080219047A1 (en) * | 2007-03-06 | 2008-09-11 | Electronics And Telecommunications Research Institute | Apparatus and method for writing data to phase-change memory by using power calculation and data inversion |
| US20090091968A1 (en) * | 2007-10-08 | 2009-04-09 | Stefan Dietrich | Integrated circuit including a memory having a data inversion circuit |
| CN103151072A (en) * | 2013-03-28 | 2013-06-12 | 中国科学院微电子研究所 | Method and device for writing data into phase change memory |
-
2013
- 2013-07-12 CN CN201310293503.8A patent/CN104282333A/en active Pending
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080219047A1 (en) * | 2007-03-06 | 2008-09-11 | Electronics And Telecommunications Research Institute | Apparatus and method for writing data to phase-change memory by using power calculation and data inversion |
| US20090091968A1 (en) * | 2007-10-08 | 2009-04-09 | Stefan Dietrich | Integrated circuit including a memory having a data inversion circuit |
| CN103151072A (en) * | 2013-03-28 | 2013-06-12 | 中国科学院微电子研究所 | Method and device for writing data into phase change memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106057236A (en) * | 2016-05-24 | 2016-10-26 | 华中科技大学 | Phase change memory data writing method |
| CN106057236B (en) * | 2016-05-24 | 2018-10-16 | 华中科技大学 | A kind of phase transition storage method for writing data |
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| WO2015003653A1 (en) | 2015-01-15 |
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