WO2015003653A1 - Storage method and memory based on data inversion - Google Patents

Storage method and memory based on data inversion Download PDF

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Publication number
WO2015003653A1
WO2015003653A1 PCT/CN2014/082053 CN2014082053W WO2015003653A1 WO 2015003653 A1 WO2015003653 A1 WO 2015003653A1 CN 2014082053 W CN2014082053 W CN 2014082053W WO 2015003653 A1 WO2015003653 A1 WO 2015003653A1
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WO
WIPO (PCT)
Prior art keywords
data
pcm
gate array
non
array
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PCT/CN2014/082053
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French (fr)
Chinese (zh)
Inventor
张立新
夏飞
熊劲
蒋德钧
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华为技术有限公司
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Priority to CN201310293503.8A priority Critical patent/CN104282333A/en
Priority to CN201310293503.8 priority
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2015003653A1 publication Critical patent/WO2015003653A1/en

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564Miscellaneous aspects
    • G11C2211/5647Multilevel memory with bit inversion arrangement

Abstract

A storage method and apparatus based on data inversion. The apparatus comprises: a NOT gate array and a PCM. The NOT gate array comprises a NOT gate arranged on each data line. The NOT gate array is used to invert a value of each bit in initial data to obtain target data of the initial data, and input the target data to the PCM. The PCM is used to store the target data. The method comprises: a NOT gate array inverting a value at each bit of initial data to obtain target data of the initial data, and inputting the target data to the PCM; and the PCM storing the target data. When the foregoing storage apparatus and method are used to store data into a PCM, the to-be-stored data is directly inverted and then stored in the PCM, which solves the problem of large energy consumption and overheads in the prior art, and can improve the data storage efficiency.

Description

 Storage method and memory based on data inversion This application claims priority to Chinese patent application filed on July 12, 2013, the Chinese Patent Office, Application No. 201310293503.8, and the invention titled "Data Reversal Based Storage Method and Memory" The entire contents of which are incorporated herein by reference.

Technical field

 The present invention relates to computer technology, and more particularly to a data inversion based storage method and memory.

Background technique

 In the past few decades, the memory system consisted of a Dynamic Random Access Memory (DRAM). However, DRAM has a problem of high power consumption. In order to reduce the power consumption of the memory system, a non-volatile memory (NVM) can be used instead of DRAM to form a memory system. Among them, phase change memory (Phase Change Memory, PCM for short) is an NVM, which can replace the DRAM to form a memory system.

 Currently, when data is written to the PCM, the original data originally stored in the storage unit is read from the storage unit to which the data to be stored is to be written. Each bit value in the data to be stored is compared with each bit value in the original data. Compared with the original data, if more than half of the data bits in the data to be stored are changed, the data to be stored is inverted, written into the storage unit, and the data to be stored is marked as 1. Otherwise, the data to be stored is directly written to the storage unit, and the to-be-stored data tag is marked as 0. When reading data from the PCM, if the data to be read is marked as 1, the data is inverted after the data is read. If the data to be read is marked with 0, there is no need to invert the read data.

The above PCM data storage method needs to read the original data before writing the data, and needs to compare the data to be stored with the original data, and has the problem of large energy consumption overhead and low data storage efficiency. Summary of the invention

 Embodiments of the present invention provide a storage method and a memory based on data inversion, which are used to reduce

Energy consumption when storing data in PCM, and improving the efficiency of data storage.

 A first aspect of the present invention provides a memory, including: a non-gate array and a PCM; the non-gate array includes a NOT gate disposed on each data line;

 The non-gate array is configured to invert each bit value in the initial data to obtain target data of the initial data, and input the target data into the PCM;

 The PCM is configured to store the target data.

 In a first possible implementation manner of the first aspect, the PCM is further configured to receive a read command, read the first data corresponding to the read command, and input the first data to The non-gate array;

 The NOT gate array is further configured to invert a value of each bit in the first data to obtain the initial data corresponding to the first data.

 With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the PCM includes a PCM line buffer and a PCM storage array, where the PCM line is slowed down The buffer is connected to an external device through a data bus, and the PCM line buffer is connected to the PCM storage array through a bus;

 The NOT gate array is disposed between the PCM line buffer and the PCM memory array. In conjunction with the first aspect or the first possible implementation of the first aspect, in a third possible implementation manner of the first aspect, the PCM includes a PCM line buffer and a PCM storage array, the PCM line The buffer is connected to an external device through a data bus, and the PCM line buffer is connected to the PCM storage array through a bus;

 The NOT gate array is disposed on the data bus.

 A data inversion-based storage method according to a second aspect of the present invention includes: a non-gate array inverting each digit in the initial data to obtain target data of the initial data, and the target Data is input to the phase change memory PCM; wherein the non-gate array includes a NOT gate disposed on each data line;

The PCM stores the target data. In a first possible implementation manner of the second aspect, the method further includes: the PCM receiving a read instruction, reading first data corresponding to the read instruction, and inputting the first data to the NOT gate Array; the non-gate array inverts each bit value in the first data to obtain the initial data corresponding to the first data.

 With reference to the second aspect, or the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the PCM includes a PCM line buffer and a PCM storage array, and the PCM line buffer Connected to an external device via a data bus, the PCM line buffer and the PCM memory array being connected by a data line, the NOT gate array being disposed between the PCM line buffer and the PCM storage array;

 The non-gate array inverts each bit value in the initial data to obtain target data of the initial data, and inputting the target data into the PCM includes:

 The PCM line buffer inputs the initial data to the NOT gate array through the data line;

 Each of the non-gates in the non-gate array reverses a bit value in the initial data to obtain the target data, and inputs the data to the PCM storage array through the data line;

 The storing, by the PCM, the target data includes:

 The PCM memory array stores the target data.

 With reference to the second aspect, or the first possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the non-gate array inverts each digit in the first data And obtaining the initial data corresponding to the first data includes:

 The PCM storage array inputs the first data to the NOT gate array through the data line;

 Each of the NOT gates in the non-gate array inverts a bit value in the first data to obtain the initial data corresponding to the first data, and inputs the data through the data line Said PCM line buffer.

With reference to the second aspect, or the first possible implementation manner of the second aspect, in a fourth possible implementation manner of the second aspect, the PCM includes a PCM line buffer and a PCM storage array, and the PCM line buffer Connected to an external device via a data bus, the PCM line buffer and the PCM The storage array is connected by a bus; the non-gate array is disposed on the data bus; the non-gate array inverts each bit value in the initial data to obtain target data of the initial data, and the target is Data input to the PCM includes:

 The external device inputs the initial data to the NOT gate array through the data bus; each of the NOT gates in the NOT gate array inverts a bit value in the initial data to obtain The target data, the target data is input to the PCM line buffer through the data bus;

 The PCM line buffer inputs the target data to the PCM storage array through the data line;

 The storing, by the PCM, the target data includes:

 The PCM memory array stores the target data.

 With reference to the second aspect, or the first possible implementation of the second aspect, in a fifth possible implementation manner of the second aspect, the non-gate array inverts each digit in the first data And obtaining the initial data corresponding to the first data includes:

 The PCM line buffer inputs the first data to the NOT gate array through the data bus;

 Each of the NOT gates in the NOT gate array reverses a bit value in the first data, and obtains the initial data corresponding to the first data, and outputs the data through the data bus.

 The data inversion based storage method and the memory provided by the embodiment of the present invention, before storing data in the PCM, inverting each digit in the initial data through the non-gate array to obtain the target of the initial data. Data, the target data is input to the PCM, and the PCM stores the target data. When the data is stored in the PCM by the embodiment of the present invention, the data to be stored is directly inverted, the inverted data is stored in the PCM, the original data does not need to be read from the PCM, and the data to be stored and the original data are to be stored. The comparison and the like are performed, thereby overcoming the problem of high energy consumption in the prior art, and improving the efficiency of data storage.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will be true. The drawings used in the examples or the description of the prior art are briefly introduced. It is obvious that the drawings in the following description are only some embodiments of the present invention, and are not creative to those skilled in the art. Other drawings can also be obtained from these drawings on the premise of labor.

 1 is a schematic structural diagram of a memory according to an embodiment of the present invention;

 FIG. 2 is a schematic structural diagram of another memory according to an embodiment of the present disclosure;

 FIG. 3 is a schematic structural diagram of another memory according to an embodiment of the present disclosure;

 4 is a schematic diagram of a data inversion based storage method according to an embodiment of the present invention; FIG. 5 is a schematic diagram of another data inversion based storage method according to an embodiment of the present invention; A schematic diagram of another data inversion based storage method is provided. FIG. 7 is a schematic diagram of a data inversion based data reading method according to an embodiment of the present invention.

detailed description

 The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

 The technical solution of the present invention will be further described in detail below through the accompanying drawings and embodiments. When "0" is written to the PCM, it is necessary to apply a high voltage to the memory cell to make the state of the memory cell amorphous. In the amorphous state, the resistance of the memory cell is large and is used to represent the value "0". When writing "1" to the PCM, it is necessary to apply a low voltage to the memory cell to make the memory cell crystalline. In the crystalline state, the memory cell has a small resistance and is used to represent the value "1". In the above data writing mode of the PCM, the energy consumption of writing "0" is greater than the energy consumption of writing "1".

 In practical applications, the frequency used by the value "0" is significantly higher than the frequency of the value "1", and the energy consumption for writing "0" to the PCM is greater than the energy consumption for writing "1", so the data is directly written. In PCM, energy is wasted.

FIG. 1 is a schematic structural diagram of a memory according to an embodiment of the present invention. As shown in FIG. 1, the memory includes: a non-gate array 1 and a PCM 2. In this embodiment, the NOT gate array 1 includes a non-gate disposed on each data line. The NOT gate array 1 is for inverting each bit value of the initial data, obtaining target data of the initial data, and inputting the target data into the PCM 2. PCM2 is used to store target data.

 In this embodiment, the NOT gate array 1 acquires initial data to be stored from the data line, and a NOT gate is set on each data. Each of the NOT gates in the non-gate array 1 inverts a bit value in the initial data to obtain the target data corresponding to the initial data. In this embodiment, the inversion is to take "0" as "1" and "Γ" as "0".

 After the NOT gate array 1 acquires the target data, the target data is input to the PCM2 through the data line, and the PCM2 stores the target data.

 For example, the initial data is 00110101, and the non-gate array 1 inverts the initial data to obtain the target data 11001010, which is input to the PCM32, and the PCM2 stores the target data 11001010.

 The memory provided in this embodiment reverses each bit value in the initial data through the NOT gate array before storing the data to the PCM, obtains the target data of the initial data, inputs the target data into the PCM, and stores the PCM. Target data. When storing data in the PCM, the embodiment of the present invention directly inverts the initial data, and then stores the inverted target data in the PCM, does not need to read the original data from the PCM, and performs initial data and original data. Comparing the operations, thereby overcoming the problem of high energy consumption in the prior art, and improving the efficiency of data storage. Further, there is no need to mark the stored target data, which can save storage resources and energy consumption.

 Moreover, in practical applications, the value "0" is higher than the value "1". Since the energy consumption for writing "0" to the PCM is greater than the energy consumption for writing "Γ, the memory provided in this embodiment is written. Data can save energy.

 Further, the PCM 2 in the memory provided in this embodiment can also receive the read command and then read the first data corresponding to the read command. In the present embodiment, the first data read by the PCM 2 is the target data obtained after the initial data is inverted by the non-gate array 1, and is not the initial data. Therefore, when the first data is read, the PCM 2 inputs the first data into the NOT gate array 1. The NOT gate array 1 inverts each bit value in the first data to obtain initial data corresponding to the first data.

For example, when storing data to PCM2, the initial data is 00110101, non-gate array 1 The initial data is inverted, the target data 11001010 of the initial data is obtained, and the target data 11001010 is input to the PCM2. When the 00110101 needs to be read, a read command is sent to the PCM2, and the first data 11001010 is read according to the read command pair, and the PCM2 inputs the first data 11001010 to the NOT gate array 1 and passes through the NOT gate array 1 to the first. The data 11001010 is inverted to obtain initial data 00110101.

 2 is a schematic structural diagram of another memory provided by an embodiment of the present invention. As shown in Fig. 2, the memory includes a NOT gate array 1 and a PCM 2. The non-gate array 1 includes a non-gate that sets each data line. The PCM 2 includes a PCM line buffer 21 and a PCM memory array 22. The PCM line buffer 21 is connected to an external device via a data bus, and the PCM line buffer is also connected to the PCM memory array 22 via a data line. In the present embodiment, the NOT gate array 1 is disposed between the PCM line buffer 21 and the PCM storage array 22, that is, on each data line between the PCM line buffer 21 and the PCM storage array 22. The NOT gate constitutes the non-gate array 1.

 When data is stored to the PCM 2, the PCM line buffer 21 receives the initial data transmitted on the data line. The PCM line buffer 21 is connected with the same data line as the initial data bits, and each data line transmits a one-bit value in the initial data. The PCM line buffer 21 inputs the initial data to the NOT gate array 1 through the data line. Specifically, the PCM line buffer 21 inputs each bit value in the initial data into the NOT gate set on the corresponding data line. The NOT gate negates a one-bit value in the initial data transmitted from the data line connected to the NOT gate. The NOT gate array 1 After the target data of the initial data is obtained, the target data is input to the PCM storage array 22 through the data line, and the PCM storage array 22 stores the target data.

 When data is read from the PCM storage array 22, the PCM storage array 22 receives the read command and reads the first data corresponding to the read command in accordance with the read command. The PCM memory array 22 inputs the first data into the NOT gate array 1 through the data lines. Specifically, the PCM storage array 22 inputs each bit value in the first data through a data line into a NOT gate connected to the data line, and the NOT gate inverts a value of the first data. After the first data is inverted by the NOT gate array 1, the initial data corresponding to the first data is obtained, and then the initial data is passed through the PCM line buffer 21.

FIG. 3 is a schematic structural diagram of another memory according to an embodiment of the present invention. As shown in Figure 3, the The memory includes a NOT gate array 1 and a PCM 2. The NOT gate array 1 includes a non-gate that sets each data line. The PCM 2 includes a PCM line buffer 21 and a PCM memory array 22. The PCM line buffer 21 is connected to an external device via a data bus, and the PCM line buffer 21 is also connected to the PCM memory array 22 via a data line. In this embodiment, the NOT gate array 1 is disposed on the data bus. Specifically, a row of NOT gates is provided on the data bus between the external device and the PCM line buffer 21, and the number of non-gates is the same as the number of initial data. For example, if the initial data is 8 bits, then 8 non-gates are arranged side by side on the data bus, and each bit value corresponds to one NOT gate. A NOT gate on the data bus between the external device and the PCM line buffer 21 is formed to constitute the NOT gate array 1.

 When data is stored to the PCM storage array 22, the external device inputs the initial data into the NOT gate array 1 through the data bus. Each non-gate in the non-gate array 1 inverts a single value in the initial data transmitted on the data bus connected to the NOT gate to obtain target data of the initial data. After the target data is obtained, the NOT gate array 1 inputs the target data into the PCM line buffer 21 through the data bus, and the PCM line buffer 21 inputs the target data into the PCM storage array 22 through the data line, PCM. The storage array 22 stores the target data.

 Upon reading data from the PCM storage array 22, the PCM storage array 22 receives the read command, reads the first data corresponding to the read command, and inputs the first data into the PCM line buffer 21, The PCM line buffer 21 transmits the first data to the NOT gate array 1. Each non-gate in the non-gate array 1 inverts the one-bit value in the first data of the input non-gate. Non-gate array 1 After the first data is inverted, the initial data of the first data is obtained and output to the external device through the data bus.

 FIG. 4 is a schematic diagram of a storage method based on data inversion according to an embodiment of the present invention. As shown in Figure 4, the method includes the following steps:

 401. The non-gate array inverts each digit in the initial data to obtain target data of the initial data, and inputs the target data to the PCM. The non-gate array includes a data line disposed on each of the data lines. On the non-gate.

A non-gate array is provided in the PCM, and the non-gate array includes a NOT gate disposed on each data line. The initial data to be stored is input to the non-gate array through the data line, and one bit value in the initial data is input in each non-gate of the non-gate array, and the non-gate array inverts each bit value in the initial data, Target data to the initial data. In this embodiment, the inversion is to take "0" as "1" and "1" as "0".

 402. The PCM stores the target data.

 After acquiring the target data, the NOT gate array inputs the target data into the PCM through the data line, and the PCM stores the target data.

 For example, the initial data is 00110101, and the non-gate on each data line in the non-gate array inverts one bit of the initial data to obtain the target data 11001010 of the initial data, and stores the target data 11001010 in the PCM.

 The data inversion-based storage method provided in this embodiment forwards each bit value in the initial data through the NOT gate array to obtain target data of the initial data, and then stores the target data, before storing the initial data to the PCM. In PCM. The data inversion based storage method provided by the embodiment of the present invention directly reverses the initial data, does not need to read the original data from the PCM, and compares the initial data with the original data, thereby overcoming the existing There is a problem of high energy consumption in the technology and an increase in the efficiency of data storage. Further, there is no need to mark the stored target data, which can save storage resources and energy consumption.

 Moreover, in practical applications, the value "0" is higher than the value "1", because the energy consumption for writing "0" to the PCM is greater than the energy consumption for writing "Γ", by the storage method provided by this embodiment, Energy savings can be saved when writing data to the PCM.

 In practice, the PCM includes a PCM line buffer and a PCM memory array. The external device is connected to the PCM line buffer via the data bus, and the PCM line buffer is connected to the PCM memory array via the data line.

 An optional setting method for the non-gate array is that the non-gate array is placed between the PCM line buffer and the PCM memory array. FIG. 5 is a schematic diagram of another storage method based on data inversion according to an embodiment of the present invention. As shown in FIG. 5, the method includes the following steps:

 501. The PCM line buffer inputs initial data to the NOT gate array through the data line.

502. Each non-gate in the non-gate array inverts a bit value in the initial data to obtain target data, and inputs the data to the PCM storage array through the data line. 503. The PCM storage array stores target data.

 Another alternative method of setting up the non-gate array is: The gate array is placed on the data bus between the external device and the PCM line buffer. FIG. 6 is a schematic diagram of another storage method based on data inversion according to an embodiment of the present invention. As shown in Figure 6, the method includes the following steps:

 601. The external device inputs the initial data to the non-gate array through the data bus.

 602. Each non-gate in the non-gate array inverts a bit value in the initial data to obtain target data, and inputs the target data into the PCM line buffer through the data bus.

 603. The PCM line buffer inputs the target data to the PCM storage array through the data line.

 604. The PCM storage array stores target data.

 FIG. 7 is a schematic diagram of a data reading method based on data inversion according to an embodiment of the present invention. As shown in Figure 7, the method includes the following steps:

 701. The PCM receives a read command.

 An external device or controller can send a read command to the PCM when attempting to read data from the PCM.

 702. The PCM reads the first data corresponding to the read command, and inputs the first data to the NOT gate array. After the PCM reads the first data according to the read command, the first data is input to the NOT gate array through the data line.

 703. The non-gate array inverts each bit value in the first data to obtain initial data corresponding to the first data.

 Since the data is inverted through the NOT gate array when data is stored in the PCM, the storage in the PCM is not the initial data, but the target data obtained by inverting the initial data. After the first data is read in the PCM, it is input to the non-gate array through the data line. The non-gate array includes a NOT gate disposed on each data line. Each non-gate in the non-gate array inverts a bit value in the first data to obtain initial data corresponding to the first data.

For example, when storing data in the PCM, if the initial data is 00110101, the non-gate on each bit of the data inverts one bit of the initial data to obtain the target data 11001010 of the initial data, and the target data is obtained. 11001010 is stored in a storage array in the PCM. In from PCM When the data is read, the first data 11001010 is read from the storage array in the PCM, and the first data is input to the non-gate array through the data line, and the non-gate array inverts the first data to obtain initial data 00110101.

 In practice, the PCM includes a PCM line buffer and a PCM memory array. The external device is connected to the PCM line buffer via the data bus, and the PCM line buffer is connected to the PCM memory array via the data line.

 An optional setting method for the non-gate array is that the non-gate array is placed between the PCM line buffer and the PCM memory array. In this embodiment, the non-gate array inverts each bit value in the first data, and obtains initial data corresponding to the first data, specifically: the PCM storage array inputs the first data into the non-gate array through the data line, Each of the NOT gates in the non-gate array inverts a bit value in the first data to obtain initial data corresponding to the first data, and inputs the data into the PCM line buffer through the data line.

 Another alternative method of setting up the non-gate array is: The gate array is placed on the data bus between the external device and the PCM line buffer. In this embodiment, the non-gate array inverts each bit value in the first data, and obtains initial data corresponding to the first data, specifically: the PCM line buffer inputs the first data to the non-data through the data bus. The gate array, each non-gate in the non-gate array inverts a bit value in the first data, and obtains initial data corresponding to the first data, and outputs the data through the data bus.

 It should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention. range.

Claims

 Claim
What is claimed is: 1. A memory, comprising: a non-gate array and a phase change memory PCM; the non-gate array comprising a non-gate disposed on each data line;
 The non-gate array is configured to invert each bit value in the initial data to obtain target data of the initial data, and input the target data into the PCM;
 The PCM is configured to store the target data.
 2. The memory according to claim 1, wherein the PCM is further configured to receive a read command, read first data corresponding to the read command, and input the first data into the Non-gate array
 The non-gate array is further configured to invert each bit value in the first data to obtain the initial data corresponding to the first data.
 The memory according to claim 1 or 2, wherein the PCM comprises a PCM line buffer and a PCM memory array, and the PCM line buffer is connected to an external device via a data bus, the PCM line a buffer is connected to the PCM storage array through a data line;
 The NOT gate array is disposed between the PCM line buffer and the PCM memory array.
 The memory according to claim 1 or 2, wherein the PCM comprises a PCM line buffer and a PCM memory array, and the PCM line buffer is connected to an external device via a data bus, the PCM line a buffer is connected to the PCM storage array via a bus;
 The NOT gate array is disposed on the data bus.
 5. A storage method based on data inversion, characterized in that it comprises:
 The non-gate array inverts each bit value in the initial data to obtain target data of the initial data, and inputs the target data into the phase change memory PCM; wherein the non-gate array includes each data set Non-gate on the line;
 The PCM stores the target data.
 6. The method according to claim 5, further comprising: the PCM receiving a read command, reading first data corresponding to the read command, and inputting the first data into the method Non-gate array
The non-gate array inverts each bit value in the first data to obtain the first The initial data corresponding to the data.
 7. The method according to claim 5 or 6, wherein the PCM comprises a PCM line buffer and a PCM storage array; the PCM line buffer is connected to an external device via a data bus, the PCM line a buffer is connected to the PCM storage array by a data line, and the NOT gate array is disposed between the PCM line buffer and the PCM storage array;
 The non-gate array inverts each bit value in the initial data to obtain target data of the initial data, and inputting the target data into the PCM includes:
 The PCM line buffer inputs the initial data to the NOT gate array through the data line; each of the NOT gates in the NOT gate array reverses a bit value in the initial data Turning, obtaining the target data, and inputting to the PCM storage array through the data line;
 The storing, by the PCM, the target data includes:
 The PCM memory array stores the target data.
 The method according to claim 7, wherein the non-gate array inverts each bit value in the first data, and obtains the initial data corresponding to the first data to include : the PCM memory array inputs the first data to the NOT gate array through the data line; each of the NOT gates in the NOT gate array performs a bit value in the first data Inverting, the initial data corresponding to the first data is obtained, and is input to the PCM line buffer through the data line.
 9. The method according to claim 5 or 6, wherein the PCM comprises a PCM line buffer and a PCM memory array, the PCM line buffer being connected to an external device via a data bus, the PCM line a buffer is connected to the PCM storage array through a data line; the non-gate array is disposed on the data bus;
 The non-gate array inverts each bit value in the initial data to obtain target data of the initial data, and inputting the target data into the PCM includes:
The external device inputs the initial data to the NOT gate array through the data bus; each of the NOT gates in the NOT gate array inverts a bit value in the initial data to obtain The target data, the target data is input to the PCM line buffer through the data bus The PCM line buffer inputs the target data to the PCM storage array through the data line;
 The storing, by the PCM, the target data includes:
 The PCM memory array stores the target data.
 The method according to claim 9, wherein the non-gate array inverts each bit value in the first data, and obtains the initial data corresponding to the first data to include : the PCM line buffer inputs the first data to the NOT gate array through the data bus;
 Each of the NOT gates in the NOT gate array inverts a bit value in the first data, and obtains the initial data corresponding to the first data, and outputs the data through the data bus.
PCT/CN2014/082053 2013-07-12 2014-07-11 Storage method and memory based on data inversion WO2015003653A1 (en)

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US20080219047A1 (en) * 2007-03-06 2008-09-11 Electronics And Telecommunications Research Institute Apparatus and method for writing data to phase-change memory by using power calculation and data inversion
US20090091968A1 (en) * 2007-10-08 2009-04-09 Stefan Dietrich Integrated circuit including a memory having a data inversion circuit
CN103151072A (en) * 2013-03-28 2013-06-12 中国科学院微电子研究所 Method and device for writing data into phase change memory

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CN103151072A (en) * 2013-03-28 2013-06-12 中国科学院微电子研究所 Method and device for writing data into phase change memory

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