CN104280636A - Matching loop full-digital type power quality monitoring device and method adopting three-tier architecture - Google Patents
Matching loop full-digital type power quality monitoring device and method adopting three-tier architecture Download PDFInfo
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Abstract
The invention provides a matching loop full-digital type power quality monitoring device and method adopting three-tier architecture. The matching loop full-digital type power quality monitoring device comprises a data processing unit, a DSP calculating unit and an FPGA front unit. The data processing unit is connected with the DSP calculating unit connected with the FPGA front unit. The device has the advantages that the three-tier architecture and reasonable task distribution based on the characteristics of platforms of all layers are adopted, the data processing ability of the full-digital type power quality monitoring device is improved, and monitoring of the power quality up to five hundred and twelve wave points of each cycle and sixteen loops to the maximum is achieved; by means of a resampling technology, the problem that system fundamental frequency can not be tracked in the sampling process of a digital mutual inductor is solved, frequency tracking of digital sampling is achieved, the problem that spectrum leakage occurs when a sampling value of an original digital mutual inductor is utilized for harmonic analysis is solved, and the problem of effective value fluctuations generated when effective value calculating is carried out is solved.
Description
Technical field
The present invention relates to power domain, particularly relate to joined loop full digital equipment for monitoring power quality and the method for three-tier architecture.
Background technology
At present, digital transformer substation has become the development trend of electric system.At present, research both domestic and external focus mostly on digital transformer substation relay protection and combine from part, special actually rare at home and abroad for the research of the electric energy quality monitoring system being applied to digital transformer substation, most equipment for monitoring power quality can not access the merge cells of transformer station; Digital electric power quality on-line monitoring device and traditional quality of power supply device access require different.The ST multimode 100M fiber optic Ethernet interface to process layer of digitalization transformer substation should be provided at hardware view, the Frame of IEC 61850 9-1/2 (corresponding GB DL/T860-91/92) should be able to be resolved at software view.
Electronic mutual inductor is transferred to the digital sampled signal (being generally IEC 60044-7/8 standard frame data) of merge cells, and the sample frequency of the IEC 61850-9-2 standard frame digital sample value signal that merge cells exports is lower.Current most of electronic mutual inductor standard is with 200 points/cycle speed rates sampled value to merge cells, and it is 80 or maintenance 200 outputs that merge cells takes out value again, so current merge cells is 80 and 200 these two kinds of output speeds mostly.Sampling rate low like this, can not meet the accuracy requirement of power quality index, and quality of power supply device, compared to protection and metering outfit, must adopt the data guarantee device of high sampling rate to have high-precision result of calculation.Complete the analysis of power quality index, sampling rate is minimum will reach 512 every cycles, the domestic digital electric power quality analysis apparatus also not adapting to high-speed sampling.But high speed output can produce very large pressure to device load with decoding, if multiloop is monitored simultaneously, so higher to matching requirements.Rational framework must be adopted and reasonably distinguish task according to the feature of each layer architecture.
Current merge cells all exports digitized samples signal according to constant duration, if at this moment mains frequency departs from (such as being offset to 50.1Hz), due to cannot hardware frequency tracking be carried out, cause the cycle time of cycle sampling time and actual waveform unequal, if still adopt the Harmonics Calculation algorithm of conventional equipment in this case, serious spectral leakage will occur, and the error of calculation that overtone order is higher is larger, cannot accomplish accurate frequency analysis.
Summary of the invention
In order to solve the problems of the prior art, the invention provides a kind of joined loop full digital equipment for monitoring power quality of three-tier architecture.
The invention provides a kind of joined loop full digital equipment for monitoring power quality of three-tier architecture, comprise data processing unit, DSP computing unit, FPGA front end units, described data processing unit is connected with described DSP computing unit, and described DSP computing unit is connected with described FPGA front end units.
As a further improvement on the present invention, this can be joined loop full digital equipment for monitoring power quality and also comprise merge cells, described FPGA front end units is connected with described merge cells, described FPGA front end units carries out decoding for the data-signal being combined unit and transmitting, data resampling, and is uploaded to described DSP computing unit;
The sampled data that described DSP computing unit is uploaded for receiving described FPGA front end units, utilizes sampled data to complete the analysis of the quality of power supply;
Described data processing unit is used for completing statistics, managed storage, communications, man-machine interaction and remote control remote communication to the result of calculation that described DSP computing unit is uploaded.
As a further improvement on the present invention, described FPGA front end units comprises second order butterworth filter, obtains fundamental signal by the harmonic component of second order butterworth filter filtering raw digital samples data;
Wave point number is weekly determined to fundamental signal sampling zero crossing algorithm, according to sampled point interval, converts the primitive period, be then converted into fundamental frequency, achieve frequency measurement;
After obtaining frequency, whether determination frequency departs from power frequency, is greater than a threshold value, so carries out second order Newton interpolation to the data in setting-up time if departed from;
According to fundamental frequency determination resampling interval, according to resampling interval, sampling second order Newton interpolation carries out resampling to raw digital samples value.
As a further improvement on the present invention, this can join loop full digital equipment for monitoring power quality can process high-speed sample data up to 512, every cycle, and can monitor at most the quality of power supply in 16 loops simultaneously.
As a further improvement on the present invention, described data processing unit is connected with storer, display, button respectively; Described FPGA front end units is connected by fiber optic Ethernet with described merge cells.
As a further improvement on the present invention, described display is color screen liquid crystal display, and this can join interface when loop full digital equipment for monitoring power quality also comprises the GPS couple be connected with described data processing unit.
As a further improvement on the present invention, described data processing unit is connected by inner Ethernet with described DSP computing unit, and the dual port RAM that described DSP computing unit is realized by FPGA inside with described FPGA front end units is connected.
As a further improvement on the present invention, each FPGA front end units and a DSP computing unit form a measurement module, and each measurement module can carry out the electric energy quality monitoring in 4 loops, and user carries out the configuration of measurement module according to on-site actual situations.
Present invention also offers described in a kind of employing and can join the method that loop full digital equipment for monitoring power quality carries out digital electric power quality monitoring, first original sampling data bag is received, according to 61850 9-2 agreements, decoding is carried out to original sampling data bag and obtain original sample value, then low-pass filtering and zero passage judgement acquisition fundamental frequency are carried out to original sampling data, resampling is carried out according to the many original sampling datas of fundamental frequency, finally pretreated data upload to DSP computing unit, each module of FPGA front end units is triggered by triggering mark, resampling and frequency analysis that each FPGA front end units completes 24 × 512 original sampling datas of 4 merge cells 4 loop 24 passages in 20ms can be met after such distribution load.
As a further improvement on the present invention, described FPGA front end units comprises decoder module, and described FPGA front end units comprises execution following steps:
First when after system acceptance to effective 9-2 message, decoder module carries out a decode operation immediately, and decoded data buffer storage is in FIFO, and then decoder module enters into idle condition, waits for that effectively 9-2 message arrives next time;
After the message data of 10 cycles finishes receiving, can trigger once the computation process relevant to harmonic wave, this series of computation is parallel carries out:
First need the resampling carrying out original sampling data before Harmonics Calculation, resampling comprises two steps:
First be the measurement of fundamental frequency, fundamental signal is obtained by carrying out filtering to the original sampling data in FIFO, fundamental signal is input to frequency measuring block, and frequency measuring block adopts zero crossing determining method to calculate fundamental frequency, and these two modules are synchronous workings;
After frequency computation part, latch frequency resultant and export, trigger interpolation resampling module and resampling is carried out to original sampling data;
Frequency analysis module carries out frequency analysis to the sampled value after resampling, and after frequency analysis completes, the sampled value after resampling and the result of calculation of harmonic wave, just pass to DSP computing unit from dual port RAM.
The invention has the beneficial effects as follows: the feature and the technical requirement that the present invention is directed to digital transformer substation, adopt three layers of hardware platform architecture and achieve high sampling rate and super multiloop electric energy quality monitoring based on the reasonable task matching of every layer architecture characteristic.Described equipment for monitoring power quality can realize the electric energy quality monitoring in 512, every cycle and maximum 16 loops.The sampling rate of 512, every cycle can meet the analysis of a series of indexs such as the analysis of higher hamonic wave m-Acetyl chlorophosphonazo, transient state.The electric energy quality monitoring simultaneously carrying out 16 96 passages in loop can save customer investment, for user brings economic worth.Under power frequency catastrophe, according to system fundamental frequency, resampling is carried out to original sampling data by resampling technology and solve spectral leakage problem when directly utilizing original sampling data to carry out frequency analysis.
Accompanying drawing explanation
Fig. 1 of the present inventionly joins loop full digital equipment for monitoring power quality theory diagram.
Embodiment
As shown in Figure 1, the invention discloses a kind of joined loop full digital equipment for monitoring power quality of three-tier architecture, comprise data processing unit, DSP computing unit, FPGA front end units, described data processing unit is connected by inner Ethernet with described DSP computing unit, and the dual port RAM that described DSP computing unit is realized by FPGA inside with described FPGA front end units is connected.
Each FPGA front end units and a DSP computing unit form a measurement module, each measurement module can carry out the electric energy quality monitoring in 4 loops, one table apparatus can monitor 16 loops at most, user carries out the configuration of measurement module according to on-site actual situations, thus saves the electric energy quality monitoring cost of user.
The present invention can support the sampling rate of the digital CT/PT whole at present of 80,200,256,512, has very strong compatibility.
Data processing unit and DSP computing unit separate, described data processing unit carries out data interaction by Ethernet and described DSP computing unit.
Hardware platform of the present invention is Embedded Hardware Platform.
This digital electric power quality device three-decker reasonable distribution decoding, calculating and mutual task load, solve super multiloop, the Real-Time Monitoring difficult point of high sampling rate.
Described FPGA front end units is connected by fiber optic Ethernet with described merge cells, and described FPGA front end units carries out decoding for the original sampled signal being combined unit and transmitting, resampling.
Described FPGA front end units completes the reception of high-speed sampling digital signal, decoding, resampling, also can accomplish high-speed sampling under traditional quality of power supply unit simulation passage.But in digital channel situation, data source is Ethernet data bag, first must decode according to stipulations, and the speed of Ethernet data bag is very fast.Device process layer devices receives 61850 9-2 messages.A merge cells 1 loop, 12 passages, each 8asdu, data throughout per second reaches 12Mb.Be exactly 12Mb × 16=196Mb according to the words accessing 16 merge cellses at full capacity.With 20ms 512 calculating, the time leaving single data processing for is 1/ (50 × 512) s=39.0625 us.If single CPU had not only carried out decoding but also carry out power quality analysis will cause high load, probably caused can not respond some in time and calculate.Decoding and data prediction work are placed in FPGA and power quality analysis function are placed in DSP computing unit by the present invention.
Cannot the problem of tracker fundamental frequency when this resampling technique solves digital mutual inductor sample, achieve the frequency-tracking of digital sample, solve the spectral leakage problem that occurs when utilizing original figure mutual inductor sample value to carry out frequency analysis and carry out effective value and calculate the effective value fluctuation problem being.
Described FPGA front end units comprises second order butterworth filter, obtains fundamental signal by the harmonic component of second order butterworth filter filtering raw digital samples data;
Wave point number is weekly determined to fundamental signal sampling zero crossing algorithm, according to sampled point interval, converts the primitive period, be then converted into fundamental frequency, achieve frequency measurement;
After obtaining frequency, whether determination frequency departs from power frequency, is greater than a threshold value, so carries out second order Newton interpolation to the data in setting-up time if departed from;
According to fundamental frequency determination resampling interval, according to resampling interval, sampling second order Newton interpolation carries out resampling to raw digital samples value.
The framework of FPGA is applicable to processing parallel high-speed data, because their several modules are all completely independently, parallel.The work of modules is triggered by the triggering mark of oneself, automatically enters idle condition after completing, and waits for that trigger mark arrival triggering once calculates next time.
First when after system acceptance to effective 9-2 message, decoder module carries out a decode operation immediately, and decoded data buffer storage is in FIFO, and then decoder module enters into idle condition, waits for that effectively 9-2 message arrives next time.
After the message data of 10 cycles finishes receiving, can trigger once the computation process relevant to harmonic wave, this series of computation is parallel carries out:
First need the resampling carrying out original sampling data before Harmonics Calculation, resampling comprises two steps:
First be the measurement of fundamental frequency, fundamental signal is obtained by carrying out filtering to the original sampling data in FIFO, fundamental signal is input to frequency measuring block, and frequency measuring block adopts zero crossing determining method to calculate fundamental frequency, and these two modules are synchronous workings;
After frequency computation part, latch frequency resultant and export, trigger interpolation resampling module and resampling is carried out to original sampling data.
Frequency analysis module carries out frequency analysis to the sampled value after resampling.After frequency analysis completes, the sampled value after resampling and the result of calculation of harmonic wave, just pass to DSP computing function module from dual port RAM.
Whole flow process overview is got up for first receiving original sampling data bag, according to 61850 9-2 agreements, decoding is carried out to original sampling data bag and obtain original sample value, then low-pass filtering and zero passage judgement acquisition fundamental frequency are carried out to original sampling data, carry out resampling according to the many original sampling datas of fundamental frequency.Finally pretreated data upload to DSP computing unit.Each module of FPGA front end units is triggered by triggering mark, can meet resampling and frequency analysis that each FPGA front end units completes 24 × 512 original sampling datas of 4 merge cells 4 loop 24 passages in 20ms after such distribution load.
Described DSP BIOS operating system is the embedded OS that TI company provides, for task scheduling; Described DSP computing unit be under DSP BIOS operating system environment under carry out multi-task scheduling.
Described task comprises the quality of power supply evaluation works such as frequency-tracking, packet abnormality processing, data batchmove, harmonic wave flickering transient state.
Described data processing unit finally completes statistics, managed storage, communications, man-machine interaction and remote control remote communication to the result of calculation that described DSP computing unit is uploaded.
Resampling is another important task of FPGA front end units.
Complete resampling and will complete three steps, 1. software filtering 2. threshold decision 3. interpolation resampling.First by second order butterworth filter, filtering harmonic component obtains fundametal compoment, gets rid of harmonic wave to the interference of zero crossing, then calculates fundamental frequency to fundamental signal sampling zero crossing evaluation algorithm.
Judge whether fundamental frequency departs from power frequency more than a scope, is greater than a threshold value if departed from, and so carries out the resampling of second order Newton interpolation to the original sampling data in setting-up time, if deviation is very little, skips interpolation resampling steps, reduce system loading;
Frequency measurement is the basis of resampling, is the basis next calculated.If actual frequency and power frequency gap have exceeded deviation threshold, be then for further processing.Can have a strong impact on frequency analysis and other quality of power supply computing index analysis calculating generation because frequency exceedes this deviation threshold.Original sampling data needs to carry out resampling according to fundamental frequency.
Current merge cells all exports digitized samples signal according to constant duration, such as every specified 512 point samplings of 20ms, if at this moment mains frequency departs from (such as being offset to 50.1Hz), then 512 of original sampled signal what represent is 0.998 cycle length.Make frequency analysis result occur error if use this original 512 points just there will be spectral leakage when carrying out frequency analysis, moreover also can cause the results such as effective value fluctuation and transient state malfunction.
The FPGA front end units of described device can receive 5120 original sampling datas within the reception buffer zone 200ms time, first carrying out cutoff frequency to these original sampling datas is that the Butterworth lowpass ripple on 2 rank of 75Hz obtains fundamental signal, removes the interference that harmonic wave judges first-harmonic zero crossing.Then the zero passage of fundamental signal sampling first-harmonic zero passage evaluation algorithm calculating 200ms is counted, drawn wave point number weekly thus, be then converted into actual frequency according to every cycle sampling number and crude sampling interval.The frequency-tracking of 10 cycles calculates window and can reduce cumulative errors, and this is consistent with the time window length of frequency analysis, and frequency analysis directly can utilize the sampled data after resampling, decreases the repeatability of task.Whether every 200ms device first determination frequency departs from power frequency, is greater than a threshold value if departed from, and will carry out interpolation resampling to the original sampling data of this 200ms.Counterweight sampled data is carried out frequency analysis and is obtained frequency analysis result.
Suppose that obtaining that crude sampling that every cycle contains counts by zero crossing algorithm is M, resampling to become the N number of sampled point of every cycle, the ratio at crude sampling interval and resampling interval is N/M.Be spaced apart unit with resampling to convert to the n-th original sampling data subscript, then the n-th resample points be positioned at resampling after M/N × n position.
Described when frequency is 50.1Hz above, every cycle 510.98 sampled points, resampling becomes every cycle 512 point sampling sequence, and the ratio with regard to resampling interval and crude sampling interval is 0.998.So resampling sequence f ' (0), f ' (1), f ' (2) ... f ' (5), f ' (6), f ' (7) ... being mapped to the sequence after crude sampling is exactly f (0), f (1 × 0.998), f (2 × 0.998) ... f ' (5 × 0.998), f ' (6 × 0.998), f ' (7 × 0.998) ...The subscript position of each point is multiplied by 0.998 times.Second order Newton interpolation needs the amplitude of three nearest sampled points, for resample points f ' (5), is designated as 4.99 under the original point after mapping.According to the principle rounded, so nearest sampled point is f (4).So according to newton forward difference require need f (2), f (3), f (4).
The Interpolation Process of the sequence n after resampling is:
1) search according to above-described method and to be less than and closest to 3 original sample value f (x0) of n, f (x1), f (x2), wherein x0, x1, x2 are the subscript of crude sampling.
2) carry out second order Newton's formula according to the following step and carry out interpolation
The error mainly three rank remainders of interpolation, because three jump business are smaller, and sampling interval is very little so error is in very little scope.
The present invention to raw data carry out resampling solve power frequency sudden change under frequency analysis precision problem.
The sampling rate of described merge cells is as a systematic parameter write digital electric power quality monitoring device, this digital electric power quality monitoring device can judge this systematic parameter when initialization, if sampling rate changes, so described FPGA front end units can select corresponding algorithm of harmonics analysis according to sampling rate, and described DSP computing unit also can select suitable flickering analytical algorithm according to sampling rate simultaneously.
The sampling rate of external merge cells is as a systematic parameter writing station, can judge this parameter during device initialization, the calculation window of such as, frequency analysis under 512 point sampling rates is 5120 points, if systematic parameter is modified to 80 inputs, frequency analysis calculation window can be revised as 1280 according to this systematic parameter by FPGA front end units.DSP computing unit also can revise the parameter of each wave filter in flickering model simultaneously, and the calculation process walked during plant running is just sampled rate and has differentiated, and so just achieves the algorithm self-adaptation in whole sampling rate situation.
Described invention can adapt to the access of merge cells of 80 points, 200 points, 256 points, 400 points, 512 multiple sampling rates.Can the merge cells of compatible main flow at present, reduce the improvement cost of traditional transformer station.
By being combined the judgement of unit sampling rate, realize algorithm of harmonics analysis for different sampling rates at software inhouse, the self-adaptative adjustment of half-wave rms algorithm and flickering scheduling algorithm.Improve the applicability of device, described digital electric power quality monitoring device is accessed in the merge cells of current main flow.
The present invention adopts the data stream of high-performance FPGA to IEC61850 9-2 stipulations to receive and real-time decoding, when the sampling rate of merge cells is 25.6KHz, receive data volume and can reach 12Mbps, in addition FPGA also needs the data received are carried out to validity, synchronous etc. to be judged, will carry out resampling when non-power frequency inputs to data.The task of this unit to bottom layer driving and each module has done reasonable arrangement and optimization.Finally meet the decoding under high sampling rate and resampling.
The present invention can apply and various multiloop occasion.As the Centralizing inspection, double-bus multi circuit transmission lines Centralizing inspection etc. of single busbar multi-loop line, by the concentrated measurement of the quality of power supply correlation parameter of the busbar voltage in monitoring circuit, multiple equipped circuit, voltage, electric current, power, electric energy, display there is communication export, can realize the quality of power supply in multiple loop and full electricity monitoring.The present invention adopts modular design, makes user can need to carry out loop configuration type selecting according to practical application, selects the cost-effective solution meeting oneself demand, thus reduces the waste of resource.When needing to increase Monitoring Line, directly can increase merge cells access module and corresponding merge cells, without the need to newly-increased digitalized electric energy quality monitoring device.This digital electric power quality monitoring device expands at most 16 loops monitoring (every loop comprises 3 phase voltages and 3 phase currents).
What this digital electric power quality monitoring device adopted is the parsing specification of the IEC61850 9-2 message of standard, the merge cells of on-the-spot accessible different manufacturers, and the channel sequence in each loop can freely configure.Can the wiring condition at flexible adaptation scene.
The sampled data that described DSP computing unit is uploaded for receiving described FPGA front end units, utilizes sampled data to complete the analysis of the quality of power supply, comprises the judgement of the voltage disturbances such as transient state, transient state, flickering;
Described data processing unit is used for completing statistics, managed storage, communications, man-machine interaction and remote control remote communication to the result of calculation that described DSP computing unit is uploaded.
Described FPGA front end units realizes dual port RAM by inside, realizes with the high rate data of DSP computing unit mutual.
The peripheral hardwares such as described data processing unit and storer, display, Ethernet are connected, and realize that data store, man-machine interaction and communication function.
Described display is color screen liquid crystal display, and described Ethernet light/electrical interface is two 10/100M Ethernet light/electrical interfaces, and described data processing unit is also connected with external GPS correction device by interface during outside target range instrument group IRIG-B couple.
Fpga logic device of the present invention is high-speed programmable gate array functional unit.
Described data processing unit is PowerPC processor, and this PowerPC processor is the CPU of the RISC framework of 32bit floating point processor.
Data processing unit is also responsible for controlling two RS-485 mouth, USB port and 8 road signal lamps.
DSP computing unit carries out conventional power quality parameter operational analysis to decoded data and result of calculation is uploaded to data processing unit together with the frequency analysis result of FPGA front end units analysis.The measurement of DSP computing unit primary responsibility voltage deviation, frequency departure, harmonic wave, flickering, degree of unbalancedness, electric current and voltage amplitude, flickering etc.; And the monitoring to transient state, transient electric-energy quality events, and the waveform event in recording events generating process.
Analog quantity channel divides by loop by data processing unit, and 6 passages (3 current channels+3 voltage channels) are a loop.Data processing unit at most can the data of corresponding 16 merge cellses, 16 loops namely 4 DSP computing units.Each loop record independently, can respond respectively.Data processing unit adopts VxWorks real time operating system, based on hard real-time system, preemptive kernel, guarantees that mission critical first priority responds.
Data processing unit also will complete that data store, communication and the function of man-machine interaction.Data processing unit by the storage of two 10/100M self-adaptation Ethernet interfaces of outside, two RS-485 mouth and USB port control realization data, communicate and the function of man-machine interaction.
The present invention is directed to feature and the technical requirement of digital transformer substation, adopt rational three-tier architecture and achieve high sampling rate and multiloop electric energy quality monitoring according to the rational allocating task of the feature of each layer architecture.Equipment for monitoring power quality of the present invention can realize the monitoring of the quality of power supply in 512 every cycles and 16 loops.The present invention realizes 512, every cycle can ensure harmonic wave, the high precision of the analysis result such as transient state, flickering.The electric energy quality monitoring that the present invention simultaneously can carry out 16 loops is simultaneously that user brings huge economic worth.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to protection scope of the present invention.
Claims (10)
1. the joined loop full digital equipment for monitoring power quality of a three-tier architecture, it is characterized in that, comprise data processing unit, DSP computing unit, FPGA front end units, described data processing unit is connected with described DSP computing unit, and described DSP computing unit is connected with described FPGA front end units.
2. according to claim 1ly join loop full digital equipment for monitoring power quality, it is characterized in that: this can be joined full digital equipment for monitoring power quality front end, loop and comprise merge cells, described FPGA front end units is connected with described merge cells, described FPGA front end units carries out decoding for the data-signal being combined unit and transmitting, data resampling, and is uploaded to described DSP computing unit;
The sampled data that described DSP computing unit is uploaded for receiving described FPGA front end units, utilizes sampled data to complete the analysis of the quality of power supply;
Described data processing unit is used for completing statistics, managed storage, communications, man-machine interaction and remote control remote communication to the result of calculation that described DSP computing unit is uploaded.
3. according to claim 2ly join loop full digital equipment for monitoring power quality, it is characterized in that: described FPGA front end units comprises second order butterworth filter, obtain fundamental signal by the harmonic component of second order butterworth filter filtering raw digital samples data;
Wave point number is weekly determined to fundamental signal sampling zero crossing algorithm, according to sampled point interval, converts the primitive period, be then converted into fundamental frequency, achieve frequency measurement;
After obtaining frequency, whether determination frequency departs from power frequency, is greater than a threshold value, so carries out second order Newton interpolation to the data in setting-up time if departed from;
According to fundamental frequency determination resampling interval, according to resampling interval, sampling second order Newton interpolation carries out resampling to raw digital samples value.
4. according to claim 2ly join loop full digital equipment for monitoring power quality, it is characterized in that: this can join loop full digital equipment for monitoring power quality can process high-speed sample data up to 512, every cycle, and can monitor at most the quality of power supply in 16 loops simultaneously.
5. according to claim 2ly join loop full digital equipment for monitoring power quality, it is characterized in that: described data processing unit is connected with storer, display, button respectively; Described FPGA front end units is connected by fiber optic Ethernet with described merge cells.
6. according to claim 5ly join loop full digital equipment for monitoring power quality, it is characterized in that: described display is color screen liquid crystal display, this can join interface when loop full digital equipment for monitoring power quality also comprises the GPS couple be connected with described data processing unit.
7. according to claim 1ly join loop full digital equipment for monitoring power quality, it is characterized in that: described data processing unit is connected by inner Ethernet with described DSP computing unit, the dual port RAM that described DSP computing unit is realized by FPGA inside with described FPGA front end units is connected.
8. according to claim 1ly join loop full digital equipment for monitoring power quality, it is characterized in that: each FPGA front end units and a DSP computing unit form a measurement module, each measurement module can carry out the electric energy quality monitoring in 4 loops, and user carries out the configuration of measurement module according to on-site actual situations.
9. one kind adopts described in any one of claim 1 to 8 and can join the method that loop full digital equipment for monitoring power quality carries out digital electric power quality monitoring, it is characterized in that, first original sampling data bag is received, according to 61850 9-2 agreements, decoding is carried out to original sampling data bag and obtain original sample value, then low-pass filtering and zero passage judgement acquisition fundamental frequency are carried out to original sampling data, resampling is carried out according to the many original sampling datas of fundamental frequency, finally pretreated data upload to DSP computing unit, each module of FPGA front end units is triggered by triggering mark, resampling and frequency analysis that each FPGA front end units completes 24 × 512 original sampling datas of 4 merge cells 4 loop 24 passages in 20ms can be met after such distribution load.
10. method according to claim 9, is characterized in that: described FPGA front end units comprises decoder module, and described FPGA front end units comprises execution following steps:
First when after system acceptance to effective 9-2 message, decoder module carries out a decode operation immediately, and decoded data buffer storage is in FIFO, and then decoder module enters into idle condition, waits for that effectively 9-2 message arrives next time;
After the message data of 10 cycles finishes receiving, can trigger once the computation process relevant to harmonic wave, this series of computation is parallel carries out:
First need the resampling carrying out original sampling data before Harmonics Calculation, resampling comprises two steps:
First be the measurement of fundamental frequency, fundamental signal is obtained by carrying out filtering to the original sampling data in FIFO, fundamental signal is input to frequency measuring block, and frequency measuring block adopts zero crossing determining method to calculate fundamental frequency, and these two modules are synchronous workings;
After frequency computation part, latch frequency resultant and export, trigger interpolation resampling module and resampling is carried out to original sampling data;
Frequency analysis module carries out frequency analysis to the sampled value after resampling, and after frequency analysis completes, the sampled value after resampling and the result of calculation of harmonic wave, just pass to DSP computing unit from dual port RAM.
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| CN106291096A (en) * | 2016-07-20 | 2017-01-04 | 中国电力科学研究院 | A kind of multistage method for resampling for nonlinear load electric energy meter |
| CN107782994A (en) * | 2017-10-20 | 2018-03-09 | 广州供电局有限公司 | Power Quality Transient event monitoring method and device |
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