CN104270144A - Three-input general logic gate circuit - Google Patents
Three-input general logic gate circuit Download PDFInfo
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- CN104270144A CN104270144A CN201410417709.1A CN201410417709A CN104270144A CN 104270144 A CN104270144 A CN 104270144A CN 201410417709 A CN201410417709 A CN 201410417709A CN 104270144 A CN104270144 A CN 104270144A
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Abstract
The invention discloses a three-input general logic gate circuit, which comprises a first two-input NAND gate U1, a second two-input NAND gate U4, a third two-input NAND gate U5, a first NOT gate U2 and a second NOT gate U3, wherein each gate circuit is formed by a single electron transistor; the first input end of the first two-input NAND gate U1 is connected to the input end of the first NOT gate U2, and the output end of the first two-input NAND gate U1 is connected to the first input end of the third two-input NAND gate U5; the output end of the first NOT gate U2 is connected to the first input end of the second two-input NAND gate U4; the input end of the second NOT gate U3 is taken as an input end V3 of the general logic gate circuit, and the output end of the second NOT gate U3 is connected to the second input end of the second two-input NAND gate U4; the output end of the second two-input NAND gate U4 is connected to the second input end of the third two-input NAND gate U5. The three-input general logic gate circuit has the advantages of nanometer ultra-small volume, ultra-low power consumption and extremely-high switching speed.
Description
Technical field
The present invention relates to Nano Scale Electronics Technology field, especially a kind of generic logic gate circuit.
Background technology
Integrated circuit technique achieves breakthrough in the past more than 50 year, but the problem such as power consumption and interconnection line tapers to its physics limit by making the characteristic size of traditional cmos (Complementary Metal Oxide Semiconductor) device.When characteristic size tapers to nanoscale by micron order, quantum effect will be occupied an leading position and may be made component failure, therefore while exploration breaks through microelectronics physics limit, scientific research personnel proposes with single-electronic transistor (SET, Single Electron Transistor) in order to replace the research approach of cmos device, to developing new very lagre scale integrated circuit (VLSIC) (VLSI, Very Large Scale Integration) technology.
As the strong competitor of nano electron device of new generation, SET work only needs little electronics, it has extremely low power consumption, and (power consumption of single SET is pw level, lower than CMOS 6,7 orders of magnitude), the feature such as extra small volume (nm level) and high switching speed (ns level can be reached), and it has unique Coulomb blockade effect and coulomb step effect, relative to traditional microelectronic component, there is absolute advantage, there is good application prospect.
Existing generic logic gate circuit, usually adopts cmos device to form, utilizes cmos device to form NAND gate and not gate, the technological deficiency of existence: volume is comparatively large, power consumption is higher, switching speed is slower.
Summary of the invention
In order to overcome the deficiency that volume is comparatively large, power consumption is higher, switching speed is slower of existing generic logic gate circuit, the invention provides three input generic logic gate circuits of a kind of nanoscale ultra-small volume, super low-power consumption, high switching speed.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of three input generic logic gate circuits, described circuit comprises the one or two input nand gate U1, the two or two input nand gate U4, the three or two input nand gate U5, the first not gate U2 and the second not gate U3, and described one or two input nand gate U1, the two or two input nand gate U4, the three or two input nand gate U5, the first not gate U2 and the second not gate U3 form by single-electronic transistor;
As the first input end V1 of generic logic gate circuit after the first input end of the one or two input nand gate U1 is connected with the input of the first not gate U2, second input of the one or two input nand gate U1 is as the second input V2 of generic logic gate circuit, and the output of the one or two input nand gate U1 is connected with the first input end of the three or two input nand gate U5; The output of the first not gate U2 is connected with the first input end of the two or two input nand gate U4; The input of the second not gate U3 is as the input V3 of generic logic gate circuit, and the output of the second not gate U3 is connected with second input of the two or two input nand gate U4; The output of the two or two input nand gate U4 is connected with second input of the three or two input nand gate U5; The output of the three or two input nand gate U5 is as the output end vo ut of generic logic gate circuit.
Further, described one or two input nand gate U1, two or two input nand gate U4, three or two input nand gate U5 all adopts two input nand gate structures, two input nand gate structures comprise a P type single-electronic transistor, 2nd P type single-electronic transistor, first N-type single-electronic transistor and the second N-type single-electronic transistor, as the first input end of two input nand gates after the grid of a described P type single-electronic transistor is connected with the grid of the first N-type single-electronic transistor, as the second input of two input nand gates after the grid of described 2nd P type single-electronic transistor is connected with the grid of the second N-type single-electronic transistor, the drain electrode of the one P type single-electronic transistor is connected with VDD, the drain electrode of the 2nd P type single-electronic transistor is unsettled, one P type single-electronic transistor source electrode, as the output of two input nand gates after the source electrode of the one P type single-electronic transistor is connected with the drain electrode of the first N-type single-electronic transistor, the source ground of the second N-type single-electronic transistor.
Further again, described first not gate U2 and the second not gate U3 all adopts non-door, described non-door comprises the 3rd P type single-electronic transistor and the 3rd N-type single-electronic transistor, the grid of the 3rd P type single-electronic transistor is connected as the input of not gate with the grid of the 3rd N-type single-electronic transistor, the source electrode of the 3rd P type single-electronic transistor is connected as the output of not gate with the drain electrode of the 3rd N-type single-electronic transistor, the drain electrode of the 3rd P type single-electronic transistor is unsettled, the source ground of the 3rd N-type single-electronic transistor.
Technical conceive of the present invention is: the present invention can obtain different Output rusults respectively according to 8 kinds of different input states, and namely a gate circuit can realize multiple different logic function to meet different needs.
Described two input nand gate U1 are made up of two P type single-electronic transistors (P-SET) and two N-type single-electronic transistors (N-SET).Described not gate U2 is made up of a P-SET and N-SET.Described not gate U3 is made up of a P-SET and N-SET.Described two input nand gate U4 are made up of two P-SET and two N-SET.Described two input nand gate U5 are made up of two P-SET and two N-SET.
Described logic gates has the features such as ultra-small volume (nm level), super low-power consumption (pw level) and high switching speed (ns level), and these features make this logic gates be with a wide range of applications.
Beneficial effect of the present invention is mainly manifested in: nanoscale ultra-small volume, super low-power consumption, high switching speed.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of three input generic logic gate circuits.
Fig. 2 is the schematic diagram of three input generic logic gate circuits.
Fig. 3 is the specific embodiment schematic diagram of three input generic logic gate circuits.
Fig. 4 is the schematic diagram of single-electronic transistor described in three input generic logic gate circuits.
Fig. 5 is the simulation result figure of three input generic logic gate circuits.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
With reference to Fig. 1 ~ Fig. 5, a kind of three input generic logic gate circuits, described circuit comprises the one or two input nand gate U1, the two or two input nand gate U4, the three or two input nand gate U5, the first not gate U2 and the second not gate U3, and described one or two input nand gate U1, the two or two input nand gate U4, the three or two input nand gate U5, the first not gate U2 and the second not gate U3 form by single-electronic transistor;
As the first input end V1 of generic logic gate circuit after the first input end of the one or two input nand gate U1 is connected with the input of the first not gate U2, second input of the one or two input nand gate U1 is as the second input V2 of generic logic gate circuit, and the output of the one or two input nand gate U1 is connected with the first input end of the three or two input nand gate U5; The output of the first not gate U2 is connected with the first input end of the two or two input nand gate U4; The input of the second not gate U3 is as the input V3 of generic logic gate circuit, and the output of the second not gate U3 is connected with second input of the two or two input nand gate U4; The output of the two or two input nand gate U4 is connected with second input of the three or two input nand gate U5; The output of the three or two input nand gate U5 is as the output end vo ut of generic logic gate circuit.
Further, described one or two input nand gate U1, two or two input nand gate U4, three or two input nand gate U5 all adopts two input nand gate structures, two input nand gate structures comprise a P type single-electronic transistor, 2nd P type single-electronic transistor, first N-type single-electronic transistor and the second N-type single-electronic transistor, as the first input end of two input nand gates after the grid of a described P type single-electronic transistor is connected with the grid of the first N-type single-electronic transistor, as the second input of two input nand gates after the grid of described 2nd P type single-electronic transistor is connected with the grid of the second N-type single-electronic transistor, the drain electrode of the one P type single-electronic transistor is connected with VDD, the drain electrode of the 2nd P type single-electronic transistor is unsettled, one P type single-electronic transistor source electrode, as the output of two input nand gates after the source electrode of the one P type single-electronic transistor is connected with the drain electrode of the first N-type single-electronic transistor, the source ground of the second N-type single-electronic transistor,
Described first not gate U2 and the second not gate U3 all adopts non-door, described non-door comprises the 3rd P type single-electronic transistor and the 3rd N-type single-electronic transistor, the grid of the 3rd P type single-electronic transistor is connected as the input of not gate with the grid of the 3rd N-type single-electronic transistor, the source electrode of the 3rd P type single-electronic transistor is connected as the output of not gate with the drain electrode of the 3rd N-type single-electronic transistor, the drain electrode of the 3rd P type single-electronic transistor is unsettled, the source ground of the 3rd N-type single-electronic transistor.
The logical expression of the present embodiment is
As shown in Figure 1, be the schematic diagram of a kind of three input generic logic gate circuits of the present invention, this module has three inputs (first input end V1, the second input V2, the 3rd input V3) and an output end vo ut.The present invention is mainly by the input signal of control three inputs, and can obtain different results, the logic function that namely same circuit realiration is different is to realize different demands.
Circuit theory diagrams as shown in Figure 2, present embodiments provide a kind of three input generic logic gate circuits be made up of single-electronic transistor, comprise the one or two input nand gate U1, the two or two input nand gate U4, the three or two input nand gate U5 altogether, with the first not gate U2, the second not gate U3, and U1, U2, U3, U4, U5 are all made up of single-electronic transistor; As the first input end V1 of generic logic gate circuit after the first input end 1 of the one or two input nand gate U1 is connected with the input 4 of the first not gate U2, second input 2 of the one or two input nand gate U1 is as the input V2 of generic logic gate circuit, and the output 3 of the one or two input nand gate U1 is connected with the first input end 11 of the three or two input nand gate U5; The output 5 of the first not gate U2 is connected with the first input end 8 of the two or two input nand gate U4; The input 6 of the second not gate U3 is as the 3rd input V3 of generic logic gate circuit, and the output 7 of the second not gate U3 is connected with second input 9 of the two or two input nand gate U4; The output 10 of the two or two input nand gate U4 is connected with second input 12 of the three or two input nand gate U5; The output 13 of the three or two input nand gate U5 is as the output end vo ut of generic logic gate circuit.
One or two input nand gate U1 is made up of two P type single-electronic transistors (P-SET) and two N-type single-electronic transistors (N-SET), and two P type single-electronic transistors are respectively T1 and T3, and two N-type single-electronic transistors are T2 and T4.
First not gate U2 is made up of a P-SET and N-SET, i.e. T9 and T10.
Second not gate U3 is made up of a P-SET and N-SET, i.e. T15 and T16.
Two or two input nand gate U4 is made up of two P-SET and two N-SET, and two P type single-electronic transistors are respectively T11 and T13, and two N-type single-electronic transistors are T12 and T14.
Three or two input nand gate U5 is made up of two P-SET and two N-SET, and two P type single-electronic transistors are respectively T15 and T17, and two N-type single-electronic transistors are T6 and T8.
Specific embodiment as shown in Figure 3, comprise 8 P-SET and 8 N-SET, wherein the structure of P-SET and N-SET as shown in Figure 4, parameter is as shown in table 1, and wherein T is the working temperature of SET, and Q0 is the background charge of SET, C0 is parasitic capacitance, Cg is grid capacitance, and C1, C2 are tunnel junctions electric capacity, and R1, R2 are tunnel junctions resistance.
Table 1
As V1=0, universal logic circuit be one by V3 as input not circuit.
As V1=1, universal logic circuit be one by V2 as input follow circuit.
As V2=0, universal logic circuit is one and inputs NAND circuits by V1, V3 as two of input.
As V3=0, universal logic circuit is one and inputs AND circuit by V1, V2 as two of input.
When V2 and V3 is in parallel, universal logic circuit becomes one by V1, V2 same or circuit as input.
When V2 get non-post in parallel with V3 time, universal logic circuit become one by V3 as input not circuit.
The present invention utilizes PSPICE to carry out simulating, verifying to circuit, the SET model of employing be widely use at present, high-precision macro model (Compact macro-model).From its logical expression, it is available that logic gates has eight kinds of states, and as shown in Table 2, Simulation results is as shown in Figure 5, and consistent with result in above-mentioned table, illustrates that logic gates can true(-)running for these eight kinds of states.
| V3 | V2 | V1 | V?out |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
Table 2
Above-listed preferred embodiment; to object of the present invention; technical scheme and advantage have carried out further detailed description; be understood that; the above is preferred embodiment of the present invention, is not limited to the present invention, within the spirit and principles in the present invention all; any amendment of doing, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. an input generic logic gate circuit, it is characterized in that: described circuit comprises the one or two input nand gate U1, the two or two input nand gate U4, the three or two input nand gate U5, the first not gate U2 and the second not gate U3, described one or two input nand gate U1, the two or two input nand gate U4, the three or two input nand gate U5, the first not gate U2 and the second not gate U3 form by single-electronic transistor;
As the first input end V1 of generic logic gate circuit after the first input end of the one or two input nand gate U1 is connected with the input of the first not gate U2, second input of the one or two input nand gate U1 is as the second input V2 of generic logic gate circuit, and the output of the one or two input nand gate U1 is connected with the first input end of the three or two input nand gate U5; The output of the first not gate U2 is connected with the first input end of the two or two input nand gate U4; The input of the second not gate U3 is as the input V3 of generic logic gate circuit, and the output of the second not gate U3 is connected with second input of the two or two input nand gate U4; The output of the two or two input nand gate U4 is connected with second input of the three or two input nand gate U5; The output of the three or two input nand gate U5 is as the output end vo ut of generic logic gate circuit.
2. three input generic logic gate circuits as claimed in claim 1, it is characterized in that: described one or two input nand gate U1, two or two input nand gate U4, three or two input nand gate U5 all adopts two input nand gate structures, two input nand gate structures comprise a P type single-electronic transistor, 2nd P type single-electronic transistor, first N-type single-electronic transistor and the second N-type single-electronic transistor, as the first input end of two input nand gates after the grid of a described P type single-electronic transistor is connected with the grid of the first N-type single-electronic transistor, as the second input of two input nand gates after the grid of described 2nd P type single-electronic transistor is connected with the grid of the second N-type single-electronic transistor, the drain electrode of the one P type single-electronic transistor is connected with VDD, the drain electrode of the 2nd P type single-electronic transistor is unsettled, the source electrode of the one P type single-electronic transistor, one P type single-electronic transistor source electrode be connected with the drain electrode of the first N-type single-electronic transistor after as the output of two input nand gates, the source ground of the second N-type single-electronic transistor.
3. three input generic logic gate circuits as claimed in claim 1 or 2, it is characterized in that: described first not gate U2 and the second not gate U3 all adopts non-door, described non-door comprises the 3rd P type single-electronic transistor and the 3rd N-type single-electronic transistor, the grid of the 3rd P type single-electronic transistor is connected as the input of not gate with the grid of the 3rd N-type single-electronic transistor, the source electrode of the 3rd P type single-electronic transistor is connected as the output of not gate with the drain electrode of the 3rd N-type single-electronic transistor, the drain electrode of the 3rd P type single-electronic transistor is unsettled, the source ground of the 3rd N-type single-electronic transistor.
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