CN104267329A - Transistor test circuit and method - Google Patents
Transistor test circuit and method Download PDFInfo
- Publication number
- CN104267329A CN104267329A CN201410563203.1A CN201410563203A CN104267329A CN 104267329 A CN104267329 A CN 104267329A CN 201410563203 A CN201410563203 A CN 201410563203A CN 104267329 A CN104267329 A CN 104267329A
- Authority
- CN
- China
- Prior art keywords
- transistor
- voltage
- control signal
- selector switch
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2608—Circuits therefor for testing bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses a transistor test circuit and a corresponding test method. The transistor test circuit is used for testing a group of transistors, wherein the transistors include at least two transistors. The transistor test circuit comprises a first power voltage end, a first control signal end and a group of testing terminals, wherein the first power voltage end is connected to first electrodes of all the transistors; the first control signal end is connected to control electrodes of all the transistors; the testing terminals include at least two testing terminals, and all the testing terminals are connected to second electrodes of all the transistors respectively. According to the transistor test circuit, the bias voltage characteristics of the transistors can be tested simultaneously; besides, the current characteristics of all the transistors can be tested respectively; as a result, the condition that the bias voltage characteristics of the transistors are tested one by one is avoided, so the waiting time is shortened, and the testing efficiency is improved.
Description
Technical field
The disclosure relates to transistor testing field, is specifically related to a kind of transistor testing circuit and corresponding method of testing.
Background technology
As the device that electronic applications is conventional, the application of various transistor is very extensive.As the product of electronics industry batch production, the such as current various thin film transistor (TFT) TFT, metal-oxide semiconductor (MOS) MOS transistor etc. used in a large number in field of liquid crystal display, usually need to test its various electrical characteristics, to ensure when being applied in electronic equipment, it has required performance and reliable quality.At present, when testing transistor, normally first one by one bias voltage characteristic test being carried out to single transistor, then carrying out testing current.For MOS transistor, because General Requirements is under various bias condition, such as fix the voltage of a certain electrode of MOS transistor, and change the voltage at other the two poles of the earth, test its bias conditions, the time that the test due to each MOS transistor needs is long, and the transistor in addition will tested is a lot, make testing efficiency very low, greatly reduce the efficiency of subsequent production flow process.Fig. 1 shows a kind of known transistor testing connecting circuit, wherein, for nmos pass transistor, the drain electrode of this nmos pass transistor is connected to supply voltage Vd, its grid is connected to grid line control signal Vg, and its source electrode is connected to test lead, according to test needs, change the voltage being applied to respective electrode, thus test its bias conditions.Owing to once can only carry out the test of bias conditions to a transistor, cause testing efficiency very low.Similarly, when carrying out bias voltage characteristic test to transistor, general is also test respectively each transistor, for nmos pass transistor, the drain electrode of nmos pass transistor is connected to supply voltage Vd, its grid is connected to grid line control signal Vg, and by its source electrode floating, according to test needs, change and be applied to the voltage of respective electrode, thus test its bias voltage situation under source electrode floating state.Owing to once can only carry out the test of bias voltage situation to a transistor, cause testing efficiency very low.
Summary of the invention
For above problem, present disclosure proposes a kind of transistor testing circuit and method of testing, the bias voltage characteristic of multiple transistor can be tested simultaneously.
Particularly, according to an aspect of the present disclosure, propose a kind of for transistor testing circuit, for testing a group transistor, wherein this group transistor comprises at least two transistors, and described transistor testing circuit comprises: the first power voltage terminal, is connected to the first pole of each transistor; First control signal end, is connected to the control pole of each transistor; And one group of calibrating terminal, comprise at least two calibrating terminals, wherein, each calibrating terminal is connected respectively to the second pole of each transistor.
Alternatively, in above-mentioned transistor testing circuit, when testing the bias voltage characteristic of each transistor at the same time, the first power voltage terminal is configured to provide the first voltage to the first pole of each transistor; First control signal end is configured to provide the first control signal to the control pole of each transistor; Each calibrating terminal is configured to floating state.
Alternatively, in above-mentioned transistor testing circuit, when testing the current characteristics of each transistor respectively, the first power voltage terminal is configured to provide the first voltage to the first pole of each transistor; First control signal end is configured to provide the first control signal to the control pole of each transistor; The calibrating terminal that tested transistor correspondence connects is configured to access test voltage, and other calibrating terminal is configured to floating state.
In addition, according to the another kind of scheme that the disclosure proposes, by the orderly control to the transistor group and selector switch unit that comprise multiple tested transistor, can realize being biased voltage to multiple tested transistor simultaneously, and after bias voltage effect completes, test the current characteristics of each transistor more respectively, avoid the shortcoming multiple tested transistor being loaded one by one to the length consuming time that bias voltage causes, thus improve testing efficiency.
Particularly, above-mentioned transistor testing circuit can also comprise: selector switch unit, and described selector switch unit comprises at least two selector switch; Second source voltage end, is connected to the first end of each selector switch; Second control signal end, is connected to the control end of each selector switch; Wherein, the second end of each selector switch connects each calibrating terminal respectively.
Alternatively, in above-mentioned transistor testing circuit, each selector switch is switching transistor, and the control end of each selector switch is the grid of switching transistor, its first end be switching transistor source electrode or drain electrode in one, its second end be switching transistor source electrode or drain electrode in another.
Alternatively, in above-mentioned transistor testing circuit, when testing the bias voltage characteristic of each transistor at the same time, the first power voltage terminal is configured to provide the first voltage to the first pole of each transistor; Second source voltage end is configured to provide the second voltage to the first end of each selector switch or do not provide voltage; First control signal end is configured to provide the first control signal to the control pole of each transistor; Second control signal end is configured to provide the second control signal to each connected selector switch, opens each selector switch, thus the second pole of each transistor is connected to second source voltage end; And each calibrating terminal is configured to floating state.
Alternatively, in above-mentioned transistor testing circuit, the first control signal applied when carrying out forward bias test to each transistor is contrary with the level each transistor being carried out to the first control signal applied when reverse bias is tested.
Alternatively, in above-mentioned transistor testing circuit, when the current characteristics of difference test transistor, the first power voltage terminal is configured to provide the first voltage to the first pole of each transistor; Second source voltage end is configured to provide the second voltage to the first end of each selector switch or do not provide voltage; First control signal end is configured to provide the first control signal to the control pole of each transistor; Second control signal end is configured to provide the second control signal to each connected selector switch, turns off each selector switch connected, thus disconnects the second pole of each transistor and the connection of second source voltage end; And the calibrating terminal to be connected with tested transistor is configured to provide test voltage, other calibrating terminal is configured to floating.
Alternatively, in above-mentioned transistor testing circuit, the level of the first voltage and the level of the second voltage are different, and the first voltage, test voltage and/or the first control signal are configured to need to change its level in time according to test.
Alternatively, in above-mentioned transistor testing circuit, the level of the second voltage and the level of test voltage are configured to identical.
According to another aspect of the present disclosure, additionally provide a kind of testing method for transistors, for testing a group transistor, wherein this group transistor comprises at least two transistors, and described testing method for transistors comprises: the first pole of each transistor is connected to the first power voltage terminal; The control pole of each transistor is connected to the first control signal end; And the second pole of each transistor is connected respectively to each calibrating terminal; Wherein provide the first voltage by the first power voltage terminal to the first pole of each transistor; The first control signal is provided to the control pole of each transistor by the first control signal end.
Alternatively, when above-mentioned testing method for transistors tests the bias voltage characteristic of each transistor at the same time, can also comprise: each calibrating terminal is configured to floating state, and according to test needs, change the level of the first voltage and/or the first control signal.
Alternatively, above-mentioned testing method for transistors is when testing the current characteristics of each transistor respectively, can also comprise: the calibrating terminal access test voltage that tested transistor correspondence is connected, other calibrating terminal is configured to floating state, and according to test needs, change the level of the first voltage, test voltage and/or the first control signal.
According to embodiment of the present disclosure, by controlling in order the group transistor comprising multiple tested transistor, the bias voltage characteristic of simultaneously testing multiple transistor can be realized, and the current characteristics of each transistor can be tested respectively, avoid and bias voltage characteristic is tested one by one to multiple transistor, thus decrease the stand-by period, improve testing efficiency.
Alternatively, above-mentioned testing method for transistors also comprises: the second pole of each transistor is connected to second source voltage end respectively by selector switch unit; Wherein, described selector switch unit comprises at least two selector switch; Wherein, the first end of each selector switch is connected to described second source voltage end; The control end of each selector switch is connected to the second control signal end; And the second end of each selector switch is connected respectively to each calibrating terminal; Wherein, the second voltage is provided by the first end of second source voltage end to each selector switch or does not provide voltage; The second control signal is provided to each connected selector switch, conducting or turn off each selector switch by the second control signal end.
Alternatively, above-mentioned testing method for transistors can also comprise: when testing each transistor biased at the same time, the second control signal is provided to each connected selector switch by the second control signal end, open each selector switch, thus the second pole of each transistor is connected to second source voltage end; And each calibrating terminal is configured to floating state.
Alternatively, in above-mentioned testing method for transistors, when testing the bias voltage characteristic of multiple transistor at the same time, according to test needs, change the level of the first voltage, the first control signal and/or the second voltage.
Alternatively, in above-mentioned testing method for transistors, the first control signal applied when carrying out forward bias test to each transistor is contrary with the level each transistor being carried out to the first control signal applied when reverse bias is tested.
Alternatively, in above-mentioned testing method for transistors, when the current characteristics of difference test transistor, the second control signal is provided to each connected selector switch by the second control signal end, turn off each selector switch connected, thus disconnect the second pole of each transistor and the connection of second source voltage end; And provide test voltage to the calibrating terminal be connected with tested transistor, and other calibrating terminal is configured to floating.
Alternatively, in above-mentioned testing method for transistors, when the current characteristics of difference test transistor, it, according to test needs, changes the level of the first voltage, test voltage and/or the first control signal.
In addition, according to embodiment of the present disclosure, by the orderly control to the group transistor and selector switch unit that comprise multiple tested transistor, can realize applying bias voltage to multiple transistor simultaneously, after bias voltage effect completes, the current characteristics of each transistor can be tested respectively, avoid and apply bias voltage one by one to tested multiple transistors, thus decrease the stand-by period, improve testing efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, be briefly described below by the accompanying drawing of embodiment, apparently, the accompanying drawing in the following describes only relates to some embodiments of the present invention, but not limitation of the present invention.
Fig. 1 shows a kind of syndeton of known transistor testing circuit;
Fig. 2 is a kind of according to an embodiment of the invention block diagram of transistor testing circuit;
Fig. 3 is the johning knot composition of the transistor testing circuit corresponding to Fig. 2 according to an embodiment of the invention;
Fig. 4 is the block diagram of another kind of according to an embodiment of the invention transistor testing circuit;
Fig. 5 is the schematic johning knot composition of the transistor testing circuit corresponding to Fig. 4 according to an embodiment of the invention;
Fig. 6 is the johning knot composition of the transistor testing circuit corresponding to Fig. 5 according to an embodiment of the invention;
Fig. 7 is the johning knot composition of another transistor testing circuit according to an embodiment of the invention;
Fig. 8 is a kind of according to an embodiment of the invention process flow diagram of testing method for transistors; And
Fig. 9 is the process flow diagram of another kind of according to an embodiment of the invention testing method for transistors;
Embodiment
Be clearly and completely described the technical scheme in the embodiment of the present invention below in conjunction with accompanying drawing, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, also belong to the scope of protection of the invention.
Fig. 2 shows a kind of according to an embodiment of the invention block diagram of transistor testing circuit, and the group transistor comprising multiple tested transistor is connected the first power voltage terminal PV1, the first control signal end CTR1, and between test lead subgroup TP.
Correspondingly, Fig. 3 shows the concrete syndeton of the transistor testing circuit corresponding to Fig. 2 according to an embodiment of the invention.As shown in Figure 3, this group transistor group comprises multiple tested transistor M1, M2, M3 ..., test lead subgroup TP comprises multiple calibrating terminal TP1, TP2, TP3 ... for nmos pass transistor, transistor M1, M2, M3 ... drain electrode be all connected to the first power voltage terminal PV1, its source electrode is connected respectively to multiple calibrating terminal TP1, TP2, TP3 ... its grid is all connected to the first control signal end CTR1, wherein the first power voltage terminal access supply voltage V1, and the first control signal end CTR1 accesses the first control signal Vg.
When to test the bias voltage characteristic of multiple transistor simultaneously, the equal floating of calibrating terminal that tested transistor is connected, supply voltage V1 can be high level, and change can be needed according to test, first control signal Vg can be high level, and change can be needed according to test, due to tested transistor source floating, the bias voltage situation of transistor in this case can be obtained.
When the current characteristics of difference test transistor, by tested transistor (such as, transistor M3) calibrating terminal that connects is (such as, TP3) connecting test voltage (such as, ground level), the calibrating terminal floating that other transistor correspondence connects, supply voltage V1 is high level, and change can be needed according to test, first control signal Vg is high level, and change can be needed according to test, tested transistor is flow through (such as by probe test, M3) electric current, thus obtain the electric current of tested transistor and corresponding drain electrode, the relation of source electrode and/or grid voltage, obtain corresponding current characteristics.
Certainly, when the current characteristics of test transistor, also calibrating terminal corresponding for tested transistor can be connect test voltage (such as, high level), supply voltage V1 is earth level, first control signal Vg is high level, and change can be needed according to test, flow through the electric current of tested transistor by probe test, thus obtain the electric current of tested transistor and corresponding drain electrode, the relation of source electrode and/or grid voltage, obtains corresponding current characteristics.
Fig. 4 illustrates the block diagram of another kind of according to an embodiment of the invention transistor testing circuit, compared with the block diagram of the illustrated transistor testing circuit of Fig. 2, the key distinction is to add selector switch unit and corresponding second control signal end CTR2 and second source voltage end PV2.
Particularly, as shown in Figure 5, selector switch unit comprises multiple selector switch S1, S2, S3 ..., the first end of each selector switch is connected to second source voltage end PV2, second end of each selector switch is connected respectively to each calibrating terminal, and the control end of each selector switch is connected to the second control signal end CTR2.
For switching transistor as above-mentioned selector switch, further describe the principle of work of the transistor testing circuit according to the present embodiment.As shown in Figure 6, selector switch unit comprises multiple switching transistor TS1, TS2, TS3,, for nmos switch transistor, the drain electrode of each switching transistor is connected respectively to each calibrating terminal, the grid of each switching transistor is connected to the second control signal end CTR2, and the source electrode of each switching transistor is connected to second source voltage end PV2.
When being biased voltage to multiple test transistor simultaneously, the first power voltage terminal PV1 earth level (0V), second source voltage end PV2 can floating or connect high level, needs setting according to test; Open selector switch unit, particularly, high level signal is accessed the second control signal end CTR2, make all conductings of each switching transistor, the first control signal Vg is accessed the first control signal end CTR1, and setting can be needed according to test.Such as, if need to test forward bias, then Vg>0, otherwise, if need test negative sense to be biased, then Vg<0; Now, the whole floating of all calibrating terminals, namely not to calibrating terminal input test voltage;
Certainly, when applying bias voltage to test transistor, also can exchange the level that the first power voltage terminal PV1 and second source voltage end PV2 accesses, other signal annexation can remain unchanged.Because the first power voltage terminal PV1 is different with the level that second source voltage end PV2 accesses, when carrying out bias voltage characteristic test, the partial pressure effects of transistor be considered, i.e. the partial pressure effects of test transistor and corresponding switching transistor.
When the current characteristics of difference test transistor, the first power voltage terminal PV1 connects high level, and can change as required; Second source voltage end PV2 can floating, connect high level or ground level; Close selector switch unit, particularly, low level signal is accessed the second control signal end CTR2, each switching transistor is all turned off; First control signal Vg is accessed the first control signal end CTR1, and change can be needed according to test; The calibrating terminal connecting test voltage (such as ground level) that the transistor correspondence that will need to test its current characteristics connects, and by the electric current of this transistor of probe test, the calibrating terminal floating that other transistors correspondences connect.Alternatively, the level that second source voltage end PV2 accesses is identical with the test voltage that calibrating terminal connects, to reduce the impact of leakage current.
Certainly, when the current characteristics of difference test transistor, first power voltage terminal PV1 also can earth level, now, need the calibrating terminal connecting test voltage (such as high level) that tested transistor correspondence connects, and need change according to test, test and record the electric current of tested transistor.
In the above description, for nmos pass transistor, describe the transistor testing circuit according to the embodiment of the present invention and principle of work thereof in detail.In fact, PMOS transistor above-mentioned nmos pass transistor can also be replaced to realize the transistor testing circuit of the embodiment of the present invention.Such as, Fig. 7 shows the transistor testing circuit that a kind of application PMOS transistor according to the embodiment of the present invention realizes, its principle of work is similar with the transistor testing circuit adopting nmos pass transistor to realize, just respective transistor conducting and close level in contrast, specific works principle no longer repeats.
In addition, although in embodiments of the present invention, as shown in Figures 6 and 7, switching transistor is identical with the type of tested transistor, such as, is nmos pass transistor or is PMOS transistor, but in fact, as required, the type of switching transistor and tested transistor also can be different.
According to one embodiment of the invention, also proposed a kind of method for test transistor, using nmos pass transistor as test transistor, as shown in Figure 8, comprise the following steps: the drain electrode of each transistor is connected to the first power voltage terminal PV1, the grid of each transistor is connected to the first control signal end CTR1, and the source electrode of each transistor is connected respectively to each calibrating terminal TP; Apply the first voltage V1 to the first power voltage terminal PV1, apply the first control signal Vg to the first control signal end CTR1.
According to one embodiment of the invention, during the bias voltage characteristic of test transistor at the same time, said method specifically comprises: provide the first voltage by the first power voltage terminal PV1 to the drain electrode of each transistor; Control signal is provided to the grid of each transistor by the first control signal end CTR1; And each calibrating terminal is configured to floating state; Wherein, change the level of the first voltage and control signal as required, with test transistor under source electrode floating state, the bias voltage situation under different drain electrodes and/or grid level.
Particularly, as mentioned above, when testing the bias voltage characteristic of multiple transistor at the same time, the equal floating of calibrating terminal that tested transistor is connected, the first voltage V1 can be high level, and can need change according to test, first control signal Vg can be high level, and change can be needed according to test, due to tested transistor source floating, the bias voltage situation of transistor in this case can be obtained.
According to one embodiment of the invention, when the current characteristics of respectively test transistor, said method specifically comprises: provide the first voltage by the first power voltage terminal PV1 to the drain electrode of each transistor; There is provided the first control signal to open tested transistor by the first control signal end CTR1 to the grid of each transistor; And provide test voltage to the calibrating terminal that tested transistor correspondence connects, and the calibrating terminal that other transistor correspondence connects is configured to floating state; Wherein, change the level of the first voltage, test voltage and/or control signal as required, the electric current of tested transistor is flow through in test, thus obtains the electric current of tested transistor and corresponding drain electrode, the relation of source electrode and/or grid voltage, obtains corresponding current characteristics.
According to one embodiment of the invention, when the current characteristics of difference test transistor, by tested transistor (such as, transistor M3) calibrating terminal that connects is (such as, TP3) ground level is accessed, the calibrating terminal floating that other transistor correspondence connects, first voltage V1 is high level, and change can be needed according to test, first control signal Vg is that high level is number to open tested transistor, and change can be needed according to test, the electric current of tested transistor is flow through by probe test, thus obtain the electric current of tested transistor and corresponding drain electrode, the relation of source electrode and/or grid voltage, obtain corresponding current characteristics.
Certainly, when the current characteristics of test transistor, also calibrating terminal corresponding for tested transistor can be connect high level, first voltage V1 is earth level, the first control signal Vg be high level to open tested transistor, and can according to test need change, the electric current of tested transistor is flow through by probe test, thus obtain the electric current of tested transistor and corresponding drain electrode, the relation of source electrode and/or grid voltage, obtain corresponding current characteristics.
As mentioned above, according to this embodiment of the invention, by controlling in order the group transistor comprising multiple tested transistor, the bias voltage characteristic of simultaneously testing multiple transistor can be realized, and the current characteristics of each transistor can be tested respectively, avoid and bias voltage characteristic is tested one by one to multiple transistor, thus decrease the stand-by period, improve testing efficiency.
According to one embodiment of the invention, also proposed a kind of method for test transistor.Particularly, for nmos pass transistor, as shown in Figure 9, the method comprises: the drain electrode of each transistor is connected to the first power voltage terminal, the grid of each transistor is connected to the first control signal end; And the source electrode of each transistor is connected respectively to each calibrating terminal; Each calibrating terminal is connected to second source voltage end respectively by selector switch unit; Wherein, described selector switch unit comprises multiple selector switch; Wherein, the first end of each selector switch is connected to described second source voltage end; The control end of each selector switch is connected to the second control signal end; And the second end of each selector switch is connected respectively to each calibrating terminal; Wherein, apply the first voltage V1 to the first power voltage terminal PV1, apply the first control signal Vg to the first control signal end CTR1, the calibrating terminal connected to tested transistor applies test voltage or by its floating; Apply the second control signal to the second control signal end, provide the second voltage or by its floating to second source voltage end.
Alternatively, each selector switch above-mentioned is switching transistor, and wherein the first end of each selector switch is the source electrode of switching transistor, and the second end of selector switch is the drain electrode of switching transistor, and the control end of selector switch is the grid of switching transistor.
Because the source electrode of the switching transistor that adopts here, drain electrode are symmetrical, so its source electrode, drain electrode can be exchanged.In embodiments of the present invention, for distinguishing transistor the two poles of the earth except grid, wherein will be called source electrode in a pole, another pole is called drain electrode.If choose source electrode as signal input part, drain as signal output part, vice versa.
According to one embodiment of the invention, during the bias voltage characteristic of test transistor at the same time, said method specifically comprises: provide the first voltage by the first power voltage terminal to the drain electrode of each transistor, the first control signal is provided to the grid of each transistor by the first control signal end, and the size of change first control signal can be needed according to test, each calibrating terminal is configured to floating state, that is, not to calibrating terminal input test voltage; The second control signal is provided to the grid of each connected switching transistor by the second control signal end, open each switching transistor, thus the source electrode of each transistor is connected to second source voltage end, the second voltage is provided or by its floating to the source electrode of each switching transistor by second source voltage end, when can obtain thus to tested transistor applying bias voltage, its drain electrode, source electrode, and/or the relation property of grid voltage and phase induced current.
Alternatively, according to above-mentioned method of testing, the first control signal applied when carrying out forward bias test to transistor is contrary with level transistor being carried out to the first control signal applied when reverse bias is tested.
Particularly, as mentioned above, when being biased voltage to multiple test transistor simultaneously, the first power voltage terminal PV1 earth level (0V), second source voltage end PV2 can floating or connect high level, needs setting according to test; Open selector switch unit, particularly, the second control signal of high level is accessed the second control signal end CTR2, make all conductings of each switching transistor, the first control signal Vg is accessed the first control signal end CTR1, and setting can be needed according to test.Such as, if need to test forward bias, then Vg>0, otherwise, if need test negative sense to be biased, then Vg<0; Now, the whole floating of all calibrating terminals;
Certainly, when applying bias voltage to test transistor, also can exchange the level that the first power voltage terminal PV1 and second source voltage end PV2 accesses, other signal annexation can remain unchanged.Because the first power voltage terminal PV1 is different with the level that second source voltage end PV2 accesses, when carrying out bias voltage characteristic test, the partial pressure effects of transistor be considered, i.e. the partial pressure effects of test transistor and corresponding switching transistor.
According to one embodiment of the invention, when the current characteristics of difference test transistor, said method specifically comprises: provide the first voltage by the first power voltage terminal to the drain electrode of each transistor, the first control signal is applied to the grid of tested transistor by the first control signal end, the second control signal is applied to the grid of each connected switching transistor by the second control signal end, turn off all switching transistors, thus disconnect the electrical connection of each calibrating terminal and second source voltage end, and provide test voltage to the calibrating terminal be connected with the transistor of tested current characteristics, and test the current characteristics of this transistor, and other calibrating terminal is configured to floating.
Particularly, when needing the current characteristics of test transistor respectively, the first power voltage terminal PV1 connects high level, and can change as required; Second source voltage end PV2 can floating, connect high level or ground level; Close selector switch unit, particularly, low level second control signal is accessed the second control signal end CTR2, each selector switch is all turned off; First control signal Vg is accessed the first control signal end CTR1, and change can be needed according to test; By the calibrating terminal connecting test voltage (such as ground level) that the transistor of its current characteristics tested correspondence connects, and by the electric current of this transistor of probe test, the calibrating terminal floating that other transistors correspondences connect.Alternatively, the level that second source voltage end PV2 accesses is identical with the test voltage that calibrating terminal connects, to reduce the impact of leakage current.
Certainly, when the current characteristics of difference test transistor, first power voltage terminal PV1 also can earth level, now, the calibrating terminal connecting test voltage (such as high level) of the transistor correspondence connection of tested current characteristics, and need change according to test, test and record the electric current of tested transistor.
As mentioned above, according to this embodiment of the invention, by the orderly control to the group transistor and selector switch unit that comprise multiple tested transistor, can realize applying bias voltage to multiple transistor simultaneously, after bias voltage effect completes, the current characteristics of each transistor can be tested respectively, avoid and apply bias voltage one by one to tested multiple transistors, thus decrease the stand-by period, improve testing efficiency.
Above the transistor testing circuit proposed in the embodiment of the present invention and method of testing are described in detail.But, as understood by those skilled in the art, the concrete structure of above-mentioned test circuit and each step of corresponding detection method are only used to the principle of work that the embodiment of the present invention is described, should not be regarded as is limitation of the present invention, and require and embody rule occasion according to corresponding, one of them or multiple parts and/or step also can combination with one another or omissions.
One of ordinary skill in the art will appreciate that all or part of flow process realized in above-described embodiment method, that the hardware that can carry out instruction relevant by computer program has come, described program can be stored in a computer read/write memory medium, this program, when performing, can comprise the flow process of the embodiment as above-mentioned each side method.Wherein, described storage medium can be disk, CD, ROM (read-only memory) (ROM) or random access memory (RAM) etc.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in technical scope disclosed in the embodiment of the present invention; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (19)
1. a transistor testing circuit, for testing a group transistor, wherein, this group transistor comprises at least two transistors, and described transistor testing circuit comprises:
First power voltage terminal, is connected to the first pole of each transistor;
First control signal end, is connected to the control pole of each transistor; And
One group of calibrating terminal, comprises at least two calibrating terminals, and wherein, each calibrating terminal is connected respectively to the second pole of each transistor.
2. transistor testing circuit according to claim 1, also comprises:
Selector switch unit, described selector switch unit comprises at least two selector switch;
Second source voltage end, is connected to the first end of each selector switch;
Second control signal end, is connected to the control end of each selector switch;
Wherein, the second end of each selector switch connects each calibrating terminal respectively.
3. transistor testing circuit according to claim 2, wherein, each selector switch described is switching transistor, the control end of each selector switch is the grid of switching transistor, its first end be switching transistor source electrode or drain electrode in one, its second end be switching transistor source electrode or drain electrode in another.
4. transistor testing circuit according to claim 1, wherein, when testing the bias voltage characteristic of each transistor at the same time,
First power voltage terminal is configured to provide the first voltage to the first pole of each transistor;
First control signal end is configured to provide the first control signal to the control pole of each transistor;
Each calibrating terminal is configured to floating state.
5. transistor testing circuit according to claim 1, wherein, when testing the current characteristics of each transistor respectively,
First power voltage terminal is configured to provide the first voltage to the first pole of each transistor;
First control signal end is configured to provide the first control signal to the control pole of each transistor;
The calibrating terminal that tested transistor correspondence connects is configured to access test voltage, and other calibrating terminal is configured to floating state.
6. transistor testing circuit according to claim 2, wherein, when testing the bias voltage characteristic of each transistor at the same time,
First power voltage terminal is configured to provide the first voltage to the first pole of each transistor;
Second source voltage end is configured to provide the second voltage to the first end of each selector switch or do not provide voltage;
First control signal end is configured to provide the first control signal to the control pole of each transistor;
Second control signal end is configured to provide the second control signal to each connected selector switch, opens each selector switch, thus the second pole of each transistor is connected to second source voltage end; And
Each calibrating terminal is configured to floating state.
7. transistor testing circuit according to claim 6, wherein, the first control signal applied when carrying out forward bias test to each transistor is contrary with the level each transistor being carried out to the first control signal applied when reverse bias is tested.
8. transistor testing circuit according to claim 2, wherein, when the current characteristics of difference test transistor,
First power voltage terminal is configured to provide the first voltage to the first pole of each transistor;
Second source voltage end is configured to provide the second voltage to the first end of each selector switch or do not provide voltage;
First control signal end is configured to provide the first control signal to the control pole of each transistor;
Second control signal end is configured to provide the second control signal to each connected selector switch, turns off each selector switch connected, thus disconnects the second pole of each transistor and the connection of second source voltage end; And
The calibrating terminal be connected with tested transistor is configured to provide test voltage, and other calibrating terminal is configured to floating.
9. transistor testing circuit according to claim 8, wherein, the level of the first voltage and the level of the second voltage are different, and the first voltage, test voltage and/or the first control signal are configured to need to change its level in time according to test.
10. transistor testing circuit according to claim 8, wherein, the level of the second voltage and the level of test voltage are configured to identical.
11. 1 kinds of testing method for transistors, for testing a group transistor, wherein, this group transistor comprises at least two transistors, and described testing method for transistors comprises:
First pole of each transistor is connected to the first power voltage terminal;
The control pole of each transistor is connected to the first control signal end; And
Second pole of each transistor is connected respectively to each calibrating terminal; Wherein
The first voltage is provided to the first pole of each transistor by the first power voltage terminal;
The first control signal is provided to the control pole of each transistor by the first control signal end.
12. testing method for transistors according to claim 11, wherein, when testing the bias voltage characteristic of each transistor at the same time, also comprise:
Each calibrating terminal is configured to floating state, and according to test needs, changes the level of the first voltage and/or the first control signal.
13. testing method for transistors according to claim 11, wherein, when testing the current characteristics of each transistor respectively,
The calibrating terminal access test voltage tested transistor correspondence connected, other calibrating terminal is configured to floating state, and according to test needs, changes the level of the first voltage, test voltage and/or the first control signal.
14. testing method for transistors according to claim 11, also comprise:
Second pole of each transistor is connected to second source voltage end respectively by selector switch unit; Wherein, described selector switch unit comprises at least two selector switch;
Wherein, the first end of each selector switch is connected to described second source voltage end;
The control end of each selector switch is connected to the second control signal end; And
Second end of each selector switch is connected respectively to each calibrating terminal;
Wherein, the second voltage is provided by the first end of second source voltage end to each selector switch or does not provide voltage;
The second control signal is provided to each connected selector switch, conducting or turn off each selector switch by the second control signal end.
15. testing method for transistors according to claim 14, also comprise: when testing each transistor biased at the same time,
There is provided the second control signal by the second control signal end to each connected selector switch, open each selector switch, thus the second pole of each transistor is connected to second source voltage end; And
Each calibrating terminal is configured to floating state.
16. testing method for transistors according to claim 15, wherein, according to test needs, change the level of the first voltage, the first control signal and/or the second voltage.
17. testing method for transistors according to claim 16, wherein, the first control signal applied when carrying out forward bias test to each transistor is contrary with the level each transistor being carried out to the first control signal applied when reverse bias is tested.
18. testing method for transistors according to claim 14, wherein, when the current characteristics of difference test transistor,
There is provided the second control signal by the second control signal end to each connected selector switch, turn off each selector switch connected, thus disconnect the second pole of each transistor and the connection of second source voltage end; And
There is provided test voltage to the calibrating terminal be connected with tested transistor, and other calibrating terminal is configured to floating.
19. testing method for transistors according to claim 18, wherein, according to test needs, change the level of the first voltage, test voltage and/or the first control signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410563203.1A CN104267329B (en) | 2014-10-21 | 2014-10-21 | Transistor testing circuit and method of testing |
| US14/573,100 US10006957B2 (en) | 2014-10-21 | 2014-12-17 | Circuit and method for testing transistor(s) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410563203.1A CN104267329B (en) | 2014-10-21 | 2014-10-21 | Transistor testing circuit and method of testing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104267329A true CN104267329A (en) | 2015-01-07 |
| CN104267329B CN104267329B (en) | 2017-03-15 |
Family
ID=52158869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410563203.1A Active CN104267329B (en) | 2014-10-21 | 2014-10-21 | Transistor testing circuit and method of testing |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US10006957B2 (en) |
| CN (1) | CN104267329B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109347065A (en) * | 2018-11-09 | 2019-02-15 | 浙江国自机器人技术有限公司 | A kind of three-phase drive device detection method, system, equipment and readable storage medium storing program for executing |
| CN110379392A (en) * | 2019-07-24 | 2019-10-25 | 京东方科技集团股份有限公司 | Array substrate, display panel and its display methods |
| CN112103199A (en) * | 2019-06-17 | 2020-12-18 | 京东方科技集团股份有限公司 | Display substrate, display device and performance test method of transistor |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6701777B2 (en) | 2016-02-15 | 2020-05-27 | セイコーエプソン株式会社 | Electro-optical device, electronic equipment |
| CN112151102B (en) * | 2019-06-28 | 2022-09-27 | 中电海康集团有限公司 | Test structure and test method |
| CN114167254B (en) * | 2021-10-31 | 2023-12-12 | 重庆台冠科技有限公司 | First TP testing tool and TP testing device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6425070A (en) * | 1987-07-20 | 1989-01-27 | Sanyo Electric Co | Method for measuring characteristic of field-effect transistor |
| US20040148123A1 (en) * | 2003-01-20 | 2004-07-29 | Elpida Memory, Inc. | Semiconductor device having a test circuit for testing an output circuit |
| CN200976035Y (en) * | 2006-12-07 | 2007-11-14 | 比亚迪股份有限公司 | Device for testing power field-effect transistor static parameter |
| CN101136347A (en) * | 2007-09-29 | 2008-03-05 | 上海集成电路研发中心有限公司 | MOS pipe interface state testing method |
| CN101629979A (en) * | 2008-07-15 | 2010-01-20 | 中芯国际集成电路制造(上海)有限公司 | Testing device |
| CN103064000A (en) * | 2013-01-05 | 2013-04-24 | 北京大学 | Threshold voltage distribution monitoring device and method of metal oxide semiconductor (MOS) tube array |
| CN103345914A (en) * | 2013-07-19 | 2013-10-09 | 深圳市华星光电技术有限公司 | Detection circuit for display panel |
| CN203705600U (en) * | 2014-01-26 | 2014-07-09 | 广东易事特电源股份有限公司 | Transistor test circuit |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5561373A (en) * | 1990-10-09 | 1996-10-01 | Fujitsu Limited | Method and device for detecting electrostatic stress applied to a product semiconductor device during each production process |
| KR100529615B1 (en) * | 2003-12-24 | 2005-11-17 | 동부아남반도체 주식회사 | Test circuit for measuring degradation of transistors |
| US7103861B2 (en) * | 2004-06-10 | 2006-09-05 | Chartered Semiconductor Manufacturing Ltd. | Test structure for automatic dynamic negative-bias temperature instability testing |
| US7365556B2 (en) * | 2004-09-02 | 2008-04-29 | Texas Instruments Incorporated | Semiconductor device testing |
| US8120356B2 (en) * | 2009-06-11 | 2012-02-21 | International Business Machines Corporation | Measurement methodology and array structure for statistical stress and test of reliabilty structures |
| KR101746197B1 (en) * | 2010-06-25 | 2017-06-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Manufacturing method and test method of semiconductor device |
| US9030221B2 (en) * | 2011-09-20 | 2015-05-12 | United Microelectronics Corporation | Circuit structure of test-key and test method thereof |
| US8643397B2 (en) * | 2011-09-26 | 2014-02-04 | Untied Microelectronics Corp. | Transistor array for testing |
| CN102928763B (en) * | 2012-11-28 | 2014-12-24 | 杭州广立微电子有限公司 | Addressing testing circuit for transistor key parameters and testing method thereof |
| KR101928815B1 (en) * | 2012-12-04 | 2018-12-13 | 한국전자통신연구원 | Electronic Device Reliability Measurement System |
| KR102037231B1 (en) * | 2013-12-23 | 2019-10-29 | 한국전자통신연구원 | Test device testing plurality of samples and operating method thereof |
| DE102014115204B4 (en) * | 2014-10-20 | 2020-08-20 | Infineon Technologies Ag | Testing of devices |
-
2014
- 2014-10-21 CN CN201410563203.1A patent/CN104267329B/en active Active
- 2014-12-17 US US14/573,100 patent/US10006957B2/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6425070A (en) * | 1987-07-20 | 1989-01-27 | Sanyo Electric Co | Method for measuring characteristic of field-effect transistor |
| US20040148123A1 (en) * | 2003-01-20 | 2004-07-29 | Elpida Memory, Inc. | Semiconductor device having a test circuit for testing an output circuit |
| CN200976035Y (en) * | 2006-12-07 | 2007-11-14 | 比亚迪股份有限公司 | Device for testing power field-effect transistor static parameter |
| CN101136347A (en) * | 2007-09-29 | 2008-03-05 | 上海集成电路研发中心有限公司 | MOS pipe interface state testing method |
| CN101629979A (en) * | 2008-07-15 | 2010-01-20 | 中芯国际集成电路制造(上海)有限公司 | Testing device |
| CN103064000A (en) * | 2013-01-05 | 2013-04-24 | 北京大学 | Threshold voltage distribution monitoring device and method of metal oxide semiconductor (MOS) tube array |
| CN103345914A (en) * | 2013-07-19 | 2013-10-09 | 深圳市华星光电技术有限公司 | Detection circuit for display panel |
| CN203705600U (en) * | 2014-01-26 | 2014-07-09 | 广东易事特电源股份有限公司 | Transistor test circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109347065A (en) * | 2018-11-09 | 2019-02-15 | 浙江国自机器人技术有限公司 | A kind of three-phase drive device detection method, system, equipment and readable storage medium storing program for executing |
| CN112103199A (en) * | 2019-06-17 | 2020-12-18 | 京东方科技集团股份有限公司 | Display substrate, display device and performance test method of transistor |
| CN112103199B (en) * | 2019-06-17 | 2024-02-23 | 京东方科技集团股份有限公司 | Display substrate, display device and performance test method of transistor |
| CN110379392A (en) * | 2019-07-24 | 2019-10-25 | 京东方科技集团股份有限公司 | Array substrate, display panel and its display methods |
| CN110379392B (en) * | 2019-07-24 | 2022-09-02 | 京东方科技集团股份有限公司 | Array substrate, display panel and display method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104267329B (en) | 2017-03-15 |
| US20160109504A1 (en) | 2016-04-21 |
| US10006957B2 (en) | 2018-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104267329A (en) | Transistor test circuit and method | |
| US10027329B2 (en) | NOR gate circuit, shift register, array substrate and display apparatus | |
| US9886879B2 (en) | Liquid crystal display and method for testing liquid crystal display | |
| KR102315421B1 (en) | Demultiplexer and display device including the same | |
| WO2015007079A1 (en) | Detection circuit used for display panel | |
| US9595215B2 (en) | Circuit for testing display panel, method for testing display panel, and display panel | |
| US20150022211A1 (en) | Detection circuit for display panel | |
| US9606645B2 (en) | Display apparatus and pixel driving method with current compensation function | |
| US10804259B2 (en) | Electrostatic protection circuit, display panel, and display apparatus | |
| CN104485058A (en) | Test circuit, array substrate and display device | |
| US11663943B2 (en) | Drive circuit and display panel | |
| CN103995369A (en) | Array substrate, display panel and test method thereof | |
| TW201729539A (en) | Power gating devices and methods | |
| KR100526576B1 (en) | High voltage transfer circuit | |
| CN105989876B (en) | Resistive memory system, driving circuit thereof and impedance setting method thereof | |
| US10263622B2 (en) | Semiconductor apparatus and method of controlling MOS transistor | |
| CN103219044B (en) | The reading circuit of Nonvolatile memory devices | |
| CN111366874A (en) | Electric leakage detection circuit, electric leakage detection device and electric leakage detection method for flash memory | |
| CN105096857A (en) | Grid driving circuit and liquid crystal display | |
| TWI553623B (en) | Driver circuit and control method thereof | |
| US9672899B2 (en) | Dual-inverter memory device and operating method thereof | |
| CN107611934A (en) | USB interface protection circuit and display device | |
| CN105679218A (en) | Time delay circuit and test tool | |
| TWI704564B (en) | Memory device and power control circuit thereof | |
| US20070133275A1 (en) | Low-power reading reference circuit for split-gate flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |