CN104253043A - Field stop type insulated gate bipolar transistor manufacturing method - Google Patents

Field stop type insulated gate bipolar transistor manufacturing method Download PDF

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Publication number
CN104253043A
CN104253043A CN201310271615.3A CN201310271615A CN104253043A CN 104253043 A CN104253043 A CN 104253043A CN 201310271615 A CN201310271615 A CN 201310271615A CN 104253043 A CN104253043 A CN 104253043A
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CN
China
Prior art keywords
layer
cut
type
substrate
type igbt
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Pending
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CN201310271615.3A
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Inventor
王万礼
邓小社
王根毅
芮强
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Wuxi CSMC Semiconductor Co Ltd
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Wuxi CSMC Semiconductor Co Ltd
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Priority to CN201310271615.3A priority Critical patent/CN104253043A/en
Publication of CN104253043A publication Critical patent/CN104253043A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333Vertical insulated gate bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)

Abstract

The invention discloses a field stop type insulated gate bipolar transistor manufacturing method. The method includes epitaxially growing and generating heavily doped N-type epitaxial layer on a substrate as a field stop layer, then epitaxially growing and generating slightly doped N-type epitaxial layer as a pressure resistant layer, performing the conventional front process, then perform back thinning process, injecting P-type impurity into the back and annealing to obtain a P-type collector area, and performing the conventional back metallizing process. The method has the advantages that the producing period is short, expensive high-energy ion injection equipment and laser annealing equipment are omitted, the thickness of the field stop layer and the concentration of the impurity can be controlled according to component requirements, the thinning process difficulty is reduced, the component performance is improved, and the process difficulty is lowered; the substrate can be selected freely, and the substrate with lower cost can be selected.

Description

Manufacture the method for field cut-off type igbt
Technical field
The present invention relates to technical field of semiconductor device, particularly the preparation method of a kind of cut-off type igbt.
Background technology
Igbt (Insulated Gate Bipolar Transistor, IGBT) be a kind of be compounded with power field effect pipe and power transistor advantage and a kind of NEW TYPE OF COMPOSITE device produced, it has the speed-sensitive switch of MOSFET and the low saturation voltage characteristic of voltage drive characteristics and bipolar transistor simultaneously and easily realizes the ability of larger current, both there is input impedance high, operating rate is fast, Heat stability is good and the simple advantage of drive circuit, there is again on state voltage low, withstand voltage height and bear the large advantage of electric current, this makes IGBT become the power electronic drive part of particularly attracting attention in field of power electronics in recent years, and obtain applying more and more widely.
The development of IGBT mainly experienced by punch (PT), non-punch (NPT) and field cut-off type (FS) three types.
PT-IGBT is with the heavily doped P-type monocrystalline of hundreds of micron thickness for substrate, and the heavily doped N-type epitaxy layer of epitaxial growth afterwards forms resilient coating and the lightly doped N-type epitaxy layer of epitaxial growth forms Withstand voltage layer, and Withstand voltage layer manufactures Facad structure.The IGBT of this structure, higher device temperature poor stability, is unfavorable for parallel operation.
There is NPT-IGBT in the 1980's ends.NPT-IGBT adopts lightly doped N-type monocrystalline to be substrate, and single crystalline substrate directly manufactures Facad structure, is thinned to withstand voltage required thickness, forms P collector region afterwards by ion implantation after Facad structure completes from the method for substrate back employing grinding, corrosion.The IGBT of this structure, because drift region is long, has the shortcoming that forward conduction voltage drop is larger.
Problems existing in this traditional NPT-IGBT, is improved by adding an extra play between its drift region and collector region.This extra play is called as field cut-off (Field Stop, FS) layer, and it is N-type doping.The doping accumulated dose of this one deck is designed to make electric field strength substantially be reduced to zero in this one deck.Below this layer, in substrate, the reduction of electric field strength can be ignored in other words, and thus, voltage blocking capability and the substrate thickness of IGBT no longer include relation, and therefore substrate can grind thinner.This just makes IGBT have very low saturation voltage, thus has very low on-state loss.Here it is has the FS-IGBT of a cutoff layer.
Usually employing first does Facad structure at present, and carry out backside particulate injection after thinning back side, the mode of then laser annealing manufactures a cutoff layer.Owing to protecting Facad structure, annealing temperature can not be too high, and now impurity activation rate is very low, affects device performance.And backside particulate injection mode cannot make impurity deep layer advance, can only obtain layer FS layer at back, thinner FS layer can impact device performance.Also have by spreading for a long time and pushing away the method that trap forms field cutoff layer and then epitaxial growth Withstand voltage layer, but this kind of method production cycle is longer, CONCENTRATION DISTRIBUTION is undesirable, and concentration gradient is comparatively large, controls thickness thinning and also there is difficulty.And above-mentioned backside particulate injects and laser annealing technique also needs energetic ion injection device costly and laser annealing apparatus, development cost is larger.
Summary of the invention
Based on this, be necessary to provide a kind of method using conventional equipment conveniently to manufacture to have the field cut-off type igbt of ideal field cutoff layer.
Manufacture a method for cut-off type igbt, comprise the following steps:
Substrate is provided;
Heavily doped N-type epitaxy layer is formed, as field cutoff layer in described substrate face epitaxial growth;
In described field, cutoff layer Epitaxial growth forms lightly doped N-type epitaxy layer, as Withstand voltage layer;
Described Withstand voltage layer manufactures the Facad structure of described field cut-off type igbt;
Described substrate is started from the back side carry out reduction processing;
From described thinning after substrate back carry out P type ion implantation and anneal;
Back face metalization is carried out to described substrate back.
Wherein in an embodiment, the scope of the thickness of described field cutoff layer is 5 ~ 200 microns, and the scope of resistivity is 0.001 ~ 200 ohm meter.
Wherein in an embodiment, the scope of the thickness of described Withstand voltage layer is 5 ~ 400 microns, and the scope of resistivity is 0.001 ~ 200 ohm meter.
Wherein in an embodiment, described Facad structure comprises grid structure, and grid structure is planar gate structure, trench gate structure, or the grid structure containing buried regions based on planar gate or trench gate structure.
Wherein in an embodiment, described substrate is silicon, carborundum, GaAs or gallium nitride.
Wherein in an embodiment, in described heavy doping and light dope technique, impurity used is the impurity with donor level
Wherein in an embodiment, the described impurity with donor level is phosphorus or arsenic.
Wherein in an embodiment, described extension is vapour phase epitaxy, liquid phase epitaxy, molecular beam epitaxy or chemical beam epitaxy.
The method of above-mentioned manufacture field cut-off type igbt, after adopting first extension field cutoff layer, the simple method of conventional NPT-IGBT manufacturing process realizes, due to do not need to spread for a long time and push away trap thus the production cycle shorter, and do not need expensive energetic ion injection device and laser annealing apparatus, just can complete whole flow process with existing NPT-IGBT production equipment.The method of above-mentioned manufacture field cut-off type igbt, can by device requirement controlling filed cutoff layer thickness and impurity concentration, and make reduction process difficulty reduce, both improve device performance, and also reduced technology difficulty.The present invention chooses comparatively free to substrate, cut because substrate finally can be thinned, therefore chooses comparatively free, may be selected to the substrate that this is lower.
Accompanying drawing explanation
Fig. 1 is the flow chart of the present invention's wherein embodiment;
Fig. 2 is the present invention's wherein each stage view of an embodiment.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is the flow chart of one embodiment of the invention, comprising:
Step S110: substrate is provided.
Select the substrate of suitable type, P type or N-type.Because substrate finally can be thinned and cut, therefore choose comparatively free, may be selected to the substrate that this is lower.Resistance substrate rate depends on the requirement of different IGBT products, and electrical resistivity range is 0.001 ~ 200 ohm meter, and substrate thickness scope is 100 ~ 1000 microns.
Step S120: form heavily doped N-type epitaxy layer (N+), as field cutoff layer in described substrate face epitaxial growth.
The method epitaxial growth of vapour phase epitaxy is adopted to form heavily doped N-type epitaxy layer as field cutoff layer, thickness and the resistivity of field cutoff layer is determined according to the parameter of making devices, the scope of the thickness of field cutoff layer is 5 ~ 200 microns, and the scope of resistivity is 0.001 ~ 200 ohm meter.Adopt this method, thickness and all desirable field cutoff layer of concentration can be generated, improve device performance and reduce reduction process difficulty below.
Step S130: cutoff layer Epitaxial growth forms lightly doped N-type epitaxy layer (N-) in described field, as Withstand voltage layer.
The method epitaxial growth of vapour phase epitaxy is adopted to form lightly doped N-type epitaxy layer as Withstand voltage layer, thickness and the resistivity of Withstand voltage layer is determined according to the parameter of making devices, the scope of the thickness of Withstand voltage layer is 5 ~ 400 microns, and the scope of resistivity is 0.001 ~ 200 ohm meter.
Step S140: the Facad structure manufacturing described field cut-off type igbt on described Withstand voltage layer.
Conveniently NPT-IGBT manufacturing process manufactures Facad structure, and comprise grid structure, grid structure can be planar gate structure, trench gate structure, or the grid structure containing buried regions based on planar gate or trench gate.Comprise growth field oxide, photoetching active area, growth scattering oxide layer injects boron impurity simultaneously, then etching scattering oxide layer anneals and pushes away trap, photoetching emitter region, growth scattering oxide layer injects N-type impurity simultaneously, then etching scattering oxide layer anneals and pushes away trap, etching oxidation layer deposited silicon nitride, photoetching groove district also etches groove, growth gate oxide, fill polycrystalline, then etched portions polycrystalline does flatening process, polycrystalline is oxidized and removes silicon nitride, deposit passivation layer, ohmic contact injection is carried out after lithography contact hole, deposition front metal, etch front metallic pattern.
Step S150: described substrate is started from the back side carry out reduction processing.
Carry out technique for thinning back side, on thinning final position cutoff layer on the scene, field cutoff layer thickness can leave enough surpluses, when not affecting withstand voltage, thickness can be thicker, can reach 200 microns, therefore reduction process window is larger, be beneficial to control, reduce technology difficulty.
Step S160: from described thinning after substrate back carry out P type ion implantation and anneal.
Conveniently NPT-IGBT manufacturing process carries out back ion implantation and annealing process, and implanting p-type impurity forms P type collector region, and dosage and energy depend on the requirement of IGBT product parameters.
Step S170: back face metalization is carried out to described substrate back.
Conveniently NPT-IGBT manufacturing process carries out back side metallization technology, at substrate back depositing metal.The conjugation of substrate back cleannes to metal and silicon has a great impact, so need carry out evaporating front cleaning, this step can remove substrate surface natural oxidizing layer.The metal material that general back face metalization evaporation uses is titanium (TI), nickel (NI), silver (AG) three kinds, and the order of evaporation is titanium layer, nickel dam, silver layer respectively.Also can increase one deck aluminium (AL), the order of evaporation is aluminium lamination, titanium layer, nickel dam, silver layer respectively.
Fig. 2 is the present invention's wherein each stage view of an embodiment.
The method of above-mentioned manufacture field cut-off type igbt, after adopting first extension field cutoff layer, the simple method of conventional NPT-IGBT manufacturing process realizes, due to do not need to spread for a long time and push away trap thus the production cycle shorter, and do not need expensive energetic ion injection device and laser annealing apparatus, just can complete whole flow process with existing NPT-IGBT production equipment.The method of above-mentioned manufacture field cut-off type igbt, can by device requirement controlling filed cutoff layer thickness and impurity concentration, and make reduction process difficulty reduce, both improve device performance, and also reduced technology difficulty.Substrate is chosen comparatively free, cut because substrate finally can be thinned, therefore choose comparatively free, may be selected to the substrate that this is lower.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.

Claims (8)

1. manufacture a method for cut-off type igbt, comprise the following steps:
Substrate is provided;
Heavily doped N-type epitaxy layer is formed, as field cutoff layer in described substrate face epitaxial growth;
In described field, cutoff layer Epitaxial growth forms lightly doped N-type epitaxy layer, as Withstand voltage layer;
Described Withstand voltage layer manufactures the Facad structure of described field cut-off type igbt;
Described substrate is started from the back side carry out reduction processing;
From described thinning after substrate back carry out P type ion implantation and anneal;
Back face metalization is carried out to described substrate back.
2. the method for manufacture field according to claim 1 cut-off type igbt, is characterized in that, the scope of the thickness of described field cutoff layer is 5 ~ 200 microns, and the scope of resistivity is 0.001 ~ 200 ohm meter.
3. the method for manufacture field according to claim 1 cut-off type igbt, is characterized in that, the scope of the thickness of described Withstand voltage layer is 5 ~ 400 microns, and the scope of resistivity is 0.001 ~ 200 ohm meter.
4. the method for manufacture field according to claim 1 cut-off type igbt, it is characterized in that, described Facad structure comprises grid structure, and grid structure is planar gate structure, trench gate structure, or the grid structure containing buried regions based on planar gate or trench gate structure.
5. the method for manufacture field according to claim 1 cut-off type igbt, is characterized in that, described substrate is silicon, carborundum, GaAs or gallium nitride.
6. the method for manufacture field according to claim 1 cut-off type igbt, is characterized in that, in described heavy doping and light dope technique, impurity used is the impurity with donor level.
7. the method for manufacture field according to claim 6 cut-off type igbt, is characterized in that, the described impurity with donor level is phosphorus or arsenic.
8. the method for manufacture field according to claim 1 cut-off type igbt, is characterized in that, described extension is vapour phase epitaxy, liquid phase epitaxy, molecular beam epitaxy or chemical beam epitaxy.
CN201310271615.3A 2013-06-28 2013-06-28 Field stop type insulated gate bipolar transistor manufacturing method Pending CN104253043A (en)

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Application Number Priority Date Filing Date Title
CN201310271615.3A CN104253043A (en) 2013-06-28 2013-06-28 Field stop type insulated gate bipolar transistor manufacturing method

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Application Number Priority Date Filing Date Title
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Publications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140120A (en) * 2015-07-20 2015-12-09 青岛佳恩半导体有限公司 Novel IGBT preparation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140120A (en) * 2015-07-20 2015-12-09 青岛佳恩半导体有限公司 Novel IGBT preparation method
CN105140120B (en) * 2015-07-20 2018-05-01 青岛佳恩半导体有限公司 A kind of preparation method of IGBT

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Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8

Applicant after: Wuxi Huarun Shanghua Technology Co., Ltd.

Address before: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8

Applicant before: Wuxi CSMC Semiconductor Co., Ltd.

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Application publication date: 20141231