CN104241112A - Forming method of amorphous semiconductor material and forming method of metal silicide - Google Patents
Forming method of amorphous semiconductor material and forming method of metal silicide Download PDFInfo
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- CN104241112A CN104241112A CN201310232183.5A CN201310232183A CN104241112A CN 104241112 A CN104241112 A CN 104241112A CN 201310232183 A CN201310232183 A CN 201310232183A CN 104241112 A CN104241112 A CN 104241112A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 196
- 238000000034 method Methods 0.000 title claims abstract description 156
- 239000000463 material Substances 0.000 title claims abstract description 113
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 84
- 239000002184 metal Substances 0.000 title claims abstract description 84
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 39
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000000137 annealing Methods 0.000 claims abstract description 44
- 239000002912 waste gas Substances 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims description 94
- 239000007789 gas Substances 0.000 claims description 48
- 230000015572 biosynthetic process Effects 0.000 claims description 46
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 32
- 230000005855 radiation Effects 0.000 claims description 32
- 238000002360 preparation method Methods 0.000 claims description 26
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims description 16
- 239000001257 hydrogen Substances 0.000 claims description 15
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 14
- 238000001816 cooling Methods 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 239000007792 gaseous phase Substances 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 43
- 239000010703 silicon Substances 0.000 description 43
- 239000002243 precursor Substances 0.000 description 24
- 239000007769 metal material Substances 0.000 description 14
- 150000002431 hydrogen Chemical class 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000005381 potential energy Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 230000003628 erosive effect Effects 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 210000004027 cell Anatomy 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
The invention relates to a forming method of an amorphous semiconductor material and a forming method of a metal silicide. The forming method of the amorphous semiconductor material includes the steps that a semiconductor preparing layer is formed on a semiconductor substrate; ultraviolet irradiation treatment is carried out on the semiconductor preparing layer until the semiconductor preparing layer is decomposed into the amorphous semiconductor material and waste gas; the waste gas is removed; the steps of forming the semiconductor preparing layer, carrying out the ultraviolet irradiation treatment and removing the waste gas are repeated until the amorphous semiconductor material with the preset thickness is formed on the semiconductor substrate. The forming method of the metal silicide includes the steps that a semiconductor substrate is provided and comprises a source region and a drain region; metal layers are arranged on the source region and the drain region respectively; first-time annealing treatment is carried out; the amorphous semiconductor material is formed on the metal layers by adopting the forming method of the amorphous semiconductor material; second-time annealing treatment is carried out; the amorphous semiconductor material is removed. The amorphous semiconductor material can be formed at the temperature of 400 DEG C and the temperature below 400 DEG C.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of amorphous semiconductor material and the formation method of metal silicide.
Background technology
Along with the development of semiconductor technology, the range of application of amorphous semiconductor material is more and more extensive.For amorphous silicon, because it can carry out compatibility with silicon substrate well, amorphous silicon is applied in the manufacturing process of semiconductor device (as: non-crystal silicon solar cell) in large quantities.
In prior art, the formation method of amorphous silicon comprises the following steps:
Semiconductor base is provided;
SiH is formed at semiconductor substrate surface
4layer;
Heat-treat, make SiH
4layer is decomposed into amorphous Si and H being greater than at the temperature of 400 DEG C
2, concrete chemical equation is: SiH
4=Si+2H
2↑;
Remove described H
2.
Above-mentioned amorphous silicon is formed under the hot conditions more than 400 DEG C.Similarly, in prior art, other amorphous semiconductor materials are also formed all under the high temperature conditions.
Along with further developing of semiconductor technology, wish in some circumstances to form amorphous semiconductor material under the cryogenic conditions below 400 DEG C, other semiconductor layers are not had an impact to make the forming process of amorphous semiconductor material.
Therefore, how to form amorphous semiconductor material at a lower temperature and just become one of those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of amorphous semiconductor material and the formation method of metal silicide, can form amorphous semiconductor material at 400 DEG C and following temperature.
For solving the problem, the invention provides a kind of formation method of amorphous semiconductor material, comprising:
Form semiconductor preparation layers on a semiconductor substrate;
Carry out Ultraviolet radiation process to described semiconductor preparation layers, until described semiconductor preparation layers is decomposed into amorphous semiconductor material and waste gas, the temperature of described Ultraviolet radiation process is less than or equal to 400 DEG C;
Remove described waste gas;
Repeat above-mentioned formation semiconductor preparation layers, Ultraviolet radiation process and remove the step of waste gas, until form the amorphous semiconductor material of predetermined thickness on described semiconductor base.
Optionally, the temperature of described Ultraviolet radiation process is more than or equal to 20 DEG C and is less than or equal to 300 DEG C.
Optionally, described semiconductor preparation layers adopts chemical gaseous phase depositing process to be formed.
Optionally, the gas that described chemical gaseous phase depositing process adopts comprises: Si
2h
6, SiH
2cl
2(i.e. DCS), SiH
3and SiH
4in one or combination in any.
Optionally, the gas that described chemical gaseous phase depositing process adopts comprises: Ge
2h
6, GeH
3and GeH
4in one or combination in any.
Optionally, the gas that described chemical gaseous phase depositing process adopts also comprises: oxygen.
Optionally, the flow of often kind of described gas is more than or equal to 1sccm and is less than or equal to 300sccm.
Optionally, each time forming described semiconductor preparation layers is more than or equal to 0.01s and is less than or equal to 10s.
Optionally, the power of described Ultraviolet radiation process is more than or equal to 10W and is less than or equal to 1000W, and pressure is more than or equal to 0.1Torr and is less than or equal to 500Torr.
Optionally, the one in argon gas and hydrogen or combination is adopted to remove described waste gas.
Optionally, the flow of described argon gas and hydrogen is more than or equal to 1sccm and is less than or equal to 1000sccm.
Optionally, each time of removing described waste gas is more than or equal to 0.1s and is less than or equal to 10s.
Optionally, while carrying out Ultraviolet radiation process, also comprise: carry out cooling processing to described semiconductor base, the temperature of described cooling processing is more than or equal to 20 DEG C and is less than or equal to 300 DEG C.
For solving the problem, present invention also offers a kind of formation method of metal silicide, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises source region and drain region;
At least on described source region and drain region, form metal level;
Carry out first time annealing in process, described first time the temperature of annealing in process be more than or equal to 200 DEG C and be less than or equal to 400 DEG C;
The formation method of above-mentioned amorphous semiconductor material is adopted to form amorphous semiconductor material on the metal layer;
Carry out second time annealing in process, the temperature of described second time annealing in process is more than or equal to 400 DEG C and is less than or equal to 700 DEG C;
Remove described amorphous semiconductor material.
Optionally, the time of annealing in process described first time is more than or equal to 10s and is less than or equal to 20s, and the time of described second time annealing in process is more than or equal to 10s and is less than or equal to 20s.
Optionally, the thickness of described amorphous semiconductor material is more than or equal to 10 dusts and is less than or equal to 200 dusts.
Optionally, wet etching method is adopted to remove described amorphous semiconductor material.
Optionally, described amorphous semiconductor material is amorphous silicon, and described wet etching method adopts one in TMAH and KOH solution or combination.
Optionally, described Semiconductor substrate also comprises gate electrode, the material of described gate electrode is polysilicon; The formation method of described metal silicide also comprises: form described metal level on described source region and drain region while, and described gate electrode forms metal level; While form amorphous semiconductor material on described metal level, described amorphous semiconductor material is formed on the metal level on gate electrode simultaneously.
Optionally, the material of described metal level comprises nickel.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the formation method of amorphous semiconductor material provided by the invention, after forming semiconductor preparation layers on a semiconductor substrate, the heat treatment of high temperature in prior art is substituted with Ultraviolet radiation process, namely semiconductor preparation layers is made to be decomposed into amorphous semiconductor material and waste gas by carrying out Ultraviolet radiation process, when removing the amorphous semiconductor material that just can form individual layer after described waste gas on a semiconductor substrate, and then repeatedly can form the process of semiconductor preparation layers, Ultraviolet radiation process and removal waste gas.Temperature due to Ultraviolet radiation process is less than or equal to 400 DEG C, thus the forming process of whole amorphous semiconductor material is all without the need to the temperature of experience higher than 400 DEG C, finally can avoid having an impact to other semiconductor layers.
Further, while carrying out Ultraviolet radiation process, cooling processing can also be carried out to described semiconductor base, the temperature of described cooling processing is more than or equal to 20 DEG C and is less than or equal to 300 DEG C, thus can ensure further in the process forming amorphous semiconductor material, semiconductor base can be in low-temperature condition, finally can improve the performance of the semiconductor device comprising this amorphous semiconductor material.
In the formation method of metal silicide provided by the invention, carrying out the first time of low temperature to the metal level on source region and drain region after annealing in process, the formation method of above-mentioned amorphous semiconductor material is first adopted to form amorphous semiconductor material under cryogenic, to avoid metal material to diffuse to source region and drain region in the process forming amorphous semiconductor material, and then carry out the second time annealing in process of high temperature, thus in second time annealing process, metal material can diffuse in amorphous semiconductor material instead of diffuse to source region and drain region, metal material finally can be suppressed the erosion of Semiconductor substrate, improve the yield of semiconductor device.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the formation method of metal silicide in prior art;
Fig. 2 to Fig. 9 is the schematic diagram of formation method one embodiment of amorphous semiconductor material of the present invention;
Figure 10 to Figure 12 is the schematic diagram of formation method one embodiment of metal silicide of the present invention.
Embodiment
In prior art, be all form amorphous semiconductor material under the high temperature conditions, thus the development need of semiconductor technology cannot be met.
Prior art, when forming metal silicide, comprises the following steps:
Shown in figure 1, silicon substrate 60 is first provided, described silicon substrate 60 comprises source region 61 and drain region 62, described silicon substrate 60 comprises grid structure, and described grid structure comprises: be positioned at the gate dielectric layer 81 on silicon substrate 60, the metal gate electrode 82 be positioned on gate dielectric layer 81, the side wall 83 be positioned on the silicon substrate 60 of gate dielectric layer 81 and metal gate electrode 82 both sides.
Continue with reference to shown in figure 1, source region 61 is formed metal level 71, and form metal level 72 on drain region 62.
Then, first time annealing in process process is carried out, with the transition state product making metal level 71 and 72 change high resistant into.
Then, carry out second time annealing in process, thus make the transition state product of high resistant change the metal silicide of low-resistance into.
Because the temperature of second time annealing in process will far above the temperature of first time annealing in process, thus when carrying out second time annealing in process, metal material in metal level 71 and 72 (as arrow direction in Fig. 1) can corrode the silicon materials be positioned at below transistor side wall 83 downwards, and can enter in the channel region under grid structure, finally can cause transistor short circuit, semiconductor device yield is declined to a great extent.
Inventor finds through research: in the process forming metal silicide, after carrying out first time annealing in process and before carrying out second time annealing in process, first can form one deck amorphous semiconductor material (as: amorphous silicon layer) on the metal layer, potential energy due to amorphous semiconductor material is less than the potential energy of metal level, and the compactness of amorphous semiconductor material is poor, thus when carrying out second time annealing in process, metal material can remove the amorphous semiconductor material corroded above it, avoid erosion silicon substrate, finally greatly can improve the yield of semiconductor device.
When adopting the method for prior art to form amorphous semiconductor material on the metal layer, owing to being hot conditions, its temperature range is little with the temperature difference of second time annealing in process, therefore metal material will be made to diffuse in silicon substrate in the process forming amorphous semiconductor material.Based on this, be necessary to reduce the temperature forming amorphous semiconductor material, when making to form amorphous semiconductor material on the metal layer, metal material can not diffuse in silicon substrate.
Inventor finds after further research, when forming amorphous semiconductor material, the Ultraviolet radiation process that can be less than or equal to 400 DEG C by temperature replaces high-temperature heat treatment of the prior art, in this temperature range, metal material can not spread in silicon substrate, and the process namely forming amorphous semiconductor material does not all affect metal level and silicon substrate, finally when second time annealing in process, metal material changes dispersal direction, avoids the impact on silicon substrate.
The method of above-mentioned formation amorphous semiconductor material can also be applied in the process making other semiconductor device, and it does not limit the scope of the invention.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Present embodiments provide a kind of formation method of amorphous semiconductor material, for simplicity, be all described for amorphous silicon below.
Shown in figure 2, provide semiconductor base 10.
Described semiconductor base 10 can be silicon substrate, germanium silicon substrate or silicon on insulated substrate, or well known to a person skilled in the art other semiconductive material substrate.Device layer and interconnection structure etc. can also be formed with in described semiconductor base 10.
Continue with reference to shown in figure 2, semiconductor base 10 is put into reaction chamber (not shown), and carry out chemical vapor deposition method, namely in reaction chamber, pass into the precursor gas 20 of silicon, the precursor gas 20 of the described silicon of part can be adsorbed on the upper surface of semiconductor base 10, and the precursor gas 20 of the described silicon of part not to be adsorbed on semiconductor base 10 but to be in suspended state.
The precursor gas of described silicon can comprise Si
2h
6, SiH
2cl
2, SiH
3and SiH
4in one or more combination in any, in the present embodiment, the precursor gas 20 of silicon is Si
2h
6.
Can being more than or equal to 1sccm and being less than or equal to 300sccm by flow of the precursor gas 20 of described silicon, the time passing into the precursor gas 20 of described silicon can be more than or equal to 0.01s and be less than or equal to 10s.
Shown in figure 3, remove the precursor gas 20 being in the described silicon of suspended state in Fig. 2, thus only residue is adsorbed on the precursor gas 20 of the silicon of semiconductor base 10 upper surface as semiconductor preparation layers.
Particularly, the one in argon gas and hydrogen or its combination can be passed in reaction chamber, the range of flow of often kind of gas comprises 1sccm ~ 1000sccm, the time passing into gas can be 0.1s ~ 10s, thus just can remove in reaction chamber the precursor gas 20 of the silicon not being adsorbed on semiconductor base 10 upper surface.
In the present embodiment, semiconductor preparation layers is formed by adsorption, and drives the gas of no reaction out of reative cell, to carry out subsequent treatment to the semiconductor preparation layers be adsorbed on semiconductor base 10 by argon gas or hydrogen etc.
Shown in figure 4, Ultraviolet radiation process is carried out to the precursor gas 20 of remaining silicon, namely adopt the precursor gas 20 being adsorbed on the silicon of semiconductor base 10 upper surface in Ultraviolet radiation Fig. 3, until the precursor gas 20 of silicon is decomposed into amorphous silicon 21 and hydrogen 22.
The temperature of described Ultraviolet radiation process can be less than or equal to 400 DEG C, thus ensures in the process forming amorphous silicon 21, without the need to experiencing high temperature.
The temperature of the present embodiment middle-ultraviolet lamp treatment with irradiation can be more than or equal to 20 DEG C and be less than or equal to 300 DEG C, as: 20 DEG C, 70 DEG C, 100 DEG C, 180 DEG C, 250 DEG C or 300 DEG C etc., namely the precursor gas 20 of silicon can be decomposed into amorphous silicon 21 and hydrogen 22 at these tem-peratures.
Particularly, because the precursor gas 20 of silicon in the present embodiment is Si
2h
6, therefore the precursor gas 20 of silicon is decomposed into the process of amorphous silicon 21 and hydrogen 22 and is under Ultraviolet radiation: Si
2h
6=2Si+3H
2↑, wherein amorphous silicon 21 is as amorphous semiconductor material, and hydrogen 22 is as waste gas.
It should be noted that, when the precursor gas selecting other gases as silicon, waste gas may change, if the precursor gas when silicon is SiH
2cl
2time, waste gas is now HCl.
The power of described Ultraviolet radiation process can be more than or equal to 10W and be less than or equal to 1000W, and pressure can be more than or equal to 0.1Torr and be less than or equal to 500Torr.
The time of described Ultraviolet radiation process is relevant with temperature, and temperature is higher, and the time is shorter, just can stop described Ultraviolet radiation process when the precursor gas 20 of silicon is decomposed completely.
Optionally, when while carrying out Ultraviolet radiation process, can also comprise: cooling processing is carried out to described semiconductor base 10, the temperature of described cooling processing is more than or equal to 20 DEG C and is less than or equal to 300 DEG C, thus can ensure further in the process forming amorphous silicon 21, semiconductor base 10 can be in low-temperature condition, finally can improve the performance of the semiconductor device comprising this amorphous silicon 21.Described cooling processing can be water-cooled also can be air-cooled, and it does not affect protection scope of the present invention.
Shown in figure 5, remove the hydrogen 22 in Fig. 4, thus form amorphous silicon layer 30 on semiconductor base 10.
Particularly, the one in argon gas and hydrogen or its combination can be passed in reaction chamber, the range of flow of often kind of gas comprises 1sccm ~ 1000sccm, and the time passing into gas can be 0.1s ~ 10s, thus just can remove the waste gas (i.e. hydrogen 22) in reaction chamber.
The thickness being now formed in the amorphous silicon layer 30 on semiconductor base 10 is only 0.1 dust ~ 5 dust, generally can not satisfy the demands.
Shown in figure 6, pass into the precursor gas 40 of silicon in reaction chamber, the precursor gas 40 of the described silicon of part can be adsorbed on the upper surface of amorphous silicon layer 30, and the precursor gas 40 of the described silicon of part not to be adsorbed on amorphous silicon layer 30 but to be in suspended state.
Specifically can the step of reference diagram 2 correspondence, do not repeat them here.
Shown in figure 7, remove the precursor gas 40 not being adsorbed on the silicon on amorphous silicon layer 30 in Fig. 6, thus adopt chemical vapor deposition method to define semiconductor preparation layers on amorphous silicon layer 30.
Specifically can the step of reference diagram 3 correspondence, do not repeat them here.
Shown in figure 8, Ultraviolet radiation process is carried out to amorphous silicon layer 30, thus the precursor gas being adsorbed on the silicon on amorphous silicon layer 30 is decomposed into amorphous silicon 41 and hydrogen 42.
Specifically can the step of reference diagram 4 correspondence, do not repeat them here.
Shown in figure 9, remove the hydrogen 42 in Fig. 8, amorphous silicon layer 30 is formed amorphous silicon layer 50.
Specifically can the step of reference diagram 5 correspondence, do not repeat them here.
Follow-up can as required, repeat above-mentioned formation semiconductor preparation layers, Ultraviolet radiation process and remove the step one or many of waste gas, until form the amorphous silicon of predetermined thickness on described semiconductor base 10.
In other embodiments of the invention, when the amorphous semiconductor material that will be formed is amorphous germanium, the gas now when adopting chemical vapor deposition method to form semiconductor preparation layers can comprise Ge
2h
6, GeH
3and GeH
4in one or more combination in any; When the amorphous semiconductor material that will be formed is amorphous silica, the gas now when adopting chemical vapor deposition method to form semiconductor preparation layers is except comprising Si
2h
6, SiH
2cl
2, SiH
3and SiH
4in one or more combination in any outside, also need to comprise oxygen; When the amorphous semiconductor material that will be formed is amorphous oxide germanium, the gas now when adopting chemical vapor deposition method to form semiconductor preparation layers is except comprising Ge
2h
6, GeH
3and GeH
4in one or more combination in any outside, also need to comprise oxygen.
After above-described embodiment forms semiconductor preparation layers on a semiconductor substrate, the heat treatment of high temperature in prior art is substituted with Ultraviolet radiation process, namely semiconductor preparation layers is made to be decomposed into amorphous semiconductor material and waste gas by carrying out Ultraviolet radiation process, when removing the amorphous semiconductor material that just can form individual layer after described waste gas on a semiconductor substrate, and then can need to repeat to be formed the process of semiconductor preparation layers, Ultraviolet radiation process and removal waste gas.Temperature due to Ultraviolet radiation process is less than or equal to 400 DEG C, thus the forming process of whole amorphous semiconductor material is all without the need to the temperature of experience higher than 400 DEG C, finally can avoid having an impact to other semiconductor layers.
The present embodiment additionally provides a kind of formation method of metal silicide, comprises the following steps:
With reference to shown in Figure 10, provide Semiconductor substrate 100, described Semiconductor substrate 100 comprises source region 110 and drain region 120, and described Semiconductor substrate 100 comprises grid structure.
Described Semiconductor substrate 100 can be silicon substrate, germanium silicon substrate or silicon on insulated substrate, or well known to a person skilled in the art other semiconductive material substrate.In the present embodiment, Semiconductor substrate 100 comprises arbitrary transistor, and the material of the Semiconductor substrate 100 corresponding with source region in transistor 110 and drain region 120 is single-crystal semiconductor material, as: monocrystalline silicon.
Particularly, the described grid structure side wall 230 that comprises the gate dielectric layer 210 be positioned in Semiconductor substrate 100, be positioned at the gate electrode 220 on described gate dielectric layer 210 and be positioned in the Semiconductor substrate 100 of described gate dielectric layer 210 side and described gate electrode 220 side.
The material of described gate dielectric layer 210 can be silica, also can be high-k dielectric material; The material of described gate electrode 220 can be polysilicon, also can be metal material.
Gate dielectric layer 210 described in the present embodiment is high-k dielectric material, and described gate electrode 220 is metal material, thus without the need to forming metal silicide on grid structure.
It should be noted that, described grid structure also can adopt other structures, and it does not limit the scope of the invention.
Continue, with reference to shown in Figure 10, described source region 110 to form metal level 310a, and form metal level 320a on described drain region 120.
The material of described metal level 310a and 320a can be nickel, cobalt or titanium.
The 310a of metal level described in the present embodiment is nickel.Particularly, physical vapour deposition (PVD) or chemical vapour deposition (CVD) is first adopted to form nickel material in Semiconductor substrate 100 and grid structure, then etch described nickel material by selective etch technique, until only remain the nickel material on source region 110 and drain region 120, thus obtain metal level 310a and 320a.
It should be noted that, when gate electrode is polysilicon, when etching nickel material, also needing to retain the nickel material be positioned on gate electrode simultaneously.
Then, carry out first time annealing in process, described first time the temperature of annealing in process be more than or equal to 200 DEG C and be less than or equal to 400 DEG C.
The time of annealing in process described first time can be more than or equal to 10s and be less than or equal to 20s.
Described first time, the thermal creep stress of annealing in process was lower, only have the part metal level 310a adjacent with the source region 110 and part metal level 320a adjacent with drain region 120 and pasc reaction to define metal silicide after making annealing, and still have part metals to fail to react with silicon topmost.In addition, because the temperature selected is lower, the metal silicide now produced is a kind of transition state product of high resistant, as: Ni
2si, GoSi etc.
Due to first time, the temperature of annealing in process is lower, and therefore metal level 310a and metal level 320 can not corrode the silicon materials be positioned at below transistor side wall 230, and can not enter in the channel region under grid structure.
Then, with reference to shown in Figure 11, after first time annealing in process, wet-etching technology can be adopted to remove metal level 310a and 320a do not reacted with silicon, thus only leave metal silicide 310b and 320b of high resistant.
Continue, with reference to shown in Figure 11, metal silicide 310b and 320b of high resistant and the surface of grid structure to form amorphous semiconductor material 400.
Described amorphous semiconductor material 400 needs to be formed under low temperature environment (being less than or equal to 400 DEG C).Amorphous semiconductor material 400 described in the present embodiment is amorphous silicon, and it specifically can adopt the method for above-described embodiment to be formed, and now metal silicide 310b and 320b of high resistant and grid structure are as described semiconductor base, do not repeat them here.
The thickness of described amorphous semiconductor material 400 can be more than or equal to 10 dusts and be less than or equal to 200 dusts, as: 10 dusts, 50 dusts, 100 dusts, 150 dusts or 200 dusts.
Owing to only needing to form metal silicide in the present embodiment on source region 110 and drain region 120, the amorphous semiconductor material 400 therefore in the present embodiment can only be positioned on metal level 310a and metal level 320a.But when gate electrode 230 also needing form metal silicide, then amorphous semiconductor material 400 also needs to be positioned on the metal level on gate electrode 230 simultaneously.
Because the temperature now forming amorphous semiconductor material 400 is lower, the metal in metal silicide 310b and 320b of therefore high resistant can not spread downwards.
Then, shown in reference Figure 12, in order to metal silicide 310b and 320b of the high resistant formed after first time annealing in process being converted into metal silicide 310c and 320c of low-resistance, carry out second time annealing in process, the temperature of described second time annealing in process is more than or equal to 400 DEG C and is less than or equal to 700 DEG C.
The time of described second time annealing in process can be more than or equal to 10s and be less than or equal to 20s.
The temperature of described second time annealing in process is greater than the temperature of first time annealing in process, thus can form metal silicide 310c and 320c of low-resistance, as: GoSi
2, NiSi etc., the electrical contact quality of formation is better.
Although the temperature of second time annealing in process is higher, metal can spread further in second time annealing in process, but owing to being now positioned at the potential energy of potential energy much smaller than the metal silicide of high resistant of the amorphous semiconductor material 400 on metal silicide 310b and 320b of high resistant, and its compactness is poor, then potential energy is larger for the Semiconductor substrate 100 of amorphous silicon material, and quality is tightr, therefore now the dispersal direction of metal can be upwards (as shown in arrow in Figure 11), namely spread from the place that potential energy is high to the place that potential energy is low, namely diffuse in amorphous semiconductor material 400, and the silicon materials be positioned at below transistor side wall 230 can not be corroded, and can not enter in the channel region under grid structure, metal material finally can be suppressed the erosion of Semiconductor substrate 100, improve the yield of semiconductor device.
Then, continue, with reference to shown in Figure 12, to remove the amorphous semiconductor material 400 in Figure 11, thus on source region 110, form the metal silicide 310c of low-resistance, and on drain region 120, form the metal silicide 320c of low-resistance.
Particularly, wet etching method can be adopted to remove described amorphous semiconductor material 400.Amorphous semiconductor material 400 described in the present embodiment is amorphous silicon, thus can adopt the one in TMAH and KOH solution or combination as wet etching solution to remove described amorphous silicon.
The present embodiment is between twice annealing process, add the step forming amorphous semiconductor material 400 under cryogenic, thus can when second time annealing in process, metal material can be made to diffuse in amorphous semiconductor material 400 instead of diffuse to source region 110 and drain region 120, metal material finally can be suppressed the erosion of Semiconductor substrate 100, improve the yield of semiconductor device.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for amorphous semiconductor material, is characterized in that, comprising:
Form semiconductor preparation layers on a semiconductor substrate;
Carry out Ultraviolet radiation process to described semiconductor preparation layers, until described semiconductor preparation layers is decomposed into amorphous semiconductor material and waste gas, the temperature of described Ultraviolet radiation process is less than or equal to 400 DEG C;
Remove described waste gas;
Repeat above-mentioned formation semiconductor preparation layers, Ultraviolet radiation process and remove the step of waste gas, until form the amorphous semiconductor material of predetermined thickness on described semiconductor base.
2. the formation method of amorphous semiconductor material as claimed in claim 1, it is characterized in that, the temperature of described Ultraviolet radiation process is more than or equal to 20 DEG C and is less than or equal to 300 DEG C.
3. the formation method of amorphous semiconductor material as claimed in claim 1, is characterized in that, described semiconductor preparation layers adopts chemical gaseous phase depositing process to be formed.
4. the formation method of amorphous semiconductor material as claimed in claim 3, is characterized in that, the gas that described chemical gaseous phase depositing process adopts comprises: Si
2h
6, SiH
2cl
2, SiH
3and SiH
4in one or combination in any.
5. the formation method of amorphous semiconductor material as claimed in claim 3, is characterized in that, the gas that described chemical gaseous phase depositing process adopts comprises: Ge
2h
6, GeH
3and GeH
4.
6. the formation method of the amorphous semiconductor material as described in claim 4 or 5, is characterized in that, the gas that described chemical gaseous phase depositing process adopts also comprises: oxygen.
7. the formation method of the amorphous semiconductor material as described in claim 4 or 5, is characterized in that, the flow of often kind of described gas is more than or equal to 1sccm and is less than or equal to 300sccm.
8. the formation method of amorphous semiconductor material as claimed in claim 3, is characterized in that, each time forming described semiconductor preparation layers is more than or equal to 0.01s and is less than or equal to 10s.
9. the formation method of amorphous semiconductor material as claimed in claim 1, it is characterized in that, the power of described Ultraviolet radiation process is more than or equal to 10W and is less than or equal to 1000W, and pressure is more than or equal to 0.1Torr and is less than or equal to 500Torr.
10. the formation method of amorphous semiconductor material as claimed in claim 1, is characterized in that, adopts the one in argon gas and hydrogen or combination to remove described waste gas.
The formation method of 11. amorphous semiconductor materials as claimed in claim 10, it is characterized in that, the flow of described argon gas and hydrogen is more than or equal to 1sccm and is less than or equal to 1000sccm.
The formation method of 12. amorphous semiconductor materials as claimed in claim 10, is characterized in that, each time of removing described waste gas is more than or equal to 0.1s and is less than or equal to 10s.
The formation method of 13. amorphous semiconductor materials as claimed in claim 1, it is characterized in that, while carrying out Ultraviolet radiation process, also comprise: carry out cooling processing to described semiconductor base, the temperature of described cooling processing is more than or equal to 20 DEG C and is less than or equal to 300 DEG C.
The formation method of 14. 1 kinds of metal silicides, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises source region and drain region;
At least on described source region and drain region, form metal level;
Carry out first time annealing in process, described first time the temperature of annealing in process be more than or equal to 200 DEG C and be less than or equal to 400 DEG C;
The formation method of the amorphous semiconductor material according to any one of claim 1 to 13 is adopted to form amorphous semiconductor material on the metal layer;
Carry out second time annealing in process, the temperature of described second time annealing in process is more than or equal to 400 DEG C and is less than or equal to 700 DEG C;
Remove described amorphous semiconductor material.
The formation method of 15. metal silicides as claimed in claim 14, it is characterized in that, the time of annealing in process described first time is more than or equal to 10s and is less than or equal to 20s, and the time of described second time annealing in process is more than or equal to 10s and is less than or equal to 20s.
The formation method of 16. metal silicides as claimed in claim 14, it is characterized in that, the thickness of described amorphous semiconductor material is more than or equal to 10 dusts and is less than or equal to 200 dusts.
The formation method of 17. metal silicides as claimed in claim 14, is characterized in that, adopts wet etching method to remove described amorphous semiconductor material.
The formation method of 18. metal silicides as claimed in claim 14, it is characterized in that, described amorphous semiconductor material is amorphous silicon, and described wet etching method adopts one in TMAH and KOH solution or combination.
The formation method of 19. metal silicides as claimed in claim 14, is characterized in that, described Semiconductor substrate also comprises gate electrode, the material of described gate electrode is polysilicon; The formation method of described metal silicide also comprises: form described metal level on described source region and drain region while, and described gate electrode forms metal level; While form described amorphous semiconductor material on described metal level, described amorphous semiconductor material is formed on the metal level on gate electrode simultaneously.
The formation method of 20. metal silicides as claimed in claim 14, it is characterized in that, the material of described metal level comprises nickel.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779202A (en) * | 2015-04-24 | 2015-07-15 | 京东方科技集团股份有限公司 | Method for manufacturing array substrate, array substrate and display device |
| CN106024606A (en) * | 2015-03-27 | 2016-10-12 | Ap系统股份有限公司 | Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device using same |
| CN108010836A (en) * | 2017-12-12 | 2018-05-08 | 江苏博普电子科技有限责任公司 | The forming method of the short grid low square resistance value grid silicides of RF-LDMOS |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5989407A (en) * | 1982-11-15 | 1984-05-23 | Mitsui Toatsu Chem Inc | Formation of amorphous silicon film |
| CN100357500C (en) * | 2005-03-04 | 2007-12-26 | 中国科学院长春光学精密机械与物理研究所 | Method for preparing microlite silicon |
| KR20090121361A (en) * | 2007-02-27 | 2009-11-25 | 식스트론 어드밴스드 머티리얼즈 인코포레이티드 | Method for forming a film on a substrate |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024606A (en) * | 2015-03-27 | 2016-10-12 | Ap系统股份有限公司 | Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device using same |
| CN104779202A (en) * | 2015-04-24 | 2015-07-15 | 京东方科技集团股份有限公司 | Method for manufacturing array substrate, array substrate and display device |
| WO2016169202A1 (en) * | 2015-04-24 | 2016-10-27 | 京东方科技集团股份有限公司 | Method for manufacture of array substrate, array substrate, and display device |
| US10276400B2 (en) | 2015-04-24 | 2019-04-30 | Boe Technology Group Co., Ltd. | Method for fabricating array substrate, array substrate and display device |
| CN108010836A (en) * | 2017-12-12 | 2018-05-08 | 江苏博普电子科技有限责任公司 | The forming method of the short grid low square resistance value grid silicides of RF-LDMOS |
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